CN105426156A - High-performance imprecise multiplier and application method therefor - Google Patents

Abstract

The present invention discloses a high-performance imprecise multiplier and an application method therefor. The imprecise multiplier consists of an imprecise Booth encoding unit, a precise Booth encoding unit, a precise 4-2 compressor unit, an imprecise 4-2 compressor unit, an imprecise compressing tree structure, and a carry-look-ahead adder unit, wherein the precise Booth encoding unit and the precise 4-2 compressor unit are used for most significant m bits of the imprecise multiplier, and the imprecise Booth encoding unit and the imprecise 4-2 compressor unit are used for least significant N bits. When applying the present invention, in the imprecise multiplier the bits corresponding to the precise Booth encoding unit and the precise 4-2 compressor unit and the bits corresponding to the imprecise Booth encoding unit and the imprecise 4-compressor unit are determined by using a software simulation method. The high-performance imprecise multiplier is a novel multiplier with a high speed, low power consumption, and a small area, and has a very broad application prospect in the field of real-time embedded processing and other low-power consumption digital circuit design.

Description

A kind of high-performance non-precision multiplier and application process thereof

Technical field:

The present invention relates to based on non-precision circuit design field, particularly relate to a kind of high-performance non-precision multiplier and application process thereof.

Background technology:

Functional experience along with various mobile device terminal is enriched constantly and is developed, and power consumption has become a key issue of restriction Design of Digital Integrated Circuit development.Industry member changes the composite request to performance, area and power consumption into from pursuit high-performance and small size for the requirement of chip design.

Large quantity research shows that the degree of accuracy that digital integrated circuit calculates and power consumption present the relation of direct ratio, and reduce counting accuracy and can reach the effect reducing power consumption, the saving of this energy simultaneously and the reduction of power consumption are obviously.By reducing counting accuracy and realize the method for low-power consumption and design concept being called as Imprecise computation, and the difference that other technologies are maximum is before that Imprecise computation system can be by mistaketo be limited in admissible scope and not need to add any mistakecorrect or indemnifying measure.

Existing accurate multiplier is faced with the requirement of increasingly serious real-time and low-power consumption computing, in the urgent need to novelnon-precision multiplier further improve performance and reduce power consumption.

Summary of the invention:

Technical matters to be solved by this invention is for embedded real-time low-power consumption application, provides a kind of high-performance non-precision multiplier and application process thereof, this multiplier area is little, speed is high, low in energy consumption.

The present invention adopts following technical scheme: a kind of high-performance non-precision multiplier, and it comprises non-precision Booth coding unit, accurately Booth coding unit, non-precision 4-2 compressor unit, accurately 4-2 compressor unit, non-precision compression tree structure and carry lookahead adder unit;

Described accurate Booth coding unit amasss for the high-order generating portion of two operands, reduces the line number of partial product and partial product passed to compressor unit use;

Described non-precision Booth coding unit amasss for two operand low level generating portions, reduces the line number of partial product and partial product passed to compressor unit use;

Described accurate 4-2 compressor unit is that 4 of a high position Partial product compressions that weight is the same are become two, to reduce the line number of partial product, all Partial product compressions is become two row, passes to carry lookahead adder unit;

Described non-precision 4-2 compressor unit is that 4 of low level Partial product compressions that weight is the same are become two, to reduce the line number of partial product, all Partial product compressions is become two row, passes to carry lookahead adder unit;

Described non-precision tree structure is under the prerequisite using Booth coding unit, and Booth coding unit can produce one in last column of partial product and compensate position, in this structure, casts out this compensation position and reduces partial product line number to reach;

Described carry lookahead adder unit is the partial product by being compressed to two row, carries out final addition and produces final result.

Further, the high-order m bit of described non-precision multiplier uses accurate Booth coding unit and accurate 4-2 compressor unit, low level n-bit to use non-precision Booth coding unit and non-precision 4-2 compressor unit, wherein m+n=k, k are total bit number of multiplier operation number.

Further, the expression formula that in accurate Booth coding unit, partial product produces is:

${\mathrm{PP}}_j=(X_{2i}\⊕X_{2i-1})(X_{2i+1}\⊕Y_j)+\stackrel{\‾}{\left(X_{2i}\⊕X_{2i-1}\right)}\left(X_{2i+1}\⊕X_{2i}\right)\left(X_{2i+1}\⊕Y_{j-1}\right),$

And the expression formula that in non-precision Booth coding unit, partial product produces is:

${\mathrm{PP}}_j=(X_{2i}\⊕X_{2i-1})\left(X_{2i+1}{\⊕}_j\right).$

Further, C is inputted in accurate 4-2 compressor unit _in, P ₁, P ₂, P ₃, P ₄, export Sum, C _out, Carry, and be respectively with the expression formula of carry:

$Sum=P_1\⊕P_2\⊕P_3\⊕P_4\⊕P_5\⊕C_{in},$

C _out＝P ₄P ₃+P ₄P ₂+P ₃P ₂，

$Carry=\stackrel{\‾}{\left(P_2\⊕P_3\⊕P_4\right)\stackrel{\‾}{\left(P_1+C_{in}\right)}+\stackrel{\‾}{\left(P_2\⊕P_3\⊕P_4\right)\left(P_1{C}_{in}\right)}}.$

P is input as in non-precision 4-2 compressor unit ₁, P ₂, P ₃, P ₄, export as Sum ', C _out'.Be respectively with the expression formula with carry:

${\mathrm{Sum}}^{\′}=(\stackrel{\‾}{P_1\⊕P_2}+\stackrel{\‾}{P_3\⊕P_4}),$

${\mathrm{Carry}}^{\′}=\left(\stackrel{\‾}{\stackrel{\‾}{P_1{P}_2}+\stackrel{\‾}{P_3{P}_4}}\right).$

The present invention also adopts following technical scheme: a kind of application process of high-performance non-precision multiplier, uses accurate Booth coding unit, accurately 4-2 compressor unit and non-precision Booth coding unit, the figure place of non-precision 4-2 compressor unit determines to comprise following steps:

Step 1), be set to 0 by using the figure place m of accurate Booth coding unit and accurate 4-2 compressor unit in non-precision multiplier and use the figure place n of non-precision Booth coding unit and non-precision 4-2 compressor unit to be set to k;

Step 2), modeling is carried out to non-precision multiplier;

Step 3), according to concrete application data, the non-precision multiplier after modeling is emulated;

Step 4), according to the requirement evaluate simulation result of application, if the result of emulation does not meet the requirement of application, then will in non-precision multiplier, use the figure place of accurate Booth coding unit and accurate 4-2 compressor unit to increase by one, use the figure place of non-precision Booth coding unit and accurate 4-2 compressor unit to reduce one;

Step 5), repeat step 2) to step 4), until the result of emulation meets the requirement of application.

The present invention has following beneficial effect:

1., compared with multiplier before, need less hardware resource;

2. compared with multiplier before, power consumption is lower, and speed is faster.

Accompanying drawing illustrates:

fig. 1for realization of the present invention figure (for 8 × 8 non-precision multipliers);

fig. 2 is the gate leve realizing circuit figure of non-precision Booth coding unit.

fig. 3 is the gate leve realizing circuit figure of non-precision 4-2 compressor unit.

fig. 4 is non-precision Multiplier Design process flow diagram.

Embodiment:

Below in conjunction with accompanying drawingtechnical scheme of the present invention is described in further detail:

as Fig. 1shown in, high-performance non-precision multiplier of the present invention comprises non-precision Booth coding unit, accurately Booth coding unit, non-precision 4-2 compressor unit, accurately 4-2 compressor unit, non-precision compression tree structure and carry lookahead adder unit.

Wherein accurately Booth coding unit amasss for the high-order generating portion of two operands, reduces the line number of partial product and partial product passed to compressor unit use.

Wherein non-precision Booth coding unit amasss for two operand low level generating portions, reduces the line number of partial product and partial product passed to compressor unit use.

Wherein accurately 4-2 compressor unit is that 4 of a high position Partial product compressions that weight is the same are become two, and object reduces the line number of partial product, and Partial product compressions the most all becomes two row, passes to carry lookahead adder unit.

Wherein non-precision 4-2 compressor unit is that 4 of low level Partial product compressions that weight is the same are become two, and object reduces the line number of partial product, and Partial product compressions the most all becomes two row, passes to carry lookahead adder unit.

Wherein non-precision tree structure is under the prerequisite using Booth coding unit, and Booth coding unit can produce one in last column of partial product and compensate position, in this structure, casts out this compensation position and reaches the object reducing partial product line number;

Wherein carry lookahead adder unit is the partial product by being compressed to two row, carries out final addition and produces final result.

As the further prioritization scheme of high-performance non-precision multiplier of the present invention, wherein the high-order m bit of non-precision multiplier uses accurate Booth coding unit and accurate 4-2 compressor unit, low level n-bit to use non-precision Booth coding unit and non-precision 4-2 compressor unit, wherein m+n=k, k are total bit number of multiplier operation number.

As the further prioritization scheme of high-performance non-precision multiplier of the present invention, the expression formula that in accurate Booth coding unit, partial product produces is:

${\mathrm{PP}}_j=(X_{2i}\⊕X_{2i-1})(X_{2i+1}\⊕Y_j)+\stackrel{\‾}{\left(X_{2i}\⊕X_{2i-1}\right)}\left(X_{2i+1}\⊕X_{2i}\right)\left(X_{2i+1}\⊕Y_{j-1}\right),$

And the expression formula that in non-precision Booth coding unit, partial product produces is:

As the further prioritization scheme of high-performance non-precision multiplier of the present invention, in accurate 4-2 compressor unit, input C _in, P ₁, P ₂, P ₃, P ₄, export Sum, C _out, Carry, and be respectively with the expression formula of carry:

$Sum=P_1\⊕P_2\⊕P_3\⊕P_4\⊕P_5\⊕C_{in},$

C _out＝P ₄P ₃+P ₄P ₂+P ₃P ₂，

$Carry=\stackrel{\‾}{\left(P_2\⊕P_3\⊕P_4\right)\stackrel{\‾}{\left(P_1+C_{in}\right)}+\stackrel{\‾}{\left(P_2\⊕P_3\⊕P_4\right)\left(P_1{C}_{in}\right)}}.$

P is input as in non-precision 4-2 compressor unit ₁, P ₂, P ₃, P ₄, export as Sum ', C _out'.Be respectively with the expression formula with carry:

${\mathrm{Sum}}^{\′}=(\stackrel{\‾}{P_1\⊕P_2}+\stackrel{\‾}{P_3\⊕P_4}),$

${\mathrm{Carry}}^{\′}=\left(\stackrel{\‾}{\stackrel{\‾}{P_1{P}_2}+\stackrel{\‾}{P_3{P}_4}}\right).$

The invention also discloses a kind of application process based on this high-performance non-precision multiplier, wherein, use accurate Booth coding unit, accurately 4-2 compressor unit and non-precision Booth coding unit, the figure place of non-precision 4-2 compressor unit determine to comprise following steps:

Step 1), be set to 0 by using the figure place m of accurate Booth coding unit and accurate 4-2 compressor unit in non-precision multiplier and use the figure place n of non-precision Booth coding unit and non-precision 4-2 compressor unit to be set to k;

Step 2), modeling is carried out to non-precision multiplier;

Step 3), according to concrete application data, the non-precision multiplier after modeling is emulated;

Step 4), according to the requirement evaluate simulation result of application, if the result of emulation does not meet the requirement of application, then will in non-precision multiplier, use the figure place of accurate Booth coding unit and accurate 4-2 compressor unit to increase by one, use the figure place of non-precision Booth coding unit and accurate 4-2 compressor unit to reduce one;

Step 5), repeat step 2) to step 4), until the result of emulation meets the requirement of application.

Fig. 2 is the gate leve realizing circuit figure of non-precision Booth coding unit.

Fig. 3 is the gate leve realizing circuit figure of non-precision 4-2 compressor unit.

Fig. 4 is non-precision Multiplier Design process flow diagram, for determining the determination using accurate Booth coding unit, accurately 4-2 compressor unit figure place (m) in non-precision multiplier and use non-precision Booth coding unit, non-precision 4-2 compressor reducer figure place unit (n).First accurate for use Booth coding unit, accurately 4-2 compressor unit figure place are set to 0, then with softwares such as C or Matlab, modeling is carried out to non-precision multiplier, then with the non-precision multiplier after software modeling, emulate for different practical applications.If simulation result is undesirable, then increase the figure place using accurate Booth coding unit, accurately 4-2 compressor unit, then the step of software modeling and emulation is repeated until the design of finding symbol to require, the optimal design that namely n=k-m of the now figure place m of pinpoint totalizer, and correspondence accords with and require.

More than just the preferred embodiment of the present invention is described.Concerning those skilled in the art, other advantage and distortion can be associated easily according to above embodiment.Therefore, the present invention is not limited to above-mentioned embodiment, and it carries out detailed, exemplary explanation as just example to a kind of form of the present invention.Not deviating from the scope of present inventive concept, the usual change that those of ordinary skill in the art carry out in the aspects of the technology of the present invention and replacement, all should be included within protection scope of the present invention.

Claims (5)

1. a high-performance non-precision multiplier, is characterized in that: comprise non-precision Booth coding unit, accurately Booth coding unit, non-precision 4-2 compressor unit, accurately 4-2 compressor unit, non-precision compression tree structure and carry lookahead adder unit;

Described accurate Booth coding unit amasss for the high-order generating portion of two operands, reduces the line number of partial product and partial product passed to compressor unit use;

Described non-precision Booth coding unit amasss for two operand low level generating portions, reduces the line number of partial product and partial product passed to compressor unit use;

Described accurate 4-2 compressor unit is that 4 of a high position Partial product compressions that weight is the same are become two, to reduce the line number of partial product, all Partial product compressions is become two row, passes to carry lookahead adder unit;

Described non-precision 4-2 compressor unit is that 4 of low level Partial product compressions that weight is the same are become two, to reduce the line number of partial product, all Partial product compressions is become two row, passes to carry lookahead adder unit;

Described non-precision tree structure is under the prerequisite using Booth coding unit, and Booth coding unit can produce one in last column of partial product and compensate position, in this structure, casts out this compensation position and reduces partial product line number to reach;

Described carry lookahead adder unit is the partial product by being compressed to two row, carries out final addition and produces final result.

2. high-performance non-precision multiplier as claimed in claim 1, it is characterized in that: the high-order m bit of described non-precision multiplier uses accurate Booth coding unit and accurate 4-2 compressor unit, low level n-bit to use non-precision Booth coding unit and non-precision 4-2 compressor unit, wherein m+n=k, k are total bit number of multiplier operation number.

3. high-performance non-precision multiplier as claimed in claim 1, is characterized in that: the expression formula that accurately in Booth coding unit, partial product produces is:

${\mathrm{PP}}_j=(X_{2i}\⊕X_{2i-1})(X_{2i+1}\⊕Y_j)+\stackrel{\‾}{(X_{2i}\⊕X_{2i-1})}\left(X_{2i+1}\⊕X_{2i}\right)\left(X_{2i+1}\⊕Y_{j-1}\right),$

And the expression formula that in non-precision Booth coding unit, partial product produces is:

${\mathrm{PP}}_j=\left(X_{2i}\⊕X_{2i-1}\right)\left(X_{2i+1}\⊕Y_j\right).$

4. high-performance non-precision multiplier as claimed in claim 1, is characterized in that: accurately input C in 4-2 compressor unit _in, P ₁, P ₂, P ₃, P ₄, export Sum, C _out, Carry, and be respectively with the expression formula of carry:

$Sum=P_1\⊕P_2\⊕P_3\⊕P_4\⊕P_5\⊕C_{in},$

C _out＝P ₄P ₃+P ₄P ₂+P ₃P ₂，

$Carry=\stackrel{\‾}{(P_2\⊕P_3\⊕P_4)\stackrel{\‾}{(P_1-C_{in})}-\stackrel{\‾}{(P_2\⊕P_3\⊕P_4)\left(P_1{C}_{in}\right)}}.$

P is input as in non-precision 4-2 compressor unit ₁, P ₂, P ₃, P ₄, export as Sum ', C _out'.Be respectively with the expression formula with carry:

${\mathrm{Sum}}^{\′}=(\stackrel{\‾}{P_1\⊕P_2}+\stackrel{\‾}{P_3\⊕P_4}),$

${\mathrm{Carry}}^{\′}=\stackrel{\‾}{(\stackrel{\‾}{P_1{P}_2}+\stackrel{\‾}{P_3{P}_4})}.$

5. an application process for high-performance non-precision multiplier, is characterized in that: use accurate Booth coding unit, accurately 4-2 compressor unit and non-precision Booth coding unit, the figure place of non-precision 4-2 compressor unit determines to comprise following steps

Step 1), be set to 0 by using the figure place m of accurate Booth coding unit and accurate 4-2 compressor unit in non-precision multiplier and use the figure place n of non-precision Booth coding unit and non-precision 4-2 compressor unit to be set to k;

Step 2), modeling is carried out to non-precision multiplier;

Step 3), according to concrete application data, the non-precision multiplier after modeling is emulated;

Step 4), according to the requirement evaluate simulation result of application, if the result of emulation does not meet the requirement of application, then will in non-precision multiplier, use the figure place of accurate Booth coding unit and accurate 4-2 compressor unit to increase by one, use the figure place of non-precision Booth coding unit and accurate 4-2 compressor unit to reduce one;

Step 5), repeat step 2) to step 4), until the result of emulation meets the requirement of application.