CN105426156B - A kind of non-precision multiplier of high-performance and its application process - Google Patents
A kind of non-precision multiplier of high-performance and its application process Download PDFInfo
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- CN105426156B CN105426156B CN201510712638.2A CN201510712638A CN105426156B CN 105426156 B CN105426156 B CN 105426156B CN 201510712638 A CN201510712638 A CN 201510712638A CN 105426156 B CN105426156 B CN 105426156B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
Abstract
The invention discloses a kind of non-precision multiplier of high-performance and its application processes, the non-precision multiplier is made of non-precision Booth coding units, accurate Booth coding units, accurate 42 compressor unit, non-precision 42 compressor unit, non-precision compression tree and carry lookahead adder unit, wherein it is using non-precision Booth coding units and 42 non-precision compressor units that the high-order m bits of non-precision multiplier, which are using accurate Booth coding units and accurate 42 compressor unit, the n-bit of low level,.In the application present invention, need to determine by the method for software emulation using the digit of accurate Booth coding units and accurate 42 compressor unit and using the digit of non-precision Booth coding units and non-precision 42 compressor unit in non-precision multiplier.The present invention is the multiplier of a kind of novel high speed, low-power consumption, small area, has very wide application prospect in real-time embedded processing and other low-power consumption digital circuit design fields.
Description
Technical field：
The present invention relates to based on non-precision circuit design field more particularly to a kind of non-precision multiplier of high-performance and its answer
Use method.
Background technology：
As the functional experience of various mobile device terminals is enriched constantly and develops, power consumption has become restriction digital integration
One critical issue of circuit design development.Industrial quarters has turned the requirement that chip designs from pursuit high-performance and small area
Become the composite request to performance, area and power consumption.
Numerous studies show that the accuracy that digital integrated electronic circuit calculates and power consumption show the relationship of direct ratio, reduce and calculate essence
Exactness can achieve the effect that reduce power consumption, while the saving of this energy and the reduction of power consumption are obviously.Pass through reduction
Counting accuracy is referred to as Imprecise computation come the method and design concept for realizing low-power consumption, and other technologies are maximum not before
It is entangled with being that mistake can be limited in permissible range and need not add any mistake by Imprecise computation system
Just or indemnifying measure.
Existing accurate multiplier is faced with the requirement of increasingly serious real-time and low-power consumption operation, and there is an urgent need to novel
Non-precision multiplier further improves performance and reduces power consumption.
Invention content：
The technical problem to be solved by the present invention is to be directed to embedded real-time low-power consumption application, a kind of non-essence of high-performance is provided
True multiplier and its application process, the multiplier area is small, speed is high, low in energy consumption.
The present invention adopts the following technical scheme that：A kind of non-precision multiplier of high-performance, including non-precision Booth codings are single
First, accurate Booth coding units, accurate 4-2 compressor units, non-precisely compress tree structure at non-precision 4-2 compressor units
And carry lookahead adder unit；
The accurate Booth coding units are accumulated for two operand high position generating portions, and the line number of partial product is reduced
And partial product is passed to compressor unit to use；
The non-precision Booth coding units are accumulated for two operand low level generating portions, and the row of partial product is reduced
It counts and partial product is passed into compressor unit and use；
The accurate 4-2 compressor units are by the same Partial product compression of 4 high-order weights into two, to reduce portion
The line number of product is divided to pass to carry lookahead adder unit by all Partial product compressions at two rows；
The non-precision 4-2 compressor units are by the same Partial product compression of 4 weights of low level into two, to reduce
The line number of partial product passes to carry lookahead adder unit by all Partial product compressions at two rows；
The non-precision tree structure is under the premise of with Booth coding units, and Booth coding units can be in part
Long-pending last column generates a compensation position and casts out the compensation position in this structure to reach and reduce partial product line number；
The carry lookahead adder unit is the partial product that will be compressed to two rows, carries out final be added and generates final knot
Fruit.
Further, the high-order m bits of the non-precision multiplier are pressed using accurate Booth coding units and accurate 4-2
Contracting device unit, low level n-bit are using non-precision Booth coding units and non-precision 4-2 compressor units, wherein m+n=k, k
The total bit number of multiplier operation number.
Further, the expression formula of partial product generation is in accurate Booth coding units：
And the expression formula that non-precisely partial product generates in Booth coding units is：
Further, C is inputted in accurate 4-2 compressor unitsin, P1, P2, P3, P4, output and position and carry Sum, Cout,
The expression formula of Carry and position and carry is respectively：
Cout=P4P3+P4P2+P3P2,
Input is P in non-precision 4-2 compressor units1, P2, P3, P4, export as Sum ', Carry, expression formula is respectively：
The present invention also adopts the following technical scheme that：A kind of application process of the non-precision multiplier of high-performance, using accurate
The position of Booth coding units, accurate 4-2 compressor units and non-precision Booth coding units, non-precision 4-2 compressor units
Number determination comprises the steps of
Step 1) will use the digit of accurate Booth coding units and accurate 4-2 compressor units in non-precision multiplier
M is set as 0 and is set as k using the digit n of non-precision Booth coding units and non-precision 4-2 compressor units；
Step 2) models non-precision multiplier, accurate Booth coding units, accurate 4-2 will be used to compress first
Device unit digit is set as 0, is then modeled to non-precision multiplier with softwares such as C or Matlab；
Step 3) emulates the non-precision multiplier after modeling using data according to specific；
Step 4) assesses simulation result according to the requirement of application, will if the result of emulation does not meet the requirement of application
Increase by one using the digit of accurate Booth coding units and accurate 4-2 compressor units in non-precision multiplier, uses non-essence
The digit of true Booth coding units and accurate 4-2 compressor units reduces one；
Step 5) repeats step 2) to step 4), until the result of emulation meets the requirement of application.
The present invention has the advantages that：
1. compared with multiplier before, less hardware resource is needed；
2. compared with multiplier before, power consumption is lower, and speed is faster.
Description of the drawings：
Fig. 1 is the realization figure of the present invention (by taking 8 × 8 non-precision multipliers as an example)；
Fig. 2 is that the gate leve of non-precision Booth coding units realizes circuit diagram.
Fig. 3 is that the gate leve of non-precision 4-2 compressor units realizes circuit diagram.
Fig. 4 is non-precision Multiplier Design flow chart.
Specific implementation mode：
Technical scheme of the present invention is described in further detail below in conjunction with the accompanying drawings：
As shown in Figure 1, the non-precision multiplier of high-performance of the present invention includes non-precision Booth coding units, accurate Booth volumes
Code unit, non-precision 4-2 compressor units, accurate 4-2 compressor units, non-precisely compression tree structure and carry look ahead add
Multiplier unit.
Wherein accurate Booth coding units are accumulated for two operand high position generating portions, and the line number of partial product is reduced
And partial product is passed to compressor unit to use.
Wherein non-precision Booth coding units are accumulated for two operand low level generating portions, and the row of partial product is reduced
It counts and partial product is passed into compressor unit and use.
Wherein accurate 4-2 compressor units are by the same Partial product compression of 4 high-order weights into two, it is therefore an objective to be subtracted
The line number of small part product, finally passes to carry lookahead adder unit by all Partial product compressions at two rows.
Wherein non-precision 4-2 compressor units are by the same Partial product compression of 4 weights of low level into two, it is therefore an objective to
The line number for reducing partial product, finally passes to carry lookahead adder unit by all Partial product compressions at two rows.
Wherein non-precision tree structure is under the premise of with Booth coding units, and Booth coding units can be in part
Long-pending last column generates a compensation position, in this structure, casts out the compensation position and achievees the purpose that reduce partial product line number；
Wherein carry lookahead adder unit is the partial product that will be compressed to two rows, carries out final be added and generates final knot
Fruit.
As the further prioritization scheme of the non-precision multiplier of high-performance of the present invention, wherein the high-order m of non-precision multiplier
Bit uses non-precision Booth coding units using accurate Booth coding units and accurate 4-2 compressor units, low level n-bit
With non-precision 4-2 compressor units, wherein m+n=k, k are the total bit number of multiplier operation number.
As the further prioritization scheme of the non-precision multiplier of high-performance of the present invention, part in accurate Booth coding units
Accumulating the expression formula generated is：
And the expression formula that non-precisely partial product generates in Booth coding units is：
As the further prioritization scheme of the non-precision multiplier of high-performance of the present invention, inputted in accurate 4-2 compressor units
Cin, P1, P2, P3, P4, export Sum, Cout, Carry, and be respectively with the expression formula of carry：
Cout=P4P3+P4P2+P3P2,
Input is P in non-precision 4-2 compressor units1, P2, P3, P4, export as Sum ', Carry.With the expression with carry
Formula is respectively：
The invention also discloses a kind of application processes based on the non-precision multiplier of the high-performance, wherein using accurate
The position of Booth coding units, accurate 4-2 compressor units and non-precision Booth coding units, non-precision 4-2 compressor units
Number determination comprises the steps of：
Step 1) will use the digit of accurate Booth coding units and accurate 4-2 compressor units in non-precision multiplier
M is set as 0 and is set as k using the digit n of non-precision Booth coding units and non-precision 4-2 compressor units；
Step 2) models non-precision multiplier；
Step 3) emulates the non-precision multiplier after modeling using data according to specific；
Step 4) assesses simulation result according to the requirement of application, will if the result of emulation does not meet the requirement of application
Increase by one using the digit of accurate Booth coding units and accurate 4-2 compressor units in non-precision multiplier, uses non-essence
The digit of true Booth coding units and accurate 4-2 compressor units reduces one；
Step 5) repeats step 2) to step 4), until the result of emulation meets the requirement of application.
Fig. 2 is that the gate leve of non-precision Booth coding units realizes circuit diagram.
Fig. 3 is that the gate leve of non-precision 4-2 compressor units realizes circuit diagram.
Fig. 4 is non-precision Multiplier Design flow chart, and list is encoded using accurate Booth for determining in non-precision multiplier
First, accurate 4-2 compressor unit digits (m) and the non-precision Booth coding units of use, non-precision 4-2 compressor reducers digit list
The determination of first (n).Accurate Booth coding units, accurate 4-2 compressor units digit will be used to be set as 0 first, then use C or
The softwares such as person Matlab model non-precision multiplier, then with the non-precision multiplier after software modeling, for difference
Practical application emulated.If simulation result is undesirable, increase using accurate Booth coding units, accurate 4-2
The digit of compressor unit, then repeatedly software modeling and the design until finding symbol requirement the step of emulation, at this time accurately
The digit m and corresponding n=k-m for pinpointing adder are the optimal design for according with and requiring.
It is above that only the preferred embodiment of the present invention is described.Those skilled in the art are come
It says, other advantages and deformation can easily be associated according to embodiment of above.Therefore, the invention is not limited in upper
Embodiment is stated, detailed, exemplary explanation is carried out to a kind of form of the present invention as just example.Without departing substantially from this hair
In the range of bright objective, what those of ordinary skill in the art carried out in the aspects of the technology of the present invention usually changes and replaces
It changes, should all be included within protection scope of the present invention.
Claims (5)
1. a kind of non-precision multiplier of high-performance, it is characterised in that：It is encoded including non-precision Booth coding units, accurate Booth
Unit, non-precision 4-2 compressor units, accurate 4-2 compressor units, non-precisely compression tree structure and carry lookahead adder
Device unit；
The accurate Booth coding units are accumulated for two operand high position generating portions, reduce the line number of partial product and
Partial product is passed to compressor unit to use；
The non-precision Booth coding units are accumulated for two operand low level generating portions, reduce the line number of partial product simultaneously
And partial product is passed into compressor unit and is used；
The accurate 4-2 compressor units are by the same Partial product compression of 4 high-order weights into two, to reduce partial product
Line number pass to carry lookahead adder unit by all Partial product compressions at two rows；
The non-precision 4-2 compressor units are by the same Partial product compression of 4 weights of low level into two, to reduce part
Long-pending line number passes to carry lookahead adder unit by all Partial product compressions at two rows；
The non-precision compression tree structure is under the premise of with Booth coding units, and Booth coding units can be in part
Long-pending last column generates a compensation position and casts out the compensation position in this structure to reach and reduce partial product line number；
The carry lookahead adder unit is the partial product that will be compressed to two rows, carries out final be added and generates final result.
2. the non-precision multiplier of high-performance as described in claim 1, it is characterised in that：The high-order m of the non-precision multiplier
Bit uses non-precision Booth coding units using accurate Booth coding units and accurate 4-2 compressor units, low level n-bit
With non-precision 4-2 compressor units, wherein m+n=k, k are the total bit number of multiplier operation number.
3. the non-precision multiplier of high-performance as described in claim 1, it is characterised in that：Part in accurate Booth coding units
Accumulating the expression formula generated is：
And the expression formula that non-precisely partial product generates in Booth coding units is：
4. the non-precision multiplier of high-performance as described in claim 1, it is characterised in that：It is inputted in accurate 4-2 compressor units
Cin, P1, P2, P3, P4, output and position Sum and carry Cout, Carry, Sum and Cout, Carry expression formula be respectively：
Cout=P4P3+P4P2+P3P2,
Input is P in non-precision 4-2 compressor units1, P2, P3, P4, output be and position Sum ＇ and carry Carry ', Sum ＇ and
The expression formula of Carry ' is respectively：
5. a kind of application process of the non-precision multiplier of high-performance, it is characterised in that：Using accurate Booth coding units, accurately
The digit determination of 4-2 compressor units and non-precision Booth coding units, non-precision 4-2 compressor units comprises the steps of
Step 1) will be set in non-precision multiplier using the digit m of accurate Booth coding units and accurate 4-2 compressor units
For 0 k is set as using the digit n of non-precision Booth coding units and non-precision 4-2 compressor units；
Step 2) models non-precision multiplier, will use accurate Booth coding units, accurate 4-2 compressor reducers list first
The digit of member is set as 0, is then modeled to non-precision multiplier with softwares such as C or Matlab；
Step 3) emulates the non-precision multiplier after modeling using data according to specific；
Step 4) assesses simulation result according to the requirement of application, if the result of emulation does not meet the requirement of application, by non-essence
Increase by one using the digit of accurate Booth coding units and accurate 4-2 compressor units in true multiplier, using non-precision
The digit of Booth coding units and accurate 4-2 compressor units reduces one；
Step 5) repeats step 2) to step 4), until the result of emulation meets the requirement of application.
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| CN108256642B (en) * | 2016-12-29 | 2021-08-31 | 上海寒武纪信息科技有限公司 | Circuit design method for non-precise calculation neural network |
| CN106775577B (en) * | 2017-01-03 | 2019-05-14 | 南京航空航天大学 | A kind of design method of the non-precision redundant manipulators multiplier of high-performance |
| CN109542393B (en) * | 2018-11-19 | 2022-11-04 | 电子科技大学 | Approximate 4-2 compressor and approximate multiplier |
| CN111966323B (en) * | 2020-08-18 | 2022-09-13 | 合肥工业大学 | Approximate multiplier based on unbiased compressor and calculation method |
| CN112286490B (en) * | 2020-11-11 | 2024-04-02 | 南京大学 | Hardware architecture and method for loop iteration multiply-add operation |
| CN113655991B (en) * | 2021-07-27 | 2024-04-30 | 南京航空航天大学 | Approximate 2-bit multiplier and large-scale multiplier |
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| CN101650642A (en) * | 2009-09-11 | 2010-02-17 | 杭州中天微系统有限公司 | Floating point addition device based on complement rounding |
| CN104238992A (en) * | 2014-09-09 | 2014-12-24 | 南京航空航天大学 | High-performance imprecise floating point adder and application method thereof |
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| US6978426B2 (en) * | 2002-04-10 | 2005-12-20 | Broadcom Corporation | Low-error fixed-width modified booth multiplier |
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| CN101650642A (en) * | 2009-09-11 | 2010-02-17 | 杭州中天微系统有限公司 | Floating point addition device based on complement rounding |
| CN104238992A (en) * | 2014-09-09 | 2014-12-24 | 南京航空航天大学 | High-performance imprecise floating point adder and application method thereof |
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