CN101304015B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN101304015B CN101304015B CN2008100887838A CN200810088783A CN101304015B CN 101304015 B CN101304015 B CN 101304015B CN 2008100887838 A CN2008100887838 A CN 2008100887838A CN 200810088783 A CN200810088783 A CN 200810088783A CN 101304015 B CN101304015 B CN 101304015B
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- supporting mass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like from infiltrating into it to attain high reliability by covering a side surface of a semiconductor chip with a thick protection layer. This invention also offers a highly productive manufacturing method of semiconductor devices by which a supporter bonded to semiconductor dice is etched from a back surface-side of the supporter so that the semiconductor devices can be separated without dicing.
Description
Technical field
The present invention relates to semiconductor device and manufacturing approach thereof, particularly use CSP (the Chip Size Package: chip size packages) type semiconductor device and manufacturing approach thereof of supporting mass.
Background technology
In recent years, as new encapsulation technology CSP by extensive concern.So-called CSP is meant the compact package that has with the profile approximate same size profile of semiconductor chip.As CSP a kind of known BGA (Ball Grid Array: the semiconductor device of type BGA) is arranged.The BGA type semiconductor device is a plurality of spherical terminals that are made up of metal materials such as scolding tin of configuration on the face of a side that encapsulates.
Require the semiconductor chip slimming in order to improve packing density, in order to satisfy this requirement, need be with the semiconductor substrate attenuation.But if the semiconductor substrate attenuation, then in manufacturing process since intensity reduce and produce warpage or breakage and can not transport.Therefore, a face of supporting mass such as glass substrate or boundary belt and semiconductor substrate is fitted, the face of the supporting mass of not fitting is carried out grinding make the semiconductor substrate attenuation.
Figure 29 is the summary section of the semiconductor device that possesses supporting mass of the existing BGA type of expression.Forms (Charge CoupledDevice: the semiconductor integrated circuit 101 that constitutes of element such as type imageing sensor or CMOS type imageing sensor charge coupled device), and the pad electrode 102 that is electrically connected with semiconductor integrated circuit 101 via dielectric film 103 formation by CCD on 100 surfaces such as the semiconductor substrate that constitutes by silicon (Si) etc.Pad electrode 102 is covered by the passivating film 104 that is made up of silicon nitride film etc.
Supporting masses such as glass substrate 105 are fitted on the surface of semiconductor substrate 100 via the adhesive linkage 106 of formations such as epoxy resin.In order in manufacturing process, to keep the semiconductor substrate 100 of slimming securely; Also in order to prevent supporting mass 105 self warpage and breakage; Supporting mass 105 thicker formation, when for example the thickness of the semiconductor substrate after the slimming 100 was the 100 μ m left and right sides, the thickness of supporting mass 105 was about 400 μ m.
On the side of semiconductor substrate 100 and the back side, form the dielectric film 107 that constitutes by silicon oxide film and silicon nitride film etc.The wiring layer 108 that will be electrically connected with pad electrode 102 is formed on the dielectric film 107 along the side and the back side of semiconductor substrate 100.The protective layer 109 that formation is made up of anti-solder flux etc. covers dielectric film 107 and wiring layer 108.Regulation zone at protective layer 109 forms peristome, and forms the spherical conducting terminal 110 that is electrically connected with wiring layer 108 through this peristome.
Pass through the line of cut DL that promptly stipulates along the border of each semiconductor device and use cutter that supporting mass 105 and protective layer 109 grades are cut into single operation (so-called cutting action), produce this semiconductor device.
Above-mentioned technology is for example on the books in following patent documentation.
Patent documentation 1: TOHKEMY 2006-93367 communique
Though above-mentioned semiconductor device has protective layer 109; Cover the wiring layer 108 that is connected with pad electrode 102; But a little less than the moisture-proof by contact site, the problem on dangerous such reliability that supporting mass 105 peels off from semiconductor element is arranged with protective layer 109 that hygroscopic resin constitutes and adhesive linkage 106 and supporting mass etc.
Along with precision machined progress, the number of chips of every wafer increases, and also increases for the quantity of the line of cut D1 of a wafer.Therefore will above-mentioned line of cut DL singly the existing manufacturing approach of cutting also have cutting action and need the problem that the time grows.When particularly that the such rigidity of glass substrate is high substrate uses as supporting mass 105, be difficult to supporting mass 105 is cut off, this also is that cutting action needs one of long reason of time.And require e-machine multifunction and slimming more.
Summary of the invention
The object of the present invention is to provide the high semiconductor device of a kind of reliability, its further purpose is to provide a kind of manufacturing approach of semiconductor device that simpleization of manufacturing process and productivity is good, and, also to seek the slim purpose that turns to of semiconductor device.
The present invention develops in view of above-mentioned problem, and its main feature is following.Be that semiconductor device of the present invention comprises: be connected with circuit element in the semiconductor chip and be formed near the metal pad the side surface part on this semiconductor chip; Be formed on the side surface part of said semiconductor chip and the dielectric film of back side portion; Connect with the back side of said metal pad and with said dielectric film mutually ground connection from the side surface part of the said semiconductor chip facial metal wiring that extends of supporting or opposing; With the side surface part of said semiconductor chip and back side portion landfill and the protective layer that forms; The conducting terminal that is electrically connected with said metal wiring via the peristome of said protective layer formation.
Said protective layer is made up of first protective layer and second protective layer.
Have will comprise said metal pad and carry out bonding supporting mass in the mode of the surface element covering of interior said semiconductor chip.
Close other semiconductor device on said semiconductor device upper strata, the said protective layer of upside semiconductor device and the semiconductor device of downside are joined.
And semiconductor device of the present invention comprises: be connected with circuit element in the semiconductor chip and be formed near the metal pad the side surface part on this semiconductor chip; Be formed on the side surface part of said semiconductor chip and the dielectric film of back side portion; Connect with the back side of said metal pad and with said dielectric film mutually ground connection from the side surface part of the said semiconductor chip facial metal wiring that extends of supporting or opposing; The protective layer that the side surface part of said semiconductor chip and back side portion form; The conducting terminal that is connected with said metal wiring via the peristome that is formed on said protective layer; Be formed on the said protective layer and with the conductive film of the side surface part landfill of said semiconductor chip.
Said semiconductor device has will comprise the mode bonding supporting mass of said metal pad in the surface element covering of interior said semiconductor chip.
The manufacturing approach of semiconductor device of the present invention comprises: prepare to be formed with via first dielectric film semiconductor substrate of metal pad, and will comprise the operation that said metal pad is fitted on the surface of the face side of interior said semiconductor substrate and supporting mass; Remove a part and operation that said first dielectric film is exposed from the rear side of said semiconductor substrate; Form the operation of second dielectric film at the whole back side of said semiconductor substrate; The operation of removing the part of said first and second dielectric films and said metal pad being exposed; Form and to be connected with the back side of said metal pad and to the operation of the metal wiring of the back side of said semiconductor substrate extension; Remove the part of said semiconductor substrate and form the operation that arrives said supporting mass thickness direction groove midway on the surface of said supporting mass; The whole back side landfill that will comprise the said semiconductor substrate of said groove forms the operation of protective layer; The operation of the conducting terminal that formation is electrically connected with said metal wiring via the peristome of said protective layer formation.
The operation that forms said protective layer has the operation that after forming first protective layer, on this first protective layer, forms second protective layer.
The manufacturing approach of semiconductor device of the present invention comprises: prepare to be formed with via first dielectric film semiconductor substrate of metal pad, and will comprise the operation of face side and the surface applying of supporting mass of the said semiconductor substrate of said metal pad; Its part is removed and operation that said first dielectric film is exposed from the rear side of said semiconductor substrate; Form the operation of second dielectric film at the whole back side of said semiconductor substrate; The operation of removing the part of said first and second dielectric films and said metal pad being exposed; Form and to be connected with the back side of said metal pad and to the operation of the metal wiring of the back side of said semiconductor substrate extension; Remove the part of said semiconductor substrate and form the operation that arrives said supporting mass thickness direction groove midway on the surface of said supporting mass; Form the operation of first protective layer in the rear side of the said semiconductor substrate that comprises said groove; The operation of the conducting terminal that formation is electrically connected with said metal wiring via the peristome of said first protective layer formation; On said first protective layer, form the operation of second protective layer.
Form in the operation of said protective layer or said first protective layer and be coated with casting resin.
Form in the operation of said second protective layer and be coated with conductive material.
Has operation with said supporting mass filmization.And has the operation that said supporting mass is removed.
The manufacturing approach of semiconductor device of the present invention comprises: the operation of being fitted in the surface of the face side of wafer-like semiconductor substrate and supporting mass; The operation that the part of said semiconductor substrate is removed; Surface at said supporting mass forms the operation that arrives said supporting mass thickness direction groove midway; Expose from the back side of said supporting mass up to said groove at the back side of the said supporting mass of etching, through cutting apart the operation that said supporting mass obtains each semiconductor device.
The manufacturing approach of semiconductor device of the present invention comprises: the face side of wafer-like semiconductor substrate fit band and said with on the fit operation on said supporting mass surface; The operation that the part of said semiconductor substrate is removed; Form the operation of the thickness direction groove midway that arrives said band at the face of the said semiconductor substrate side of said band; Formation is formed on the operation that has the protective layer of peristome on side and the back side of said semiconductor substrate and in the position corresponding with said groove; The operation that expose from the rear side of said supporting mass up to said band at the back side of the said supporting mass of etching; Supply with lytic agent and said band is peeled off from said semiconductor substrate to the said band that exposes, and obtain the operation of each semiconductor device through separating said semiconductor substrate and said supporting mass.
The manufacturing approach of semiconductor device of the present invention comprises: the operation of being fitted in the surface of the face side of wafer-like semiconductor substrate and supporting mass; The operation that the part of said semiconductor substrate is removed; Surface at said supporting mass forms the operation that arrives said supporting mass thickness direction groove midway; At least the position corresponding at the said supporting mass of the etching back side and make the operation with the thickness attenuation of the supporting mass of said groove correspondence position with said groove; Through said supporting mass being cut apart the operation that obtains each semiconductor device along said groove to said supporting mass loading.
According to the present invention,, the semiconductor device of comparing the moisture-proof raising with existing structure can be provided owing to formed protective layer with whole semiconductor chip landfill.According to the present invention and since not one by one the cutting line of cut just can obtain the semiconductor device of singualtion with single treatment, so can shorten the needed time of cutting action significantly, can improve productivity.Owing to have supporting mass carried out the operation of filmization or the operation that supporting mass is removed, so can be with the semiconductor device slimming.
Description of drawings
Fig. 1 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 2 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 3 A, B are the profiles of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 4 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 5 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 6 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 7 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 8 is the profile of explanation first embodiment of the invention manufacturing method for semiconductor device;
Fig. 9 is the profile of explanation second embodiment of the invention manufacturing method for semiconductor device;
Figure 10 is the profile of explanation second embodiment of the invention manufacturing method for semiconductor device;
Figure 11 is the profile of explanation third embodiment of the invention manufacturing method for semiconductor device;
Figure 12 is the profile of explanation fourth embodiment of the invention manufacturing method for semiconductor device;
Figure 13 is the profile of explanation fifth embodiment of the invention manufacturing method for semiconductor device;
Figure 14 is the profile of explanation sixth embodiment of the invention manufacturing method for semiconductor device;
Figure 15 is the profile of explanation seventh embodiment of the invention manufacturing method for semiconductor device;
Figure 16 is the profile of explanation seventh embodiment of the invention manufacturing method for semiconductor device;
Figure 17 is the profile of explanation seventh embodiment of the invention manufacturing method for semiconductor device;
Figure 18 is the profile of explanation seventh embodiment of the invention manufacturing method for semiconductor device;
Figure 19 is the profile of explanation eighth embodiment of the invention manufacturing method for semiconductor device;
Figure 20 is the profile of explanation nineth embodiment of the invention manufacturing method for semiconductor device;
Figure 21 is the profile of explanation nineth embodiment of the invention manufacturing method for semiconductor device;
Figure 22 is the profile of explanation nineth embodiment of the invention manufacturing method for semiconductor device;
Figure 23 is the profile of explanation tenth embodiment of the invention manufacturing method for semiconductor device;
Figure 24 is the profile of explanation tenth embodiment of the invention manufacturing method for semiconductor device;
Figure 25 is the profile of explanation eleventh embodiment of the invention manufacturing method for semiconductor device;
Figure 26 is the profile of explanation eleventh embodiment of the invention manufacturing method for semiconductor device;
Figure 27 is the profile of explanation eleventh embodiment of the invention manufacturing method for semiconductor device;
Figure 28 is the profile of explanation eleventh embodiment of the invention manufacturing method for semiconductor device;
Figure 29 is the profile of the existing semiconductor device of explanation.
Symbol description
1,101 semiconductor integrated circuit
2,100 semiconductor substrates
The 2a semiconductor chip
3,103 dielectric films, 4,38,68,102 pad electrodes
5,104 passivating films
6,71,52,106 adhesive linkages
7,105 supporting masses
8,12,18,32,40,42,54,61 peristomes
9,107 dielectric films
10,108 wiring layers
11,53 grooves
13,13a, 21,31,41,55,109 protective layers, first protective layer
14,15,110 conducting terminals
20,30,35,37,43,45,56,60,67,70,75 semiconductor devices
The DL line of cut
35,65 first semiconductor devices
36,66 second semiconductor devices
46 conductions are stuck with paste
16,47 resist layers
50 bands
72,51 cavitys
17 guard blocks
The first embodiment of the present invention is described with reference to the accompanying drawings.Fig. 1 to Fig. 8 is profile or the plane graph of representing with manufacturing process's order respectively.Below the manufacturing process of explanation is to use the wafer-like semiconductor substrate to carry out, with the line of cut DL of regulation as the border with a plurality of semiconductor devices of rectangular formation, for ease and explanation forms the operation of one of them semiconductor device.
Embodiment
At first as shown in Figure 1, prepare to be formed with on its surface semiconductor integrated circuit 1 (for example photo detector such as ccd sensor, cmos sensor, illuminance transducer or light-emitting component, close drive circuit that semiconductor element such as transistor constitutes or logical circuit by layer, the distribution that is connected with them etc.), by the wafer-like semiconductor substrate 2 of formations such as silicon (Si).Semiconductor substrate 2 for example has the thickness about 300 μ m～700 μ m.For example form the film thickness of 2 μ m at the surperficial upper nonconductive Film 3 of semiconductor substrate 2 silicon oxide film of formation such as thermal oxidation method or CVD method (for example through).
Then through splash method or galvanoplastic and the formation of other film build method aluminium (Al), aluminium alloy or copper metal levels such as (Cu); Then not shown resist layer is come this metal level of etching as mask, on dielectric film 3, form the for example pad electrode 4 of 1 μ m film thickness.Pad electrode 4 is the external connection electrode that semiconductor integrated circuit 1 are electrically connected with its peripheral element via not shown distribution.From after the conducting terminal 14 stated via pad electrode 4 with supply voltage, earthed voltage or various signal to supplies such as semiconductor integrated circuit 1 or semiconductor substrates 2.The allocation position of pad electrode 4 is unqualified, also can be configured on the semiconductor integrated circuit 1.
Form on the part that covers pad electrode 4 on the surface of semiconductor substrate 2 then or whole passivating film 5 (silicon nitride film that for example forms) through the CVD method.Among Fig. 1, passivating film 5 forms on the part that covers pad electrode 4.
Then, on the surface of the semiconductor substrate that comprises pad electrode 42, come the supporting mass 7 of bonded wafer shape via adhesive linkage 6 by formations such as epoxy resin, polyimides (for example photosensitive polyimide), resist, propylene.Present embodiment with the face of semiconductor substrate 2 sides of supporting mass 7 as the surface, with other face as the back side.Comprise at semiconductor integrated circuit 1 under the situation of photo detector and light-emitting component; Because adhesive linkage 6 becomes the passage of the light of injecting from the light of semiconductor integrated circuit 1 radiation or to semiconductor integrated circuit 1, so preferably transparent, constitute by the well behaved material of transmissive light.
Supporting mass 7 for example can be membranaceous boundary belt, can be the substrate of rigidity such as glass, quartz, pottery, metal also, also can be made up of resin.Supporting mass 7 also has the function of its element surface of protection in supporting semiconductor substrate 2, its film thickness for example is about about 400 μ m.Comprise at semiconductor integrated circuit 1 under the situation of photo detector and light-emitting component, supporting mass 7 is made up of transparent or semitransparent material, has the performance of transmitted light.
Use back side grinding attachment (grinding machine) to carry on the back grinding to the back side of semiconductor substrate 2 then, with the thickness (for example about 100 μ ms) of semiconductor substrate 2 attenuates up to regulation.This grinding process also can be etch processes, also can and use grinding and etch processes.According to the initial thickness of the semiconductor substrate 2 of the purposes of end article and specification and preparation, need not carry out this grinding process sometimes yet.
As shown in Figure 2 then, selectively only to carrying out etching with pad electrode 4 corresponding regulation zones the semiconductor substrate 2, make dielectric film 3 expose a part from the rear side of semiconductor substrate 2.Below with this part of exposing as peristome 8.Peristome 8 forms clathrate in the rear side of semiconductor substrate 2, and shown in Fig. 3 A, Fig. 3 B, the semiconductor substrate 2 of wafer-like is divided into island like this.
With reference to Fig. 3 A, Fig. 3 B the selectable etching to this semiconductor substrate 2 is described.Fig. 3 A, Fig. 3 B are the general views of looking sideways from semiconductor substrate 2, and Fig. 2 is corresponding with profile along the X-X of Fig. 3 A, Fig. 3 B.
Shown in Fig. 3 A, also can semiconductor substrate 2 be etched into the roughly rectangular shape than supporting mass 7 narrow width.Shown in Fig. 3 B, be formed with the zone of pad electrode 4 through etching only, can also make the periphery of semiconductor substrate 2 become concavo-convex.The latter makes the overlapping area of semiconductor substrate 2 and supporting mass 7 big, and semiconductor substrate 2 is residual near the periphery of supporting mass 7.Therefore, see that the latter's structure is for well from the viewpoint of the bearing strength that improves 7 pairs of semiconductor substrates 2 of supporting mass.According to the latter's structure, the warpage of the supporting mass 7 that causes owing to the coefficient of thermal expansion difference that can prevent by semiconductor substrate 2 and supporting mass 7, so the crackle that can prevent semiconductor device with peel off.Also can semiconductor substrate 2 be designed to and the different shape of flat shape shown in Fig. 3 A, Fig. 3 B.Manufacturing process when explanation is carried out etching with semiconductor substrate 2 shown in Fig. 3 A later on.
In the present embodiment, make the sidewall of the transverse width of semiconductor substrate 2, but also can make the fixed width of semiconductor substrate 2 and make the interarea of its sidewall and supporting mass 7 vertically carry out etching the closer to the wide more crustal inclination etching semiconductor of face side substrate 2.
To utilize the dielectric films 9 such as silicon oxide film or silicon nitride film of formation such as plasma CVD method to be formed on then to comprise on the side and the back side of the inner semiconductor substrate 2 of peristome 8.Then as shown in Figure 4, not shown resist layer is come etching dielectric film 3 and dielectric film 9 selectively as mask.To remove selectively with dielectric film 9 to the regional formed dielectric film 3 of line of cut DL from the part of pad electrode 4 through this etching, at least a portion of pad electrode 4 is exposed in the bottom of peristome 8.
The aluminium (Al) and the copper metal levels such as (Cu) that then, will become wiring layer 10 through splash method or galvanoplastic and other film build method form the for example film thickness of 1 μ m.Then not shown resist layer is come this metal level of etching selectively as mask.As shown in Figure 5, through this etching this metal level and pad electrode 4 are formed by connecting and are side and the wiring layer on the back side 10 that is formed on semiconductor substrate 2.
Form the not shown connection electrode layer (for example layer closes nickel dam and gold layer) that covers wiring layer 10 then.Why form connection electrode layer and be because the wiring layer 10 that is made up of aluminium etc. is difficult to engage with the conducting terminal 14 that is made up of scolding tin etc., also for the material that prevents conducting terminal 14 to wiring layer 10 inflows.Also protective layer 13 these connection electrode layers of back formation can formed.
As shown in Figure 6 then, utilize cutter or dry ecthing a part to be removed on the surface of passivating film 5, adhesive linkage 6 and supporting mass 7 from semiconductor substrate 2 sides, be formed into supporting mass 7 thickness directions groove 11 midway.Groove 11 along the border (line of cut DL) of each semiconductor device and the relatively surface of supporting mass 7 is formed a plurality of on direction in length and breadth.Like this, semiconductor substrate 2 is broken into semiconductor chip by branch.Followingly continue explanation as semiconductor chip 2a.
As long as making the side of adhesive linkage 6 exposes; The cross sectional shape that does not limit groove 11 is a V word shape shown in Figure 6; Also can be ellipticity or rectangle etc. roughly; But the good viewpoints of spreadability are seen in the groove 11 of the protective layer of stating after make 21, preferably set V word shape for or make the crooked laterally shape in top (near the part on semiconductor chip 2a surface).
Then as shown in Figure 7, will with after state conducting terminal 14 the protective layer 13 of corresponding position, formation zone with peristome 12 form thick to: from the side of the semiconductor chip 2a that comprises said groove 11 to the back side with whole semiconductor chip 2a landfill.
At this, the formation of said protective layer 13 is for example carried out as follows.At first for example use stencil printing to form casting resin, up to than said semiconductor chip 2a about high 30 μ m with peristome 12 with mode with said semiconductor chip 2a landfill.
Material as said protective layer 13 can use organic type of materials such as polyimide based resin, anti-flux film.Also can use the absorbing material that absorbs visible light or infrared ray etc.
Can utilize distribution method (rubbing method) to be coated with as the formation method of said protective layer 13.
As above, the protective layer 13 of present embodiment covers the side of said adhesive linkage 6 fully, and forms thick arriving whole semiconductor chip 2a landfill.Therefore semiconductor device 20 of the present invention is compared with existing semiconductor devices and has been improved moisture-proof.Even therefore likewise use the bad anti-flux film of moisture-proof as protective layer 13 with existing, moisture-proof can not reduce than existing structure is enough thick because this anti-flux film forms.
Web plate printing conductive material (for example scolding tin) on the connection electrode layer that the peristome 12 from protective layer 13 exposes forms spherical conducting terminal 14 shown in Figure 8 through this electric conducting material is carried out Reflow Soldering with heat treatment then.The formation method of conducting terminal 14 is not limited to above-mentioned, also can be formed by electrolytic plating method and the so-called apportion design etc. of using distributor scolding tin etc. to be applied to the regulation zone.Like this, pad electrode 4 just is electrically connected with conducting terminal 14 via wiring layer 10.
Though omitted illustrated explanation, through being carried out etching equably, the whole back side of said supporting mass 7 can make supporting mass 7 be thinned to the thickness (for example about 50 μ m) of regulation, and can also be with semiconductor device 20 slimmings.
As engraving method, preferably use back side grinding attachment (grinding machine) to carry out mechanical etching, while or substrate rotation is used comprise the soup of fluoric acid etc. to carry out etched rotation wet etching.But so long as the method at the etching supporting mass 7 whole back sides then also can be other engraving methods such as immersion etching.
As shown in Figure 8, through using cutter said protective layer 13 is carried out the semiconductor device 20 that the chip size packages type has just been accomplished in disjunction with supporting mass 7.Via conducting terminal 14 with semiconductor device 20 to installations such as printed base plates.
First embodiment utilizes said protective layer 13 to comprise said adhesive linkage 6 and laterally whole semiconductor chip 2a is covered fully.Therefore, suppressed adhesive linkage 6 and contacted, can prevent that corrosive deposit (for example moisture) is to semiconductor integrated circuit 1 or adhesive linkage 6 intrusions with outside atmosphere.
The second embodiment of the present invention is described with reference to the accompanying drawings.Omit its explanation with identical symbolic representation for structure identical and manufacturing process with first embodiment.
As shown in Figure 8, first embodiment covers through the whole back side of protective layer 13 with semiconductor substrate 2.Relative therewith, as shown in Figure 9, in the semiconductor device 30 of second embodiment; Be characterized in adopting following operation; Be about to the first protective layer 13a and be formed into the back side of closing on semiconductor substrate 2, shown in figure 10, on this first protective layer 13a, form second protective layer 31 with peristome.On said connection electrode layer, form conducting terminal 14 via formed peristome in said second protective layer 31.
At this, be to use the apportion design coating for example to add the end inserts of filler as the first protective layer 13a in the present embodiment.Material as the said first protective layer 13a can use organic type of materials such as casting resin, polyimide resin, anti-flux film.Also can use the absorbing material that absorbs visible light or infrared ray etc., also can use the reflecting material of reflect visible light or infrared ray etc.Use anti-flux material as 31 of said second protective layers.
With reference to Figure 11 the third embodiment of the present invention is described below.Then omit its explanation for structure identical and manufacturing process with identical symbolic representation with first and second embodiment.
Among first and second embodiment, form the protective layer 13 and the first protective layer 13a with the mode of the said groove 11 of landfill.Relative therewith; Shown in figure 11; The characteristics of the semiconductor device 35 of the 3rd embodiment are for adopting following operation; Promptly with roughly uniformly thickness form protective layer 41 at the back side of semiconductor substrate 2 with peristome, on said connection electrode layer, form conducting terminal 14 via the peristome of said protective layer 41.Use apportion design to form conduction and stick with paste 46 (for example silver is stuck with paste) with the mode that covers said groove 11.Also can use screen printing to form conduction and stick with paste 46.
More than the said semiconductor device 35 of explanation is because after the protective layer 109 that forms with existing semiconductor device 100 likewise forms protective layer 41; Use conduction to stick with paste 46 the side of groove 11 and semiconductor chip 2a carried out landfill, improved moisture-proof so compare with existing structure.Stick with paste 46 owing to be formed with conduction, so ability reflect visible light or infrared ray etc.
If on semiconductor integrated circuit 1, form adhesive linkage, the quality of this semiconductor device is reduced.For example comprise under the situation of photo detector and light-emitting component at semiconductor integrated circuit 1, adhesive linkage hinders light incident to the semiconductor integrated circuit 1 light outgoing of semiconductor integrated circuit 1 (or from) and the quality that can not get sometimes hoping.In addition, also have the light of the such specific wavelength of blue streak (Blu-Ray) to make the adhesive linkage deterioration, because the problem that the quality of movement of the adhesive linkage semiconductor device of this deterioration reduces.
So shown in figure 12, the semiconductor device 45 of the 4th embodiment does not accompany adhesive linkage 52 through forming cavity 51 between semiconductor integrated circuit 1 and supporting mass 7.Therefore, the semiconductor device (for example blue streak light-receiving semiconductor device) that for the existence owing to adhesive linkage 52 quality of movement is reduced just becomes effective structure.As the 4th embodiment the structure with said cavity 51 is described, but the present invention also can adopt the structure with said cavity 51 for above-mentioned first, second with the 3rd embodiment.
Under state during with the whole etching of said supporting mass 7 with said cavity 51, such the 5th embodiment semiconductor device 60 that possesses the adhesive linkage 52 that on semiconductor integrated circuit 1, has peristome 61 that forms then shown in figure 13.The present invention also can adopt the structure of the said supporting mass of whole etchings for above-mentioned first, second with the 3rd embodiment.
Then, explain with reference to Figure 14 that as the 6th embodiment the semiconductor device that will possess the adhesive linkage 52 with said peristome 61 closes a plurality of laminate-type semiconductor devices 67 on vertical (up and down) direction upper strata.Figure 14 representes first and second semiconductor devices 65,66 profile of the laminate-type semiconductor device 67 that closes of layer in order.Said semiconductor device 65,66 possesses the pad electrode 68 that exposes to the outside from peristome 61.Except pad electrode 68 exposes this point to the outside from peristome 61, with the pad electrode of having explained 4 are same structures.
Said laminate-type semiconductor device 67 is at each semiconductor device 65 of completion, after 66; The conducting terminal 14 of second semiconductor device 66 is alignd with the pad electrode 68 of first semiconductor device 65 and overlapping, for example conducting terminal 14 is connected with pad electrode 68 then and accomplishes through the thermo-compressed method.Explained that in above-mentioned explanation carrying out layer between the semiconductor device with same kind (same size) closes; But so long as the semiconductor device of pad electrode 68 and conducting terminal 14 alignment, just being not limited to is to carry out layer between the semiconductor device with same kind (same size) to close.Certainly also maybe be on said semiconductor device 66 further layer close other semiconductor device.
Because this laminate-type semiconductor device 67 does not have supporting mass 7, so can the height setting of laminate structures be become minimum.Owing to pass through protective layer 13 with semiconductor substrate 2 landfills; Promptly the side from semiconductor chip 2a forms protective layer 13 to the back side with whole mulched ground; So can also so that up and down the state that is adjacent to of semiconductor device 65,66 carry out layer and close, so become strong structures such as resistance to impact.Said protective layer 13 also can be made up of the first protective layer 13a and second protective layer 31.
Then to Figure 18 the 7th embodiment is described referring to figs. 1 through Fig. 6 and Figure 15.Owing to explained that Fig. 1 is to Fig. 6 among first embodiment; So omit detailed explanation; But the thickness of supporting mass 7 is set the degree of depth of groove 11 among Fig. 6 after the consideration singualtion; For example become about 50 μ m, then form groove 11, its bottom is configured in apart from the about 70 μ m left and right sides depth locations in supporting mass 7 surfaces as if thickness setting with final supporting mass 7.Even utilizing cutter to form under the situation of groove 11, using the operation of cutter also only is this operation, as after obtain stating not using cutter in the operation of each semiconductor device.Therefore, and use the manufacturing approach of cutter to compare in the operation that forms groove 11 with these two operations of operation that are used for obtaining each semiconductor device, the operation of present embodiment use cutter is few, so can shorten the needed time as whole manufacturing process.
Shown in figure 15 then, with after state conducting terminal 15 the corresponding position of formation zone and groove 11, for example have the protective layer 21 of peristome 12,18 with the thickness formation of 10 μ m.The formation of protective layer 21 is for example carried out as follows.At first utilize coating-cladding process with organic type of materials such as polyimide resin, anti-solder flux to whole coating, and enforcement heat treatment (preliminary drying).Make organic type of material exposure-development of coating then and form the opening that exposes the regulation zone, afterwards it is implemented heat treatment (back baking).Like this, just obtain having the protective layer 21 of peristome 12,18 in and groove 11 corresponding positions regional with the formation of conducting terminal 15.Though the protective layer 21 of present embodiment has covered the side of adhesive linkage 6 fully, the side of supporting mass 7 only is that the part near semiconductor substrate 2 is capped, and does not form protective layer 21 on the line of cut DL at least.
In other words, the end of protective layer 21 is configured in from the surface of supporting mass 7 to groove 11 bottoms midway, does not form protective layer 21 in the bottom of groove 11.Through forming peristome 18 with the groove of protective layer 21 11 corresponding positions like this, and can prevent after after the supporting mass 7 back etched operations stated the semiconductor device of adjacency be connected through protective layer 21, can rightly each semiconductor device be separated.
Web plate printing conductive material (for example scolding tin) on the connection electrode layer that the peristome 12 from protective layer 21 exposes forms spherical conducting terminal 15 shown in Figure 16 through this electric conducting material is refluxed with heat treatment then.The formation method of conducting terminal 15 is not limited to above-mentioned, also can be formed by electrolytic plating method and the so-called apportion design (rubbing method) etc. of using distributor scolding tin etc. to be applied to the regulation zone.Like this, pad electrode 4 just is electrically connected with conducting terminal 15 via wiring layer 10.
From the liquid anticorrosive additive material of the rear side rotary coating of semiconductor substrate 2, comprise that groove 11 inwalls are covered conducting terminal 15 and protective layer 21 integral body such as grade by resist layer 16 then.The thickness that resist layer 16 has is the degree with semiconductor chip 2a landfill.Make this resist layer 16 sclerosis through implementing heat treatment then.Owing in groove 11, be filled with resist layer 16 via peristome 18, so resist layer 16 contacts with supporting mass 7 in the bottom of groove 11.
Then, guard blocks 17 such as for example membranaceous UV band or glass substrate are fitted on the back side of semiconductor chip 2a.When the supporting mass 7 back etched operations of following narration and transporting afterwards, guard block 17 keeps semiconductor chip 2a, and has the function of protection conducting terminal 15 etc.
Then shown in figure 17, from the back side of supporting mass 7 etching is carried out equably up to groove 11 and resist layer 16 are exposed in the whole back side of supporting mass 7, make supporting mass 7 be thinned to the thickness (for example about 50 μ m) of regulation.As engraving method, preferably use back side grinding attachment (grinding machine) to carry out mechanical etching, while or substrate rotation is used comprise the soup of fluoric acid etc. to carry out etched rotation wet etching.But so long as the method at the etching supporting mass 7 whole back sides then also can be to soak etching (デ イ Star プ エ Star チ Application グ) to wait other engraving method.
According to of the etching of precalculated etching ratio, or utilize Optical devices to detect exposing of resist layer 16 etc., stop through such method with this supporting mass 7 of time management.Make the supporting mass 7 island ground singualtion of wafer-like like this, can form the semiconductor device 70 of shaped like chips singualtion in the lump.
Even groove 11 is exposed from the back side of supporting mass 7, in groove 11, also be formed with resist layer 16, the guard block 17 of on the back side of semiconductor chip 2a, also fitting.Therefore, each semiconductor device 70 can not disperse.Because resist layer 16 becomes obstacle with guard block 17, so corrosive deposits such as soup can not invaded to semiconductor chip 2a side, the operating characteristics of semiconductor device 70 can not worsen.
Behind the back etched with supporting mass 7, each semiconductor device 70 is transported under the state that is fitted with guard block 17, but is seamlessly filled by resist layer 16 between the adjacent semiconductor device 70.Therefore, when transporting, be difficult to produce that mutual wiping is bumped and mechanical damage such as damaged between the adjacent semiconductor device 70.
Supply with the lytic agent of stipulating from the rear side of supporting mass 7 then and dissolve the resist layer 16 that exposes, pick up the semiconductor device 70 of singualtion then from guard block 17.When guard block 17 is the UV band,, just can easily pick up semiconductor device 70 through reducing its cementability to guard block 17 irradiation ultraviolet radiations.
Other the new bands of also can on the back side of supporting mass 7, fitting are peeled off guard block 17 then, and the lytic agent of supplying with regulation from the rear side of semiconductor chip 2a then dissolves resist layer 16.
Shown in figure 18, through the semiconductor device 70 of above operation completion chip size packages type.Semiconductor device 70 is installed on printed base plate etc. via conducting terminal 15.
More than the 7th embodiment of explanation be not as prior art with line of cut DL singly cutting obtain each semiconductor device, but obtain each semiconductor device through the whole back side of etching supporting mass 7.Therefore, owing to be to make all semiconductor devices in the lump by singualtion, so can shorten the needed time of cutting action significantly, can tremendous raising productivity.
The 7th embodiment is owing to seeking the slimming of supporting mass 7 and the singualtion of semiconductor device, so compared with prior art can make slim semiconductor device expeditiously simultaneously.Because the slimming of supporting mass 7 is after the structure important document of semiconductor devices such as wiring layer 10, conducting terminal 15 and protective layer 21 all forms, to carry out,, the rigidity of the supporting mass 7 that is caused by slimming can not impact in the stage that forms of each structure important document so reducing.
Even the back etched through supporting mass 7 makes groove 11 expose from the back side of supporting mass 7, in groove 11, be formed with resist layer 16, the guard block 17 of on the back side of semiconductor chip 2a, fitting.Therefore, etch material (soup that the particulate that is for example produced during the back etched of supporting mass 7 and this etching work procedure use etc.) can not invaded to semiconductor chip 2a side, can not suppress the deterioration of quality.
Among the 7th embodiment, the side protected seam 21 of adhesive linkage 6 covers fully, and the side near semiconductor substrate 2 in the side of supporting mass 7 is capped.Therefore, suppressed adhesive linkage 6 and contacted, can prevent that etch material (for example moisture) is to semiconductor integrated circuit 1 and adhesive linkage 6 intrusions with outside atmosphere.
The eighth embodiment of the present invention is described with reference to the accompanying drawings.Then omit its explanation for structure identical and manufacturing process with identical symbolic representation with the 7th embodiment.
Shown in figure 17, among the 7th embodiment with the back etched of supporting mass 7 midway to supporting mass 7 thickness directions.Relative therewith, the characteristics of the 8th embodiment are to adopt supporting mass 7 whole etched operations.The etching of this supporting mass 7 for example stops in supporting mass 7 whole etched moment point through management etching ratio.Shown in figure 19, can obtain topmost through this operation is the semiconductor device 75 of adhesive linkage 6.At this moment, adhesive linkage 6 has the effect of the surface of protection semiconductor chip 2a.
Because the 8th embodiment likewise is to make each semiconductor device fully in the lump by singualtion with the 7th embodiment also, so can shorten the needed time of cutting action significantly, can improve productivity.And do not had the thickness of supporting mass 7, so can obtain the semiconductor device more slim than the 7th embodiment.
The nineth embodiment of the present invention is described with reference to the accompanying drawings.Then omit its explanation for structure identical and manufacturing process with identical symbolic representation with the 7th and the 8th embodiment.
Among the 7th and the 8th embodiment, adhesive linkage 6 is formed uniformly between semiconductor substrate 2 and supporting mass 7.Relative therewith, shown in figure 20, the characteristics of the 9th embodiment are to form adhesive linkage 71 partly, between semiconductor chip 2a and supporting mass 7, form the same cavity 72 of cavity 51 among the Figure 12 with the 4th embodiment.
The inner space that cavity 72 is surrounded by semiconductor chip 2a, adhesive linkage 71 and supporting mass 7, for example through on the surface of semiconductor substrate 2, being coated with the material of adhesive linkage 71 annularly, the supporting mass 7 of fitting then forms.
Under the state that has cavity 72 like this, likewise the back side of etching supporting mass 7 is up to exposing groove 11 with the operation of using Figure 16 and Figure 17 to explain, and formation possesses the semiconductor device of cavity 72.
Though,, the quality of this semiconductor device is reduced if on semiconductor integrated circuit 1, form adhesive linkage with the narration repetition of the 4th embodiment.For example comprise under the situation of photo detector and light-emitting component at semiconductor integrated circuit 1, adhesive linkage hinders light incident to the semiconductor integrated circuit 1 light outgoing of semiconductor integrated circuit 1 (or from) and the quality that can not get sometimes hoping.
In addition, also have, because the problem that the adhesive linkage of this deterioration reduces the quality of movement of semiconductor device because the light of the such specific wavelength of blue streak (Blu-Ray) makes the adhesive linkage deterioration.
Because the 9th embodiment and the 4th embodiment likewise do not accompany adhesive linkage 52 through forming cavity 72 between semiconductor integrated circuit 1 and supporting mass 7.Therefore, the semiconductor device (for example blue streak light-receiving semiconductor device) that for the existence owing to adhesive linkage quality of movement is reduced just becomes effective structure.
Have in that kind shown in figure 20 under the state of cavity 72, during with the whole etching of supporting mass 7, formation then shown in figure 21 possesses the semiconductor device of the adhesive linkage 71 that on semiconductor integrated circuit 1, has peristome 32 as the 8th embodiment explanation.This becomes the same structure of structure with the adhesive linkage with peristome 61 52 of the 5th embodiment shown in Figure 13.
Therefore with the narration of the 6th embodiment likewise, the semiconductor device that can that kind shown in figure 22 be possessed the adhesive linkage 71 with peristome 32 layer in vertical direction closes a plurality of and cambium layer mould assembly semiconductor device.Though repeat, its summary situation be described with reference to Figure 22.Figure 22 representes semiconductor device 35,36 profile of the laminate-type semiconductor device 37 that closes of layer in order.Semiconductor device 35,36 possesses the pad electrode 38 that exposes to the outside from peristome 32.Except pad electrode 38 exposes this point to the outside from peristome 32, with the pad electrode of having explained 4 are same structures.
Laminate-type semiconductor device 37 is at each semiconductor device 65 of completion, after 66; The conducting terminal 15 of semiconductor device 36 is alignd with the pad electrode 38 of semiconductor device 35 and overlapping, for example conducting terminal 15 is connected with pad electrode 38 then and accomplishes through the thermo-compressed method.Certainly also possibly close other semiconductor device on semiconductor device 36 upper stratas.Because this laminate-type semiconductor device 37 does not have supporting mass 7, so can the height setting of laminate structures be become minimum.
The tenth embodiment of the present invention is described with reference to the accompanying drawings.Then omit its explanation for structure identical and identical manufacturing process with identical symbolic representation with the 7th to the 9th embodiment.
Among the 7th to the 9th embodiment etching is carried out at the whole back side of supporting mass 7 equably.Relative therewith, the tenth embodiment adopts the processing at local etching supporting mass 7 back sides.At first shown in figure 23, form groove 11 and resist layer 16, behind applying guard block 17 on the back side of semiconductor chip 2a, will be formed on selectively on the back side of supporting mass 7 having peristome 40 resist layers 47 with groove 11 corresponding positions.
Shown in figure 24 then, with resist layer 47 as mask partly etching supporting mass 7 the back side and form peristome 42.Peristome 42 is in the position relative with groove 11, promptly on direction in length and breadth, forms a plurality of along the borderline phase of each semiconductor device to the back side of supporting mass 7.This etching proceeds to and makes peristome 42 arrival slots 11 and groove 11 and resist layer 16 are exposed, and like this, the supporting mass 7 of wafer-like is formed the semiconductor device 43 that is turned to shaped like chips by monolithic in the lump by island ground singualtion.
As engraving method, seek to shorten the viewpoint of manufacturing process's time and see from the single treatment mass substrate, preferably wet etching.At this moment just can as long as be immersed in the container that is full of the regulation soup with the state that is formed with above-mentioned resist layer 47.The etching at supporting mass 7 back sides also can be carried out through dry ecthing and sandblast.
The sidewall of the supporting mass 7 of arrival slot 11 is tilted etching from the back side among Figure 24, but when anisotropic etchings such as utilizing dry ecthing and sandblast comes etching supporting mass 7, also can make the interarea approximate vertical of this sidewall and supporting mass 7.
The lytic agent of supplying with regulation from peristome 42 then dissolves resist layer 16, from guard block 17 each semiconductor device 43 peeled off afterwards,
More than the tenth embodiment of explanation be not as prior art with line of cut DL singly cutting obtain each semiconductor device, and be to use the resist layer 47 that has peristome 42 along the border of each semiconductor device that the back side local etching of supporting mass 7 is obtained each semiconductor device.Therefore, owing to be to make all semiconductor devices in the lump by singualtion, so can shorten the needed time of cutting action significantly, can tremendous raising productivity.
The 11st embodiment of the present invention is described with reference to the accompanying drawings.Then omit its explanation for structure identical and manufacturing process with identical symbolic representation with the 7th to the tenth embodiment.
Shown in figure 25, on the surface of semiconductor substrate 2, be with 50 via adhesive linkage 6 applyings, be with applying supporting mass 7 on 50.Be with 50 for example to constitute by polyimides, preferably by with adhesive linkage 6 with after protective layer 55 material different stated constitute.This is owing to make the solvent that with 50 viscosity reduce removing with supplying with sometimes at 50 o'clock, and at this moment can adhesive linkage 6 and protective layer 55 not removed simultaneously.Forming peristome 8, dielectric film 9 and wiring layer 10 etc. with the same operation of the 7th embodiment then.
Shown in figure 26 then, utilize cutter and dry ecthing from semiconductor chip 2a side sections remove passivating film 5, adhesive linkage 6 and be with 50, form to arrive thickness direction groove 53 midway like this with 50.Groove 53 along the border (line of cut DL) of each semiconductor device and relatively forms a plurality of on direction in length and breadth with 50 surface.
Then, in that 53 corresponding positions formation have the protective layer 55 that is made up of anti-solder flux etc. of peristome 12,54 with groove with the formation of conducting terminal 15 zone.Though the protective layer 55 of present embodiment has covered the side of adhesive linkage 6 fully, the side with 50 only is that the part near semiconductor chip 2a is capped, and does not form protective layer 55 on the line of cut DL at least.
In other words, the end of protective layer 55 is configured in from adhesive linkage 6 sides to groove 53 bottoms midway, does not form protective layer 55 in the bottom of groove 53., can prevent to be connected through protective layer 55 forming peristome 54 through like this, can rightly each semiconductor device be separated at the semiconductor device of removing with 50 o'clock adjacency with groove 53 corresponding positions.
Shown in figure 27 then, the connection electrode layer that exposes at the peristome 12 from protective layer 55 forms conducting terminal 15.Then, comprise groove 53 inwalls and conducting terminal 15 and protective layer 55 integral body such as grade are covered by resist layer 16 interior from the rear side painting erosion resistant agent material of semiconductor chip 2a.In the bottom of groove 53 resist layer 16 be with 50 to contact.Applying guard block 17 on the back side of semiconductor chip 2a then.
Then as use Figure 24 explanation, use resist layer 47 comes partly etching supporting mass 7 and makes and be with 50 to expose.Remove to the lytic agent that exposes then and be with 50, semiconductor chip 2a is separated with supporting mass 7 with 50 supply regulations.
Then remove resist layer 16, pick up the semiconductor device 56 of singualtion from guard block 17.Then accomplish chip size packages type semiconductor device 56 shown in Figure 28 through above operation.
Because the 11 embodiment likewise is to make each semiconductor device all in the lump by singualtion with the 7th to the tenth embodiment also, so can shorten the needed time of cutting action significantly, can improve productivity.And do not had the thickness of supporting mass 7, so can obtain slim semiconductor device.
The 12nd embodiment of the present invention is described below.For the structure identical with manufacturing process then omits or simply its explanation with first to the 5th embodiment.
Shown in figure 16, comprise groove 11 inwalls among the 7th embodiment and conducting terminal 15 and protective layer 21 integral body such as grade are covered by resist layer 16 interior.Relative therewith, do not form resist layer 16 among the 12 embodiment, applying guard block 17 on the back side of semiconductor chip 2a.Except not forming resist layer 16 this point, be the structure identical, so the diagram of the 12 embodiment is omitted with Figure 16.
Then, the back side of the whole supporting mass 7 of etching equably, or be formed on the resist layer (with reference to Figure 23) that has peristome with groove 11 corresponding positions selectively at the back side of supporting mass 7, come partly etching supporting mass 7 with this resist layer as mask.
At this, the 7th, the tenth embodiment carries out etching up to groove 11 is exposed, and like this, the supporting mass 7 of wafer-like is formed the semiconductor device that is turned to shaped like chips by monolithic in the lump by singualtion.Relative therewith, close at groove 11 among the 12 embodiment that the etching of supporting mass 7 is stopped.Promptly extremely thin at the thickness of the position supporting mass 7 corresponding with groove 11.The thickness of the supporting mass 7 of this position for example is 50～100 μ m.
Owing to before groove 11 is exposed, do not carry out etching; Even so do not form resist layer 16; Also corrosive deposit (soup that the particulate that is for example produced during the back etched of supporting mass 7 and this etching work procedure use etc.) can not invaded, can not suppress the deterioration of quality to semiconductor substrate 2 sides owing to supporting mass 7 becomes obstacle.
Then to the position of these supporting mass 7 attenuation in addition physics mechanical load and supporting mass 7 is cut off along groove 11.For example use the utensil of staff or regulation to push supporting mass 7 cut-outs along what groove 11 was stipulated to face side particularly from the rear side of supporting mass 7.
Like this, the supporting mass 7 of wafer-like is promptly formed the semiconductor device that is turned to shaped like chips by monolithic by island ground singualtion.
Like this, by the singualtion that also can seek semiconductor device through two-stage procedure (the back etched operation of supporting mass 7 and give the operation of physical load to the correspondence position of groove 11).According to this manufacturing approach, have not form resist layer 16 and can prevent the advantage that corrosive deposit is invaded to semiconductor chip 2a side.Owing to need not use cutter, so can shorten the needed time of cutting action.Through in the back side of supporting mass 7, applying physical load continuously or side by side and roughly obtain the semiconductor device of singualtion in the lump, can improve productivity with groove 11 all corresponding positions.
The present invention is not limited to the foregoing description, can change in the scope that does not break away from its main idea certainly.For example the foregoing description has been explained the semiconductor device of BGA (the Ball Grid Array) type with spherical conducting terminal, but the present invention also goes for LGA (Land Grid Array: land grid array) type and other CSP (Chip Size Package) type semiconductor device.
In the foregoing description conducting terminal is formed on the back side of semiconductor substrate, but also can disposes conducting terminal in abutting connection with ground with the side of semiconductor substrate.
The the 7th to the 12 embodiment is formed with protective layer 21,55, but also can be applicable to the semiconductor device that does not form protective layer, effectively obtains extensive being suitable for of manufacturing approach ability quilt that monolithic turns to the semiconductor device of shaped like chips as being used for.At this moment, preferably use the metal material (for example copper) high as wiring layer 10 to corrosive deposit (moisture etc.) patience.
Claims (14)
1. a semiconductor device is characterized in that, comprising: be connected with circuit element in the semiconductor chip and be formed near the side surface part on this semiconductor chip metal pad,
Be formed on side surface part and the back side portion of said semiconductor chip dielectric film,
Connect with the back side of said metal pad and with said dielectric film mutually ground connection from the side surface part of said semiconductor chip support or oppose the facial metal wiring that extends,
To comprise said semiconductor chip end interior integral body with the protective layer of uniform face landfill,
The conducting terminal that is electrically connected with said metal wiring via the peristome that is formed at said protective layer,
The end portion thickness of said protective layer is thicker than the aggregate thickness of said semiconductor chip, said dielectric film, said metal wiring.
2. semiconductor device as claimed in claim 1 is characterized in that, said protective layer comprises first protective layer and second protective layer.
3. according to claim 1 or claim 2 semiconductor device is characterized in that, has to comprise said metal pad with covering and carry out bonding supporting mass in the mode of interior said semiconductor chip surface portion.
4. a semiconductor device is characterized in that, closes other semiconductor device on the described semiconductor device of claim 1 upper strata, and said protective layer and the semiconductor device of downside of the described semiconductor device of claim 1 of upside are joined.
5. a semiconductor device is characterized in that, comprising: be connected with circuit element in the semiconductor chip and be formed near the side surface part on this semiconductor chip metal pad,
Be formed on side surface part and the back side portion of said semiconductor chip dielectric film,
Connect with the back side of said metal pad and with said dielectric film mutually ground connection from the side surface part of said semiconductor chip support or oppose the facial metal wiring that extends,
Be formed on side surface part and the back side portion of said semiconductor chip protective layer,
The conducting terminal that is connected with said metal wiring via the peristome that is formed at said protective layer,
Be formed on the said protective layer and carry out with uniform face to the end conductive film of landfill from the side surface part of said semiconductor chip.
6. semiconductor device as claimed in claim 5 is characterized in that, has to comprise said metal pad with covering and carry out bonding supporting mass in the mode of interior said semiconductor chip surface portion.
7. the manufacturing approach of a semiconductor device is characterized in that, comprising:
Preparation is formed with the semiconductor substrate of metal pad via first dielectric film, and will comprise operation that said metal pad fits on the surface of the face side of interior said semiconductor substrate and supporting mass,
From the rear side of said semiconductor substrate its part is removed and make operation that said first dielectric film exposes,
Form at the whole back side of said semiconductor substrate second dielectric film operation,
Remove the part of said first and second dielectric films and make operation that said metal pad exposes,
Form be connected with the back side of said metal pad and the operation of the metal wiring of the back side of said semiconductor substrate extension,
Remove the part of said semiconductor substrate and form on the surface of said supporting mass the operation that arrives said supporting mass thickness direction groove midway,
With landfill comprise operation that the mode of said groove at the whole back side of interior said semiconductor substrate form protective layer,
The operation of the conducting terminal that formation is electrically connected with said metal wiring via the peristome that is formed at said protective layer.
8. the manufacturing approach of semiconductor device as claimed in claim 7 is characterized in that, the operation that forms said protective layer has: the operation that after forming first protective layer, on this first protective layer, forms second protective layer.
9. the manufacturing approach of a semiconductor device is characterized in that, comprising:
Preparation is formed with the semiconductor substrate of metal pad via first dielectric film, and will comprise operation that said metal pad fits on the surface of the face side of interior said semiconductor substrate and supporting mass,
From the rear side of said semiconductor substrate its part is removed and make operation that said first dielectric film exposes,
Form at the whole back side of said semiconductor substrate second dielectric film operation,
Remove the part of said first and second dielectric films and make operation that said metal pad exposes,
Form be connected with the back side of said metal pad and the operation of the metal wiring of the back side of said semiconductor substrate extension,
Remove the part of said semiconductor substrate and form on the surface of said supporting mass the operation that arrives said supporting mass thickness direction groove midway,
Comprise operation that the rear side of said groove at interior said semiconductor substrate form first protective layer,
The operation of the conducting terminal that formation is electrically connected with said metal wiring via the peristome that is formed at said first protective layer,
On said first protective layer, form the operation of second protective layer.
10. the manufacturing approach of semiconductor device as claimed in claim 7 is characterized in that, forms in the operation of said protective layer and is coated with casting resin.
11. the manufacturing approach like claim 8 or 9 described semiconductor devices is characterized in that, forms in the operation of said first protective layer and is coated with casting resin.
12. the manufacturing approach of semiconductor device as claimed in claim 9 is characterized in that, forms in the operation of said second protective layer and is coated with conductive material.
13. the manufacturing approach like each described semiconductor device in the claim 7 to 9 is characterized in that, has the operation of said supporting mass being carried out slimming.
14. the manufacturing approach like each described semiconductor device in the claim 7 to 9 is characterized in that, has the operation of removing said supporting mass.
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| Application Number | Priority Date | Filing Date | Title |
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| JP122753/07 | 2007-05-07 | ||
| JP2007122753A JP5101157B2 (en) | 2007-05-07 | 2007-05-07 | Manufacturing method of semiconductor device |
| JP2007143965A JP5122184B2 (en) | 2007-05-30 | 2007-05-30 | Semiconductor device and manufacturing method thereof |
| JP143965/07 | 2007-05-30 |
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| CN102496622B (en) * | 2011-11-25 | 2016-03-30 | 格科微电子（上海）有限公司 | The method for packing of image sensor chip and camera module |
| US9117715B2 (en) * | 2012-07-18 | 2015-08-25 | Hong Kong Applied Science and Technology Research Institute Company Limited | Wafer-level device packaging |
| CN105261627A (en) * | 2015-10-19 | 2016-01-20 | 格科微电子（上海）有限公司 | CSP method and part of image sensor chip |
| US20170186712A1 (en) * | 2015-12-29 | 2017-06-29 | Xintec Inc. | Chip package and method for forming the same |
| JP6604476B2 (en) * | 2016-03-11 | 2019-11-13 | パナソニックＩｐマネジメント株式会社 | Device chip manufacturing method |
| TWI717846B (en) | 2018-09-25 | 2021-02-01 | 精材科技股份有限公司 | Chip package and method for forming the same |
| CN109830890B (en) * | 2019-01-15 | 2021-10-22 | 华天慧创科技（西安）有限公司 | Chip module, wafer-level chip packaging structure and packaging method |
| CN114497962A (en) * | 2021-12-22 | 2022-05-13 | 中国电子科技集团公司第二十九研究所 | Design method of broadband impedance matching directional coupler |
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| US7102238B2 (en) * | 2003-04-24 | 2006-09-05 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
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| JP2001085363A (en) * | 1999-09-13 | 2001-03-30 | Mitsui High Tec Inc | Method for manufacturing semiconductor device |
| US6818532B2 (en) * | 2002-04-09 | 2004-11-16 | Oriol, Inc. | Method of etching substrates |
| TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
| JP4562371B2 (en) * | 2002-10-30 | 2010-10-13 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP4334397B2 (en) * | 2003-04-24 | 2009-09-30 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP4248355B2 (en) * | 2003-09-24 | 2009-04-02 | 三洋電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2006093367A (en) * | 2004-09-24 | 2006-04-06 | Sanyo Electric Co Ltd | Manufacturing method of semiconductor device |
| JP4522213B2 (en) * | 2004-09-29 | 2010-08-11 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP4728033B2 (en) * | 2005-04-19 | 2011-07-20 | 株式会社ディスコ | Processing method of semiconductor wafer |
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| US7102238B2 (en) * | 2003-04-24 | 2006-09-05 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
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| CN101304015A (en) | 2008-11-12 |
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