CN105261627A - CSP method and part of image sensor chip - Google Patents
CSP method and part of image sensor chip Download PDFInfo
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- CN105261627A CN105261627A CN201510674986.5A CN201510674986A CN105261627A CN 105261627 A CN105261627 A CN 105261627A CN 201510674986 A CN201510674986 A CN 201510674986A CN 105261627 A CN105261627 A CN 105261627A
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- semiconductor substrate
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- sensor chip
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- line layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The invention provides a CSP (chip scale packaging) method and part of an image sensor chip. The CSP method comprises: providing an image sensor chip which comprises a pixel array formed on the functional surface of a semiconductor substrate; and connecting the back side of the semiconductor substrate with a metal line layer, wherein the metal line layer is in connection with electric signals through solder bumps. The CSP part shortens a current path, cuts substrate resistance and circuit loss, reduces the substrate resistance difference among pixel units, enhances the signal uniformity between a pixel array center and an edge, and improves the imaging performance of an image sensor. For an image sensor with an N-shaped substrate, the N-shaped substrate can be in connection with a power supply from the back side of a semiconductor substrate, avoiding forming deeper ion implantation on the functional surface of the semiconductor substrate, reducing process difficulty, and allowing a thicker EPI layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of CSP method for packing and packaging part of image sensor chip.
Background technology
At present, imageing sensor (ImageSensor) chip encapsulation technology of main flow comprises: COB(ChipsOnBoard) and CSP(ChipScalePackaging).Wherein CSP refers to the chip encapsulation technology that chip size packages is substantially identical with chip core size, and in CSP, the ratio of long term voyage and package area is about 1:1.1, and every encapsulation meeting this standard can be referred to as CSP.Such packing forms substantially increases the integrated level on printed circuit board (PCB) (PCB), reduces the volume and weight of electronic device, improves the performance of product.
As shown in Figure 1 and Figure 2, wherein, image sensor chip 1 comprises the pel array 3 be formed on the functional surfaces 2a of Semiconductor substrate 2 to the CSP packaging part of conventional images sensor chip; The back side 2b of Semiconductor substrate 2 is formed with the first insulating barrier 4, metal line layer 5, second insulating barrier 6 successively.
Along with the raising of integrated level; chip area reduces; especially front illuminated (FSI) imageing sensor; single pixel cell size is little; space for connecting the signal of telecommunication is very limited; such as, the ground connection of each pixel cell needs to be connected on the guard ring (guardring) 10 of pel array 3 periphery by Semiconductor substrate 2, and this guard ring 10 is connected to pad (PAD) 11 by metal interconnected again.For 2,000,000 pixel Pixel Dimensions 1.75 μm, pel array is 1600 ╳ 1200, be in the pixel cell P at pel array center and the minimum spacing L(=600 ╳ 1.75 μm at pel array edge) also can reach more than 1000 μm, current path is long, resistance substrate is large, circuit loss is large, and because each pixel cell is different from the distance between array edges, cause the resistance substrate difference of each pixel cell large, finally cause the inequality signal of pel array centerand edge even, the imaging performance of effect diagram image-position sensor.
In addition, for the imageing sensor adopting N-type substrate, when N-type substrate needs to connect power supply, usually will form darker ion implantation from Semiconductor substrate functional surfaces could be picked out, more difficult realization in technique, limits the thickness of the epitaxial loayer (EPI) in Semiconductor substrate.
Summary of the invention
The object of the present invention is to provide a kind of CSP method for packing and packaging part of image sensor chip, reduce resistance substrate and circuit loss, reduce the resistance substrate difference between each pixel cell, improve the signal uniformity of pel array centerand edge, improve the imaging performance of imageing sensor.
For achieving the above object, the present invention adopts following technical scheme:
One aspect of the present invention provides a kind of CSP method for packing of image sensor chip, comprising: provide image sensor chip, and described image sensor chip comprises the pel array be formed on Semiconductor substrate functional surfaces; Be connected with metal line layer at the described Semiconductor substrate back side, described metal line layer connects the signal of telecommunication by solder bump.
Preferably, the first insulating barrier, metal line layer, the second insulating barrier is formed successively in the described Semiconductor substrate back side, at least one through hole is formed in described first insulating barrier, filled conductive material in described through hole, described electric conducting material is electrically connected with the described Semiconductor substrate back side, metal line layer respectively.
Preferably, metal electrode layer, the first insulating barrier, metal line layer, the second insulating barrier is formed successively in the described Semiconductor substrate back side, described metal electrode layer is electrically connected with described electric conductor substrate back, at least one through hole is formed in described first insulating barrier, filled conductive material in described through hole, described electric conducting material is electrically connected with described metal electrode layer, metal line layer respectively.
Preferably, described Semiconductor substrate is P type substrate, described solder bump ground connection.
Preferably, described Semiconductor substrate is N-type substrate, and described solder bump connects power supply.
Preferably, the thickness of described Semiconductor substrate is 50 μm-200 μm.
Another aspect of the present invention provides a kind of CSP packaging part of image sensor chip, and described image sensor chip comprises the pel array be formed on Semiconductor substrate functional surfaces; The described Semiconductor substrate back side is connected with metal line layer, and described metal line layer connects the signal of telecommunication by solder bump.
Preferably, the described Semiconductor substrate back side is formed with the first insulating barrier, metal line layer, the second insulating barrier successively, at least one through hole is provided with in described first insulating barrier, be filled with electric conducting material in described through hole, described electric conducting material is electrically connected with the described Semiconductor substrate back side, metal line layer respectively.
Preferably, the described Semiconductor substrate back side is formed with metal electrode layer, the first insulating barrier, metal line layer, the second insulating barrier successively, described metal electrode layer is electrically connected with described electric conductor substrate back, at least one through hole is provided with in described first insulating barrier, be filled with electric conducting material in described through hole, described electric conducting material is electrically connected with described metal electrode layer, metal line layer respectively.
Preferably, described Semiconductor substrate is P type substrate, described solder bump ground connection.
Preferably, described Semiconductor substrate is N-type substrate, and described solder bump connects power supply.
Preferably, the thickness of described Semiconductor substrate is 50 μm-200 μm.
Compared with prior art, the present invention has following technique effect:
The CSP packaging part of image sensor chip of the present invention, shorten current path, reduce resistance substrate and circuit loss, reduce the resistance substrate difference between each pixel cell, improve the signal uniformity of pel array centerand edge, improve the imaging performance of imageing sensor.For the imageing sensor adopting N-type substrate, N-type substrate can connect power supply from the Semiconductor substrate back side, without the need to forming darker ion implantation from Semiconductor substrate functional surfaces, reducing technology difficulty, allowing larger EPI layer thickness.
Accompanying drawing explanation
By Figure of description and subsequently together with Figure of description for illustration of the embodiment of some principle of the present invention, the further feature that the present invention has and advantage will become clear or more specifically be illustrated.Wherein:
Fig. 1 is the cutaway view of the CSP packaging part of conventional images sensor chip;
Fig. 2 is the vertical view of the CSP packaging part of conventional images sensor chip;
Fig. 3 is the cutaway view of the CSP packaging part of image sensor chip according to the embodiment of the present invention 1;
Fig. 4 is the cutaway view of the CSP packaging part of image sensor chip according to the embodiment of the present invention 2.
Embodiment
For solving the problem of the even image quality difference of CSP packaging part inequality signal of conventional images sensor chip, one aspect of the present invention provides a kind of CSP method for packing of image sensor chip, comprise: provide image sensor chip, described image sensor chip comprises the pel array be formed on Semiconductor substrate functional surfaces; Be connected with metal line layer at the described Semiconductor substrate back side, described metal line layer connects the signal of telecommunication by solder bump.
Another aspect of the present invention provides a kind of CSP packaging part of image sensor chip, and described image sensor chip comprises the pel array be formed on Semiconductor substrate functional surfaces; The described Semiconductor substrate back side is connected with metal line layer, and described metal line layer connects the signal of telecommunication by solder bump.
The CSP packaging part of image sensor chip of the present invention, shorten current path, reduce resistance substrate and circuit loss, reduce the resistance substrate difference between each pixel cell, improve the signal uniformity of pel array centerand edge, improve the imaging performance of imageing sensor.For the imageing sensor adopting N-type substrate, N-type substrate can connect power supply from the Semiconductor substrate back side, without the need to forming darker ion implantation from Semiconductor substrate functional surfaces, reducing technology difficulty, allowing larger EPI layer thickness.
Below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
embodiment 1
Fig. 3 is the cutaway view of the CSP packaging part of image sensor chip according to the embodiment of the present invention 1.
As shown in Figure 3, image sensor chip 101 comprises the pel array 103 be formed on the functional surfaces 102a of Semiconductor substrate 102, the back side 102b of Semiconductor substrate 102 is formed with the first insulating barrier 104 successively, metal line layer 105, second insulating barrier 106, at least one through hole 108 is provided with in first insulating barrier 104, electric conducting material is filled with in this through hole 108, electric conducting material in this through hole 108 respectively with the back side 102b of Semiconductor substrate 102, metal line layer 105 is electrically connected, thus the back side 102b of electrical connection Semiconductor substrate 102 and metal line layer 105, metal line layer 105 connects the signal of telecommunication by solder bump 107, such as, when Semiconductor substrate 102 is P type substrate, described solder bump 107 ground connection, when Semiconductor substrate 102 is N-type substrate, described solder bump 107 connects power supply.
Compared to prior art, in the CSP packaging part of the present embodiment image sensor chip, each pixel cell of pel array only need through the thickness D(about 50 μm-200 μm of Semiconductor substrate), without the need to through pel array center to more than distance L(1000 μm of edge), shorten current path, reduce resistance substrate and circuit loss, reduce the resistance substrate difference between each pixel cell, improve the signal uniformity of pel array centerand edge, improve the imaging performance of imageing sensor.In addition, for the imageing sensor adopting N-type substrate, N-type substrate can connect power supply from the Semiconductor substrate back side, without the need to forming darker ion implantation from Semiconductor substrate functional surfaces, reducing technology difficulty, allowing larger EPI layer thickness.
Present invention also offers the CSP method for packing of this image sensor chip, comprise: image sensor chip 101 is provided, this image sensor chip 101 comprises the pel array 103 be formed on the functional surfaces 102a of Semiconductor substrate 102, the first insulating barrier 104 is formed successively in the back side 102b of Semiconductor substrate 102, metal line layer 105, second insulating barrier 106, at least one through hole 108 is formed in the first insulating barrier 104, filled conductive material in through hole 108, electric conducting material in this through hole 108 respectively with the back side 102b of Semiconductor substrate 102, metal line layer 105 is electrically connected, thus the back side 102b of electrical connection Semiconductor substrate 102 and metal line layer 105, metal line layer 105 connects the signal of telecommunication by solder bump 107, such as, when Semiconductor substrate 102 is P type substrate, described solder bump 107 ground connection, when Semiconductor substrate 102 is N-type substrate, described solder bump 107 connects power supply.
embodiment 2
Fig. 4 is the cutaway view of the CSP packaging part of image sensor chip according to the embodiment of the present invention 2.
As shown in Figure 4, image sensor chip 201 comprises the pel array 203 be formed on the functional surfaces 202a of Semiconductor substrate 202, the back side 202b of Semiconductor substrate 202 is formed with metal electrode layer 209 successively, first insulating barrier 204, metal line layer 205, second insulating barrier 206, wherein metal electrode layer 209 is electrically connected with the back side 202b of Semiconductor substrate 202, at least one through hole 208 is provided with in first insulating barrier 204, electric conducting material is filled with in this through hole 208, electric conducting material in this through hole 208 respectively with metal electrode layer 209, metal line layer 205 is electrically connected, thus the back side 202b of electrical connection Semiconductor substrate 202 and metal line layer 205, metal line layer 205 connects the signal of telecommunication by solder bump 207, such as, when Semiconductor substrate 202 is P type substrate, described solder bump 207 ground connection, when Semiconductor substrate 202 is N-type substrate, described solder bump 207 connects power supply.
In embodiment 1, based on the distribution of lead to the hole site, still there is some difference for the different pixels unit in pel array and the distance between through hole, therefore the resistance substrate of each pixel cell still slightly difference.And in the present embodiment, all pixel cells in pel array 203 are connected with metal line layer 205 after first linking same metal electrode layer 209 again, each pixel cell is roughly the same with the distance of metal electrode layer 209, and resistance substrate difference reduces further.Preferably, metal electrode layer 209 and area of metal electrode layer 209 corresponding with the position of pel array 203 is not less than the area of pel array 203, distance between each pixel cell and metal electrode layer 209 is equal to the thickness D(about 50 μm-200 μm of Semiconductor substrate 202), resistance substrate is identical, signal uniformity is better, substantially improves the imaging performance of imageing sensor.In addition, for the imageing sensor adopting N-type substrate, N-type substrate can connect power supply from the Semiconductor substrate back side, without the need to forming darker ion implantation from Semiconductor substrate functional surfaces, reducing technology difficulty, allowing larger EPI layer thickness.
Present invention also offers the CSP method for packing of this image sensor chip, comprise: image sensor chip 201 is provided, this image sensor chip 201 comprises the pel array 203 be formed on the functional surfaces 202a of Semiconductor substrate 202, first metal electrode layer 209 is formed by sputtering and/or electroplating technology in the back side 202b of Semiconductor substrate 202, this metal electrode layer 209 is electrically connected with the back side 202b of Semiconductor substrate 202, and then form the first insulating barrier 204 successively, metal line layer 205, second insulating barrier 206, at least one through hole 208 is formed in the first insulating barrier 204, filled conductive material in through hole 208, electric conducting material in this through hole 208 respectively with metal electrode layer 209, metal line layer 205 is electrically connected, thus the back side 202b of electrical connection Semiconductor substrate 202 and metal line layer 205, metal line layer 205 connects the signal of telecommunication by solder bump 207, such as, when Semiconductor substrate 202 is P type substrate, described solder bump 207 ground connection, when Semiconductor substrate 202 is N-type substrate, described solder bump 207 connects power supply.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a CSP method for packing for image sensor chip, is characterized in that, comprising:
There is provided image sensor chip, described image sensor chip comprises the pel array be formed on Semiconductor substrate functional surfaces;
Be connected with metal line layer at the described Semiconductor substrate back side, described metal line layer connects the signal of telecommunication by solder bump.
2. the CSP method for packing of image sensor chip as claimed in claim 1, it is characterized in that, the first insulating barrier, metal line layer, the second insulating barrier is formed successively in the described Semiconductor substrate back side, at least one through hole is formed in described first insulating barrier, filled conductive material in described through hole, described electric conducting material is electrically connected with the described Semiconductor substrate back side, metal line layer respectively.
3. the CSP method for packing of image sensor chip as claimed in claim 1, it is characterized in that, metal electrode layer, the first insulating barrier, metal line layer, the second insulating barrier is formed successively in the described Semiconductor substrate back side, described metal electrode layer is electrically connected with described electric conductor substrate back, at least one through hole is formed in described first insulating barrier, filled conductive material in described through hole, described electric conducting material is electrically connected with described metal electrode layer, metal line layer respectively.
4. the CSP method for packing of image sensor chip as claimed in claim 1, it is characterized in that, described Semiconductor substrate is P type substrate, described solder bump ground connection.
5. the CSP method for packing of image sensor chip as claimed in claim 1, it is characterized in that, described Semiconductor substrate is N-type substrate, and described solder bump connects power supply.
6. the CSP method for packing of image sensor chip as claimed in claim 1, it is characterized in that, the thickness of described Semiconductor substrate is 50 μm-200 μm.
7. a CSP packaging part for image sensor chip, is characterized in that,
Described image sensor chip comprises the pel array be formed on Semiconductor substrate functional surfaces;
The described Semiconductor substrate back side is connected with metal line layer, and described metal line layer connects the signal of telecommunication by solder bump.
8. the CSP packaging part of image sensor chip as claimed in claim 7, it is characterized in that, the described Semiconductor substrate back side is formed with the first insulating barrier, metal line layer, the second insulating barrier successively, at least one through hole is provided with in described first insulating barrier, be filled with electric conducting material in described through hole, described electric conducting material is electrically connected with the described Semiconductor substrate back side, metal line layer respectively.
9. the CSP packaging part of image sensor chip as claimed in claim 7, it is characterized in that, the described Semiconductor substrate back side is formed with metal electrode layer, the first insulating barrier, metal line layer, the second insulating barrier successively, described metal electrode layer is electrically connected with described electric conductor substrate back, at least one through hole is provided with in described first insulating barrier, be filled with electric conducting material in described through hole, described electric conducting material is electrically connected with described metal electrode layer, metal line layer respectively.
10. the CSP packaging part of image sensor chip as claimed in claim 7, it is characterized in that, described Semiconductor substrate is P type substrate, described solder bump ground connection.
The CSP packaging part of 11. image sensor chips as claimed in claim 7, it is characterized in that, described Semiconductor substrate is N-type substrate, and described solder bump connects power supply.
The CSP packaging part of 12. image sensor chips as claimed in claim 7, is characterized in that, the thickness of described Semiconductor substrate is 50 μm-200 μm.
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| CN201510674986.5A CN105261627A (en) | 2015-10-19 | 2015-10-19 | CSP method and part of image sensor chip |
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| CN201510674986.5A CN105261627A (en) | 2015-10-19 | 2015-10-19 | CSP method and part of image sensor chip |
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| CN101304015A (en) * | 2007-05-07 | 2008-11-12 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
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| CN103985722A (en) * | 2013-02-13 | 2014-08-13 | 拉碧斯半导体株式会社 | Semiconductor device and manufacture method thereof, and system including semiconductor device |
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2015
- 2015-10-19 CN CN201510674986.5A patent/CN105261627A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6498387B1 (en) * | 2000-02-15 | 2002-12-24 | Wen-Ken Yang | Wafer level package and the process of the same |
| CN101261984A (en) * | 2007-03-08 | 2008-09-10 | 育霈科技股份有限公司 | Structure of semiconductor device package and the method of the same |
| CN101304015A (en) * | 2007-05-07 | 2008-11-12 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101136418A (en) * | 2007-10-25 | 2008-03-05 | 上海交通大学 | Backlight type light gate type CMOS image sensor |
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Application publication date: 20160120 |