CN101296214A - Time orthogonal frequency division multiplexing modem - Google Patents
Time orthogonal frequency division multiplexing modem Download PDFInfo
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Abstract
The invention discloses a multiplexing modem of time orthogonal frequency-division, which relates to a modem device with restricted transmitting power, strong anti-frequency offset capability and the performance of resisting inter-symbol interference in the field of communication. The multiplexing modem of the invention comprises components such as a low-medium frequency modulator, a demodulator, an auxiliary multiplexer/demultiplexer, an intermediate frequency amplifier, a D/A converter, a low pass filter, a self-vibration module, a mixer, an adder, a band-pass filter and a power supply, etc.; by adopting TOFDM signals with quasi-constant envelop transmission, the modem of the invention realizes the performance of resisting the inter-symbol interference which is the same as that of the traditional OFDM technology, has the capability of collecting multipath, overcomes the problems of large peak-to-average power ratio and the bad capability of resisting frequency offset, and also realizes the purpose of the multiplexing modem of the time orthogonal frequency-division. The modem of the invention also has the advantages of high integration degree, small volume, light weight and good flexibility, etc. and is especially suitable for the field requiring for the modem with large-capacity wireless data transmission performance among strong multipath high-speed moving targets with seriously restricted power.
Description
Technical field
The present invention relates to a kind of time orthogonal frequency division multiplexing (the being called for short TOFDM) modulator-demodulator in the communications field, be specially adapted to the modem apparatus of the big capacity wireless data transmission between the serious limited strong multipath high-speed moving object of power.
Background technology
OFDM (OFDM) technology can effectively suppress the transmission impairment that strong multipath brings under certain condition, anti-intersymbol interference, anti-fading, outstanding advantage that the band efficiency height is the OFDM technology.But this technology has two outstanding defectives: peak-to-average power ratio of transmitter very big (〉=7) and anti-deviation capability are poor.In the radio communication between ground sky, absolutely empty big capacity omnidirectional antenna, because transmit power limited, and body and geomorphological features caused serious multipath transmisstion, in addition the relative high-speed motion of sourcesink, have very big Doppler frequency shift, so the OFDM The Application of Technology is greatly limited.
Summary of the invention
The objective of the invention is to avoid the weak point in the above-mentioned background technology and a kind of have accurate permanent envelope transmission, time orthogonal frequency division multiplexing modem that anti-deviation capability is strong be provided.The present invention not only has the performance of the opposing intersymbol interference identical with traditional OFDM technology, has the ability of collecting multipath, and overcome the problem of the big and anti-deviation capability difference of peak-to-average power ratio, also have characteristics such as integrated degree height, volume is little, in light weight, mobility is good.
The object of the present invention is achieved like this:
It comprises again auxiliary/coupler 1, Low Medium Frequency modulator 2, demodulator 3, intermediate frequency amplifier 4, D/A converter 5-1 to 5-2, low pass filter 6-1 to 6-2, local oscillator module 7-1 to 7-2, frequency mixer 8-1 to 8-2, adder 9, band pass filter 10, power supply 29, wherein assist the input port 1 of multiple/ coupler 1,2,5,6 respectively with the information code current A port of outside input, symbol clock B port, the output port 3 of demodulator 3,4 link to each other, its output port 3,4 respectively with Low Medium Frequency modulator 2 input ports 1,2, output port 7, the 8 outside respectively information code current C ports of exporting, symbol clock D port links to each other, the input port 1 of auxiliary multiplexer- demultiplexer 1,2 receive information code current respectively, symbol clock, input port 5,6 information code currents that demodulate of receiving demodulation device 3 respectively, symbol clock, output port 3,4 export the information code current after subdivision connects respectively, symbol clock is to Low Medium Frequency modulator 2, output port 7,8 export the information code current after the tap respectively, symbol clock; Low Medium Frequency modulator 2 output ports 3,4 link to each other with each input port 1 of D/A converter 5-1,5-2 respectively, each output port 2 of D/A converter 5-1 to 5-2 links to each other with each input port 1 of low pass filter 6-1 to 6-2 respectively, Low Medium Frequency modulator 2 exports the Low Medium Frequency modulation signal to D/A converter 5 respectively and carries out digital to analog conversion, and the signal after the digital to analog conversion carries out low-pass filtering again; Each input port 1,2 of frequency mixer 8-1 to 8-2 respectively with each output port 2 of low pass filter 6-1 to 6-2, each output port 1 of local oscillator module 7-1 to 7-2 links to each other, its output port 3 links to each other with the input port 1,2 of adder 9 respectively, frequency mixer 8 carries out mixing with the local oscillation signal and the signal after the low-pass filtering of 7 outputs of local oscillator module, and the signal after the mixing exports adder 9 to; The input port 1 of band pass filter 10 links to each other with the output port 3 of adder 9, and its output port 2 links to each other with sender input port E by immediate frequency cable, and band pass filter 10 carries out the sum signal of adder 9 outputs to export behind the bandpass filtering; The input port 1 of intermediate frequency amplifier 4 links to each other with receiver output port F by immediate frequency cable, its output port 2,3 is connected with the input port 1,2 of demodulator 3 respectively, intermediate frequency amplifier 4 carries out automatic gain control with the intermediate-freuqncy signal of input, signal after the control again with the local oscillation signal mixing of two different frequencies, two signals after the mixing export demodulator 3 respectively to; Power supply 29 goes out the corresponding power end with each parts of end+V voltage end and connects, the power supply that provides each parts to need.
Low Medium Frequency modulator 2 of the present invention comprises serial to parallel conversion module 11, time delay module 12-1 to 12-5, differential coding module 13-1 to 13-6, base band shaping module 14-1 to 14-6, first group of module 15-1 to 15-6 that multiplies each other, second group of the module 16-1 to 16-6 that multiplies each other, summation module 17-1 to 17-2, frequency division module 18, simple signal generation module 19, phase shift block 20; Described serial to parallel conversion module 11 inputs 1 pin links to each other with again auxiliary/coupler 1 output port 3, its output 2,3,4,5,6,7 pin respectively with differential coding module 13-1 input 1 pin, time delay module 12-1 to 12-5 input 1 pin links to each other, each output 2 pin of time delay module 12-1 to 12-5 link to each other with each input 1 pin of differential coding module 13-2 to 13-6 respectively, the serial code stream that serial to parallel conversion module 11 will assist subdivision to connect output carries out obtaining six tunnel parallel code streams behind the serial to parallel conversion, the first via exports differential coding module 13-1 to, the the second the road to the five the tunnel exports time delay module 12 respectively to delays time, code stream after the time-delay exports differential coding module 13 respectively to, and differential coding module 13 carries out input code flow to export base band shaping module 14 to behind the differential coding; Each input 1 pin of base band shaping module 14-1 to 14-6 links to each other with each output 2 pin of differential coding module 13-1 to 13-6 respectively, each output 2,3 pin respectively with first group of each input 1 pin of module 15-1 to 15-6 that multiplies each other, second group of each input 2 pin of module 16-1 to 16-6 that multiply each other links to each other, base band shaping module 14 is carried out base band shaping with the code stream of differential coding module 13 output respectively, and the base band shaping signal exports first group of module 15 of multiplying each other, second group of module 16 that multiplies each other respectively to; First group multiply each other each input 2 pin of module 15-1 to 15-3 respectively with simple signal generation module 19 outputs 1,2,3 pin link to each other, each output 3 pin respectively with summation module 17-1 input 1,3,5 pin link to each other, first group multiply each other each input 2 pin of module 15-4 to 15-6 respectively with simple signal generation module 19 outputs 1,2,3 pin link to each other, each output 3 pin respectively with summation module 17-2 input 1,3,5 pin link to each other, first group of module 15 that multiplies each other is respectively with carrier signal and the base band shaping signal multiplication imported, form I road modulation signal, I road modulation signal exports summation module 17 respectively to; Second group of each input 1 pin of module 16-1 to 16-3 that multiplies each other links to each other with phase shift block 20 outputs 4,5,6 pin respectively, and each output 3 pin links to each other with summation module 17-1 input 2,4,6 pin respectively; Second group of each input 1 pin of module 16-4 to 16-6 that multiplies each other links to each other with phase shift block 20 outputs 4,5,6 pin respectively, each output 3 pin links to each other with summation module 17-2 input 2,4,6 pin respectively, second group of carrier wave and base band shaping signal multiplication that the module 16 that multiplies each other is exported phase shift block respectively, form Q road modulation signal, Q road modulation signal exports summation module 17 respectively to; Each output 7 pin of summation module 17-1 to 17-2 link to each other with each input port 1 of D/A converter 5-1 to 5-2 respectively, and summation module 17 exports the signal after the addition to D/A converter 5 respectively; Frequency division module 18 inputs 1 pin links to each other with again auxiliary/coupler 1 output port 4, and its output 2 pin link to each other with serial to parallel conversion module 11 inputs 8 pin, and frequency division module 18 carries out frequency division with the symbol clock of input; Phase shift block 20 inputs 1,2,3 pin link to each other with simple signal generation module 19 outputs 1,2,3 pin respectively, and phase shift block is carried out phase shift respectively with simple signal; Serial to parallel conversion module 11, time delay module 12-1 to 12-5, differential coding module 13-1 to 13-6, base band shaping module 14-1 to 14-6, first group of module 15-1 to 15-6 that multiplies each other, second group of 16-1 to 16-6, summation module 17-1 to 17-2, frequency division module 18, simple signal generation module 19, phase shift block 20 each input 9 pin go out end+V voltage end with power supply 29 and are connected, each input 10 pin is connected with earth terminal, power supply 29 provides the operating voltage of each module, and the ground end is with each module earth terminal.
The present invention compares background technology and has following advantage:
1. the Low Medium Frequency modulator 2 that adopts of the present invention, by the prime information code stream is divided into six the tunnel, and transmit with six frequencies, increased the length of channel signal,, made the amplitude peak quadrature form the time orthogonal frequency division multiplexing symbol transmission in time to improve the ability of the intersymbol interference that the opposing multipath causes, compare with the OFDM technology, reduce peak-to-average power ratio, six frequency signals have been had approach 1 peak-to-average power ratio, realized the function that rake receives simultaneously.
2. the demodulator 3 of the present invention's employing has been realized the distortion adaptive coherent demodulation by six tunnel time orthogonal frequency division multiplexing signals of forming, and has realized the performance of good opposing intersymbol interference.
3. major part of the present invention adopts extensive field programmable device to make, and therefore can realize neatly modification to this device operating parameters the structure of equipment being simplified greatly by disposing different programs, and cost significantly reduces.
4. the integrated degree height of the present invention, so volume is little, in light weight, stable and reliable for performance, easy to maintenance, the equipment maneuverability obviously improves.
Description of drawings
Fig. 1 is the present invention's electricity functional-block diagram.
Fig. 2 is the electrical schematic diagram of Low Medium Frequency modulator 2 embodiment of the present invention.
Fig. 3 is the electrical schematic diagram of demodulator 3 embodiment of the present invention.
Embodiment
Referring to figs. 1 through Fig. 3, the present invention is made up of again auxiliary/coupler 1, Low Medium Frequency modulator 2, demodulator 3, intermediate frequency amplifier 4, D/A converter 5-1 to 5-2, low pass filter 6-1 to 6-2, local oscillator module 7-1 to 7-2, frequency mixer 8-1 to 8-2, adder 9, band pass filter 10, power supply 29.Fig. 1 is an electric functional-block diagram of the present invention, and embodiment presses Fig. 1 connection line.Wherein the effect of again auxiliary/coupler 1 is by port B incoming symbol clock, and input port A input external information code stream carry out the branch frame and handle, and information code current, the symbol clock that will divide frame to handle offers Low Medium Frequency modulator 2 by output port 3,4; Composite bit stream that receiving demodulation device 3 demodulates and symbol clock go frame to handle, and isolate business information and export to outside letter sign indicating number port C, and the output symbol clock is to external symbol clock port D simultaneously.Embodiment assists, and multiple/coupler 1 adopts U.S. Alterna company to produce Stratix Series FPGA chip manufacturing.
The input port 1,2 of Low Medium Frequency modulator 2 of the present invention is imported information code current, the clock of output port 3,4 outputs of again auxiliary/coupler 1 respectively, and information code current is modulated into two-way Low Medium Frequency time orthogonal frequency division multiplexing signal, by the output port 3,4 of Low Medium Frequency modulator 2 the two-way Low Medium Frequency signal that forms is delivered to D/A converter 5-1 and 5-2 respectively.It is made up of serial to parallel conversion module 11, time delay module 12-1 to 12-5, differential coding module 13-1 to 13-6, base band shaping module 14-1 to 14-6, first group of module 15-1 to 15-6 that multiplies each other, second group of the module 16-1 to 16-6 that multiplies each other, summation module 17-1 to 17-2, frequency division module 18, simple signal generation module 19, phase shift block 20.Fig. 2 is the electrical schematic diagram of Low Medium Frequency modulator 2 of the present invention, and embodiment presses Fig. 2 connection line.
The effect of serial to parallel conversion module 11 is that the information code current of/coupler 1 output multiple with assisting carries out serial to parallel conversion, and it is divided into parallel 6 the tunnel, differential coding module 13-1 is delivered in the output of the 1st route output port 2 pin, and the 2 the road to the 5 the tunnel sends into time delay module 12-1 to 12-5 through the output of output port 3 to 7 pin respectively.Time delay module 12-1 to 12-5 sends 5 tunnel parallel code streams of serial to parallel conversion module output, 1/6～5/6 symbol period of delaying time respectively into differential coding module 13-2 to 13-6 then.The effect of differential coding module 13-1 to 13-6 is that the code stream information of input is carried out exporting to base band shaping module 14-1 to 14-6 behind the differential coding.The code stream information of base band shaping module 14-1 to 14-6 input difference coding module 13-1 to 13-6 output, and it is carried out base band shaping handle the formation raised cosine singal.Frequency division module 18 carries out frequency division with the clock signal of input, forms the clock control signal of each module of Low Medium Frequency modulator 2.Simple signal generation module 19 produces 3 single-frequency carrier signals, is used for the base band shaping signal mixing to Low Medium Frequency, and first group of multiply each other module 15-1 to 15-6 and phase shift block 20 are sent in its output.Phase shift block 20 is used for that simple signal generation module 19 is produced three single carriers and carries out 90 ° of phase shifts.First group of module 15-1 to 15-3 that multiplies each other multiplies each other the raised cosine singal of three single carriers and base band shaping module 14-1 to 14-3 output respectively, forms the I tributary signal that 3 tunnel parallel QPSK modulate; First group of module 15-4 to 15-6 that multiplies each other forms the I tributary signal of other 3 tunnel parallel QPSK modulation.Second group of module 16-1 to 16-3 that multiplies each other multiplies each other the raised cosine singal of three single-frequency carrier waves after 90 ° of phase shifts and base band shaping module 14-1 to 14-3 output respectively, forms the Q tributary signal of 3 tunnel parallel QPSK modulation; Second group of module 16-4 to 16-6 that multiplies each other forms the Q tributary signal that other 3 tunnel parallel QPSK modulate.Summation module 17-1 superposes preceding 3 road I branch roads, Q tributary signal, and summation module 17-2 superposes back 3 road I branch roads, Q tributary signal, forms the time orthogonal frequency division multiplexing signal of 3 frequencies in the two-way band, and be 1/2 symbol period the relative time delay of two paths of signals.Embodiment serial to parallel conversion module 11, time delay module 12-1 to 12-5, differential coding module 13-1 to 13-6, base band shaping module 14-1 to 14-6, first group of module 15-1 to 15-6 that multiplies each other, second group of the module 16-1 to 16-6 that multiplies each other, summation module 17-1 to 17-2, frequency division module 18, simple signal generation module 19 and phase shift block 20 all adopt a U.S. Alterna company to produce Stratix Series FPGA chip manufacturing.
This uses novel D/A converter 5-1 and 5-2 will become analog signal by the two-way numeral Low Medium Frequency signal of Low Medium Frequency modulator 2 outputs respectively, and sends into low pass filter 6-1 to 6-2 respectively.The effect of low pass filter 6-1 to 6-2 is respectively two-way to be simulated the Low Medium Frequency signal to carry out exporting frequency mixer 8-1 and 8-2 to after the low-pass filtering.Local oscillator module 7-1 and 7-2 produce the intermediate frequency subcarrier of two different frequencies respectively, and send into frequency mixer 8-1 and 8-2.The purpose of frequency mixer 8-1 and 8-2 be two-way Low Medium Frequency signal respectively with the subcarrier mixing, form the two-way intermediate-freuqncy signal, and flow to adder 9.Adder 9 superposes the two-way intermediate-freuqncy signal of input, forms the intermediate frequency time orthogonal frequency division multiplexing signal of 6 frequencies in one road band.After the intermediate frequency time orthogonal frequency division multiplexing signal that band pass filter 10 is exported adder 9 carries out bandpass filtering, export sender input port E to.Implement the AD9763 cake core making that ice-cold D/A converter 5-1 and 5-2 adopt U.S. A/D company to produce.The AD9854 cake core that local oscillator module 7-1 and 7-2 adopt U.S. A/D company to produce is made.The HSB3 frequency mixer that frequency mixer 8-1 and 8-2 adopt Chengdu Asia Optical to produce is made.The SBP-70 type band pass filter that band pass filter 10 adopts the company in sky, Chengdu to produce is made.
The effect of demodulator 3 of the present invention is with after 3 frequently time orthogonal frequency division multiplexing signal transformations obtain base band time orthogonal frequency division multiplexing signal in the two-way band, detects through the distortion adaptive coherent it is carried out demodulation, recovers source code flow information.It is made up of A/D converter 21-1 to 21-2, Digital Down Converter Module 22-1 to 22-6, coherent detection module 23-1 to 23-6, integration judging module 24-1 to 24-6, differential decoding module 25-1 to 25-6, odd coupling road module 26-1 to 26-6, parallel serial conversion module 27, bit synchronization module 28, Fig. 3 is the electrical schematic diagram of demodulator 3 of the present invention, and embodiment presses Fig. 3 connection line.Wherein A/D converter 21-1 and 21-2 receive the two-way simulation Low Medium Frequency time orthogonal frequency division multiplexing signal of the output port 2,3 of intermediate frequency amplifier 4, and by sampling it are become digital signal.
Digital Down Converter Module 22-1 to 22-3 and Digital Down Converter Module 22-4 to 22-6 import the Low Medium Frequency time orthogonal frequency division multiplexing signal by 3 frequencies in the band of A/D converter 21-1 and 2 outputs of 21-2 outbound port respectively, and it is down-converted to zero intermediate frequency, obtain 6 tunnel parallel base band time orthogonal frequency division multiplexing signals, each road is divided into I, Q tributary signal, respectively by the output of port 2,3 pin.The effect of coherent detection module 23-1 to 23-6 be respectively to 6 tunnel of Digital Down Converter Module 22-1 to 22-6 output parallel base band time orthogonal frequency division multiplexing signals by the demodulation of distortion adaptive coherent, detect multipath synthetic the time become waveform, play the effect of rake simultaneously.Bit synchronization module 28 is extracted by bit synchronous and is handled, and produces several timing pulse signals, and a kind of pulse signal that is used for integration judgement usefulness flows to integration judging module 26-1 to 26-6 and uses; Another kind is used for the timing pulse signal of the synthetic usefulness of code stream, offers parallel serial conversion module 27 and uses, and timing pulse signal is exported to the input port 6 of again auxiliary/coupler 1 by port 2 pin.Under the control of the bit synchronization signal of integration judging module 24-1 to 24-6 synchronization module 28 outputs on the throne, respectively 6 tunnel coherent signals that comprise I, Q branch road of coherent detection module 23-1 to 23-6 output are carried out the pure breath of integration and recovered digital information in code element sampling finish time judgement.The effect of differential decoding module 25-1 to 25-6 is respectively the digital information of integration judging module 24-1 to 24-6 output to be carried out differential decoding, determines original digital information.Odd coupling road module 26-1 to 26-6 is respectively applied for I, the Q branch road digital information of differential decoding module 25-1 to 25-6 output is carried out the odd coupling road, and flows to parallel serial conversion module 27.Parallel serial conversion module 27 receives 6 road digital informations that walk abreast of odd coupling road module 26-1 to 26-6 output, and under the control of the bit synchronization signal of synchronization module 28 outputs on the throne, recover original transmitted information by parallel serial conversion, export the input port 6 of again auxiliary/coupler 1 to.Embodiment Digital Down Converter Module 22-1 to 22-6, coherent detection module 23-1 to 23-6, integration judging module 24-1 to 24-6, differential decoding module 25-1 to 25-6, odd coupling road module 26-1 to 26-6, parallel serial conversion module 27, bit synchronization module 28 all adopt a U.S. Alterna company to produce Stratix Series FPGA chip manufacturing.AD9218 type and AD6604 integrated chip that A/D converter 21-1 and 21-2 adopt U.S. A/D company to produce are made.
The concise and to the point operation principle of the present invention is as follows:
During transmission information, again auxiliary/coupler 1 carries out the processing of branch frame with the continuous letter sign indicating number of external business information end A input.Low Medium Frequency modulator 2 is the framing information of again auxiliary/coupler 1 output, be divided into 6 tunnel parallel code streams, and delay time respectively to 2 to 6 the tunnel, so that form the time quadrature signal of accurate permanent envelope, again differential coding is carried out on each road, carry out base band shaping then and handle formation raised cosine baseband signal, like this by method along separate routes, the symbol period on every road becomes original 6 times, has expanded mark space, has strengthened the ability of anti-intersymbol interference; With 1, the 4 tunnel and first Low Medium Frequency carrier frequency mixing, 2nd, 5 tunnel and second Low Medium Frequency carrier frequency mixings, 3rd, 6 tunnel and the 3rd Low Medium Frequency carrier frequency mixings, the frequency of three Low Medium Frequency carrier waves has certain intervals, afterwards, preceding 3 road signals and back 3 road signals are carried out superposition respectively, form 3 frequency time orthogonal frequency division multiplexing signals in the two-way band.After process D/A conversion of two-way Low Medium Frequency modulation signal and the low-pass filtering, carry out mixing with the subcarrier signal of two different frequencies respectively again, two paths of signals phase superposition after the mixing, form the intermediate frequency time orthogonal frequency division multiplexing signal of 6 frequencies in one road band, it is carried out can sending into sender behind the bandpass filtering.Time orthogonal frequency division multiplexing signal by 6 frequencies in the band that forms, expanded mark space, can realize the ability of the intersymbol interference that good anti-multipath causes, sort signal has the characteristics of permanent envelope simultaneously, can realize when promptly transmitting that peak-to-average power ratio is 1, avoid the excessive power that brings of peak-to-average power ratio to use problem.
During reception information, intermediate frequency amplifier 4 receives the intermediate-freuqncy signal from receiver output port F, after it is amplified, after carrying out respectively carrying out low-pass filtering again after the mixing with the local oscillator of two different frequencies, form the Low Medium Frequency time orthogonal frequency division multiplexing signal of 3 frequencies in the two-way band, send into demodulator 3 then.In demodulator 3, after two-way Low Medium Frequency signal carried out A/D sampling, finish conversion from the Low Medium Frequency to the zero intermediate frequency by Digital Down Convert, the Low Medium Frequency time orthogonal frequency division multiplexing signal transformation of every road is 3 tunnel parallel zero intermediate frequency signals, then can obtain 6 tunnel parallel baseband signals, this signal is sent into coherent detection module 23-1 to 23-6 more respectively and is carried out the demodulation of distortion adaptive coherent subsequently, under the bit synchronization clock control that synchronization module 28 on the throne provides, 6 road signals after the demodulation obtain binary digital information through the integration judgement, and then pass through differential decoding respectively, obtain 6 tunnel parallel digital information code streams behind the odd coupling road, 6 road code streams can recover original transmitted information through after the parallel/serial conversion at last again.
Mounting structure of the present invention is as follows:
It is in the printed board of 135 * 260mm that all circuit devcies among Fig. 1 to Fig. 3 are installed in two length and widths, then printed board being installed in a length is in the cabinet of 320 * 285 * 128mm, the cable socket of letter sign indicating number inbound port A, symbol clock inbound port B, letter sign indicating number outbound port C, symbol clock outbound port D is installed on the front panel of cabinet, install sender in the back on the plate and go out cable socket and the power input socket that inbound port E, receiver go out inbound port F, the assembly cost invention.
Claims (3)
1. orthogonal frequency division multiplexing modem, it comprises again auxiliary/coupler (1), intermediate frequency amplifier (4), D/A converter (5-1) is to (5-2), low pass filter (6-1) is to (6-2), local oscillator module (7-1) is to (7-2), frequency mixer (8-1) is to (8-2), adder (9), band pass filter (10), power supply (29), it is characterized in that: also comprise Low Medium Frequency modulator (2), demodulator (3), wherein assist the input port 1 of multiple/coupler (1), 2,5,6 respectively with the information code current A port of outside input, symbol clock B port, the output port 3 of demodulator (3), 4 link to each other, its output port 3,4 respectively with Low Medium Frequency modulator (2) input port 1,2, output port 7, the 8 outside respectively information code current C ports of exporting, symbol clock D port links to each other, the input port 1 of auxiliary multiplexer-demultiplexer (1), 2 receive information code current respectively, symbol clock, input port 5, the information code current that 6 difference receiving demodulation devices (3) demodulate, symbol clock, output port 3,4 export the information code current after subdivision connects respectively, symbol clock is to Low Medium Frequency modulator (2), output port 7,8 export the information code current after the tap respectively, symbol clock; Low Medium Frequency modulator (2) output port 3,4 links to each other with each input port 1 of D/A converter (5-1), (5-2) respectively, each output port 2 of D/A converter (5-1) to (5-2) links to each other with each input port 1 of low pass filter (6-1) to (6-2) respectively, Low Medium Frequency modulator (2) exports the Low Medium Frequency modulation signal to D/A converter (5) respectively and carries out digital to analog conversion, and the signal after the digital to analog conversion carries out low-pass filtering again; Each input port 1,2 of frequency mixer (8-1) to (8-2) respectively with each output port 2 of low pass filter (6-1) to (6-2), each output port 1 of local oscillator module (7-1) to (7-2) links to each other, its output port 3 links to each other with the input port 1,2 of adder (9) respectively, frequency mixer (8) carries out mixing with the local oscillation signal and the signal after the low-pass filtering of local oscillator module (7) output, and the signal after the mixing exports adder (9) to; The input port 1 of band pass filter (10) links to each other with the output port 3 of adder (9), its output port 2 links to each other with sender input port E by immediate frequency cable, and band pass filter (10) carries out the sum signal of adder (9) output to export behind the bandpass filtering; The input port 1 of intermediate frequency amplifier (4) links to each other with receiver output port F by immediate frequency cable, its output port 2,3 is connected with the input port 1,2 of demodulator (3) respectively, intermediate frequency amplifier (4) carries out automatic gain control with the intermediate-freuqncy signal of input, signal after the control again with the local oscillation signal mixing of two different frequencies, two signals after the mixing export demodulator (3) respectively to; Power supply (29) goes out the corresponding power end with each parts of end+V voltage end and connects, the power supply that provides each parts to need.
2. according to the described time orthogonal frequency division multiplexing modem of claim 1, it is characterized in that: Low Medium Frequency modulator (2) comprises serial to parallel conversion module (11), time delay module (12-1) to (12-5), differential coding module (13-1) to (13-6), base band shaping module (14-1) to (14-6), first group of module that multiplies each other (15-1) to (15-6), second group of module that multiplies each other (16-1) to (16-6), summation module (17-1) to (17-2), frequency division module (18), simple signal generation module (19), phase shift block (20); Described serial to parallel conversion module (11) input 1 pin links to each other with again auxiliary/coupler (1) output port 3, its output 2,3,4,5,6,7 pin respectively with differential coding module (13-1) input 1 pin, time delay module (12-1) to (12-5) input 1 pin links to each other, each output 2 pin of time delay module (12-1) to (12-5) link to each other with each input 1 pin of differential coding module (13-2) to (13-6) respectively, the serial code stream that the serial to parallel conversion module will assist subdivision to connect output carries out obtaining six tunnel parallel code streams behind the serial to parallel conversion, the first via exports differential coding module (13) to, the the second the road to the five the tunnel exports time delay module (12) respectively to delays time, code stream after the time-delay exports differential coding module (13) respectively to, and differential coding module (13) carries out input code flow to export base band shaping module (14) to behind the differential coding; Each input 1 pin of base band shaping module (14-1) to (14-6) links to each other with each output 2 pin of differential coding module (13-1) to (13-6) respectively, each output 2,3 pin respectively with each input 1 pin of first group of module that multiplies each other (15-1) to (15-6), each input 2 pin of second group of module that multiplies each other (16-1) to (16-6) link to each other, base band shaping module (14) is carried out base band shaping with the code stream of differential coding module (13) output respectively, and the base band shaping signal exports first group of module that multiplies each other (15), second group of module that multiplies each other (16) respectively to; Each input 2 pin of first group of module that multiplies each other (15-1) to (15-3) respectively with simple signal generation module (19) output 1,2,3 pin link to each other, each output 3 pin respectively with summation module (17-1) input 1,3,5 pin link to each other, each input 2 pin of first group of module that multiplies each other (15-4) to (15-6) respectively with simple signal generation module (19) output 1,2,3 pin link to each other, each output 3 pin respectively with summation module (17-2) input 1,3,5 pin link to each other, first group of module that multiplies each other (15) is respectively with carrier signal and the base band shaping signal multiplication imported, form I road modulation signal, I road modulation signal exports summation module (17) respectively to; Each input 1 pin of second group of module that multiplies each other (16-1) to (16-3) links to each other with phase shift block (20) output 4,5,6 pin respectively, and each output 3 pin links to each other with summation module (17-1) input 2,4,6 pin respectively; Each input 1 pin of second group of module that multiplies each other (16-4) to (16-6) links to each other with phase shift block (20) output 4,5,6 pin respectively, each output 3 pin links to each other with summation module (17-2) input 2,4,6 pin respectively, carrier wave and base band shaping signal multiplication that second group of module that multiplies each other (16) exported phase shift block respectively, form Q road modulation signal, Q road modulation signal exports summation module (17) respectively to; Each output 7 pin of summation module (17-1) to (17-2) link to each other with each input port 1 of D/A converter (5-1) to (5-2) respectively, and summation module (17) exports the signal after the addition to D/A converter (5) respectively; Frequency division module (18) input 1 pin links to each other with again auxiliary/coupler (1) output port 4, and its output 2 pin link to each other with serial to parallel conversion module (11) input 8 pin, and frequency division module (18) carries out frequency division with the symbol clock of input; Phase shift block (20) input 1,2,3 pin link to each other with simple signal generation module (19) output 1,2,3 pin respectively, and phase shift block (19) is carried out phase shift respectively with simple signal; Serial to parallel conversion module (11), time delay module (12-1) is to (12-5), differential coding module (13-1) is to (13-6), base band shaping module (14-1) is to (14-6), first group of module that multiplies each other (15-1) is to (15-6), second group (16-1) is to (16-6), summation module (17-1) is to (17-2), frequency division module (18), simple signal generation module (19), each input 9 pin of phase shift block (20) go out end+V voltage end with power supply (29) and are connected, each input 10 pin is connected with earth terminal, power supply provides the operating voltage of each module, and the ground end is with each module earth terminal.
3. time orthogonal frequency division multiplexing modem according to claim 1 and 2 is characterized in that: demodulator (3) comprises A/D converter (21-1) to (21-2), Digital Down Converter Module (22-1) to (22-6), coherent detection module (23-1) to (23-6), integration judging module (24-1) to (24-6), differential decoding module (25-1) to (25-6), odd coupling road module (26-1) to (26-6), parallel serial conversion module (27), bit synchronization module (28); Each input 1 pin of described A/D converter (21-1) to (21-2) respectively with the output port 2 of intermediate frequency amplifier (4), 3 link to each other, each input 1 pin of Digital Down Converter Module (22-1) to (22-3) links to each other with A/D converter (21-1) output 2 pin, each input 1 pin of Digital Down Converter Module (22-4) to (22-6) links to each other with A/D converter (21-2) output 2 pin, each output 2 of Digital Down Converter Module (22-1) to (22-6), 3 pin respectively with each input 1 of coherent detection module (23-1) to (23-6), 2 pin link to each other, A/D converter (21) carries out analog to digital conversion with the intermediate frequency amplifying signal of input respectively, signal after the analog to digital conversion exports Digital Down Converter Module (22) respectively to and transforms to zero intermediate frequency, and zero intermediate frequency signals exports coherent detection module (23) to; Each input 1,2 pin of integration judging module (24-1) to (24-6) link to each other with each output 3,4 pin of coherent detection module (23-1) to (23-6) respectively, each output 3,4 pin links to each other with each input 1,2 pin of differential decoding module (25-1) to (25-6) respectively, integration judging module (24) is carried out the integration judgement with the coherent detection signal of input respectively, and the code word that rules out exports differential decoding module (25) respectively to; Each input 1,2 pin of odd coupling road module (26-1) to (26-6) link to each other with each output 3,4 pin of differential decoding module (25-1) to (25-6) respectively, each output 3 pin links to each other with parallel serial conversion module (27) input 1,2,3,4,5,6 pin respectively, odd coupling road module (26) is carried out the odd coupling road with the information code current of input respectively, and the signal behind the odd coupling road exports parallel serial conversion module (27) respectively to; Parallel serial conversion module (27) input 7 pin link to each other with bit synchronization module (28) output 2 pin, output 8 pin link to each other with again auxiliary/coupler (1) input port 5, the parallel code stream that parallel serial conversion module (27) will be imported is transformed into serial code stream, and serial code stream exports again auxiliary/coupler (1) to; Bit synchronization module (28) output 1 pin links to each other with each input 5 pin of integration judging module (24-1) to (24-6) respectively, output 2 pin link to each other with again auxiliary/coupler (1) input port 6, bit synchronization module (28) produces bit synchronization signal, and bit synchronization signal exports integration judging module (24), again auxiliary/coupler (1) to; A/D converter (21-1) to (21-2), Digital Down Converter Module (22-1) to (22-6), coherent detection module (23-1) to (23-6), integration judging module (24-1) to (24-6), differential decoding module (25-1) to (25-6), odd coupling road module (26-1) to (26-6), parallel serial conversion module (27), each input 9 pin of bit synchronization module (28) go out end+V voltage end with power supply (29) and are connected, each input 10 pin is connected with earth terminal, power supply (29) provides the operating voltage of each module, and the ground end is with each module earth terminal.
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