CN201252555Y - Speed self-adaptive scatter communication modem - Google Patents
Speed self-adaptive scatter communication modem Download PDFInfo
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- CN201252555Y CN201252555Y CNU2008201056343U CN200820105634U CN201252555Y CN 201252555 Y CN201252555 Y CN 201252555Y CN U2008201056343 U CNU2008201056343 U CN U2008201056343U CN 200820105634 U CN200820105634 U CN 200820105634U CN 201252555 Y CN201252555 Y CN 201252555Y
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Abstract
The utility model discloses a speed self-adaptive scatter communication modem relating to a scatter communication modem of the speed self-adaptive technique in the field of communication. The modem comprises a network protocol transducer, a speed self-adaptive controller, a speed self-adaptive modem, a communication channel detector, a digital phase-locked loop, an A/D transducer, a D/A transducer, a local oscillator module, a frequency mixer, a filter amplifier and other parts. The modem adopts the speed self-adaptive technique to enable the scatter communication system to always work at the optimum speed of the communication channel and to change following the fluctuation transmission speed of the received electrical level. The modem is further provided with the self-adapting on the transmission distance and is characterized in that the speed is switched nondestructively under the condition that the communication channel is changed, the communication capacity of the scatter communication system covers the full speed of small, middle and big capacities and the like, the modem is suitable for the device of the modem of the scatter communication system for transmitting IP network data.
Description
Technical field
The utility model relates to a kind of rate adaptation scatter communication modulator-demodulator in the communications field, is specially adapted to do intelligent rate adaptation tracking under the channel slow fading characteristic, with the scatter communication system modulation-demodulation device of transmission ip network number certificate.
Background technology
Traditional scatter communication is adopted constant transmissions speed according to link calculation, in the scatter channel level fluctuation time period, higher incoming level causes waste to transmission equipment, reduced the information transfer efficiency of scattering equipment, can not on former scatter communication Equipment Foundations, adopt the many speed rates that are suitable for network IP data, and can not be when channel level rises and falls the transmission capacity of adaptively modifying channel, range of application is little, can not satisfy customer requirements.
Summary of the invention
The purpose of this utility model is to avoid the weak point in the above-mentioned background technology and provides a kind of to have the Channel Detection function and make equipment always work in rate adaptation scatter communication modulator-demodulator on the iptimum speed of current channel.The utility model modulator-demodulator replaces group of stability road speed with transmission network IP data, also eliminated the reduction of the efficiency of transmission that channel incoming level fluctuating conversion causes, detect variations of fading channels Adaptive Transmission speed in real time, reach higher efficiency of transmission, traditional scatter communication equipment is changed to the IP network transfer function, the needs that adapt to the user network business, also has the harmless switching of speed, the scatter communication of many speed such as that message capacity covers is little, neutralization is big, characteristics such as device structure is simple.
The purpose of this utility model is achieved in that
It comprises network protocol converter 1, rate adaptation multiplexer 2, rate adaptation Low Medium Frequency modulator 3, D/A converter 4, local oscillator module 5, frequency mixer 6, band pass filter 7, amplifier 8, intermediate frequency amplifier 9, A/D converter 10, rate adaptation demodulator 11, rate adaptation coupler 12, channel detector 13, rate adaptation controller 14 digital phase-locked loops 15, power supply 28, described network protocol converter 1 input port 7,8 by holding wire respectively with input port A, B connects, its input port 1,2 export clock ports 1 with rate adaptation multiplexer 2 respectively, control port 2 links to each other, and its output port 3 links to each other with rate adaptation multiplexer 2 input letter sign indicating number ports 3; The input port 1,2 of rate adaptation Low Medium Frequency modulator 3 links to each other with output letter sign indicating number port 4, the clock port 5 of rate adaptation multiplexer 2 respectively, and its output port 3 links to each other with D/A converter 4 input ports 1 by data/address bus; Frequency mixer 6 input ports 1,2 link to each other with D/A converter 4 output ports 2, local oscillator module 5 output ports 1 by holding wire respectively, and its output port 3 links to each other with band pass filter 7 input ports 1 by holding wire; Amplifier 8 input ports 1 link to each other with band pass filter 7 output ports 2 by holding wire, and output port 2 links to each other with the outbound port C that transmits by holding wire; Intermediate frequency amplifier 9 input ports 1 link to each other with received signal inbound port D by immediate frequency cable, the outbound port C that transmits is connected by wireless transmission/received signal with received signal inbound port D, and intermediate frequency amplifier 9 output ports 2 link to each other with A/D converter (10) input port 1; Rate adaptation demodulator 11 input ports 1 link to each other with A/D converter 10 output ports 2 by data/address bus, and its output port 2,3 links to each other with rate adaptation coupler 12 input letter sign indicating number port ones, clock port 2 respectively; The input port 4,5,6 of network protocol converter 1 links to each other with letter sign indicating number port 3, clock port 4, the control port 5 of rate adaptation coupler 12 output respectively, and 9,10 of its output ports are connected with output port E, port F respectively by holding wire; Rate adaptation coupler 12 each input port 6, output port 7,8,9 link to each other with rate adaptation controller 14 each output port 2, input port 6,7,8 respectively; Channel detector 13 input ports 1 to 8 pin links to each other with A/D converter 10 output ports 3 to 10 respectively by data/address bus, and its output port 9 links to each other with rate adaptation controller 14 input ports 1 by data/address bus; Rate adaptation controller 14 each output port 3,4,5 by control bus respectively with the input port 6 of rate adaptation multiplexer 2, the input port 4 of rate adaptation Low Medium Frequency modulator 3, the input port 4 of rate adaptation demodulator 11; Digital phase-locked loop 15 input ports 1 link to each other by the steady clock G of immediate frequency cable and height port, and output port 2,3 links to each other with rate adaptation demodulator 3 input ports 5, rate adaptation Low Medium Frequency modulator 11 input ports 5 respectively; The corresponding power end with each parts of power supply 28 outputs+V voltage end also connects.
The utility model channel detector 13 comprises that code element A/D merges module group 16-1 to 16-4, interface and sequential control module group 17-1 to 17-4, FFT processing module group 18-1 to 18-4, calibration module group 19-1 to 19-4, amplitude delivery module group 20-1 to 20-4, amplitude merges module 21, data cache module 22, described code element A/D merge each input port 1 pin of module group 16-1 to 16-4 respectively with the output port 3 of A/D converter 10,5,7,9 link to each other, its each input port 2 pin respectively with the output port 4 of A/D converter 10,6,8,10 link to each other, and its each output port 3 pin are connected in series interface and sequential control module group 17-1 to 17-4 successively by data/address bus respectively, FFT processing module group 18-1 to 18-4, calibration module group 19-1 to 19-4, amplitude delivery module group 20-1 to 20-4 respectively goes into, outbound port 1, merge module 21 each input port 3 with amplitude behind 2 pin, 1,2,4 pin connect; Data cache module 22 input ports 1 pin is connected with output port 5 pin that amplitude merges module 21 by data/address bus, and its output port 2 pin are connected with the input port 1 of rate adaptation controller 14 by data/address bus; Code element A/D merges module group 16-1 to 16-4, interface and sequential control module group 17-1 to 17-4, FFT processing module group 18-1 to 18-4, calibration module group 19-1 to 19-4, amplitude delivery module group 20-1 to 20-4, amplitude and merges module 21, data cache module 22 each input 7 pin and go out with power supply 28 that end+V voltage end is connected, each input 8 pin is held with ground and is connected.
The utility model rate adaptation controller 14 comprises level comparator 23, error code comparator 24, rate selection timer 25, rate controlled module 26, rate selection device 27, and described channel detector 13 output ports 1 are connected with level comparator 23 input ports 1 pin in the rate adaptation controller 14 by data/address bus; Level comparator 23 output ports 2 pin are connected with input port 1 pin of rate controlled module 26; The output port 7,8 of rate adaptation coupler 12 is connected with input port 2,3 pin of rate controlled module 26 respectively, its output port 9 is connected with input port 1 pin of error code comparator 24, and output port 2 pin of error code comparator 24 are connected with input port 4 pin of rate controlled module 26; Output port 1 pin of rate selection timer 25 is connected with input port 5 pin of rate controlled module 26; Input port 1 pin of rate selection device 27 is connected with output port 6 pin of rate controlled module 26, and its output port 2,3,4,5 pin are connected with the input port 6 of rate adaptation multiplexer 2, the input port 4 of rate adaptation Low Medium Frequency modulator 3, the input port 4 of rate adaptation demodulator 11, the input port 6 of rate adaptation coupler 12 respectively; Level comparator 23, error code comparator 24, rate selection timer 25, rate controlled module 26, rate selection device 27 each input 9 pin go out with power supply 16 that end+V voltage end is connected, each input 10 pin links to each other with the ground end.
The utility model is compared background technology and is had following advantage:
1. the utility model has adopted channel detector 13 and rate adaptation controller 14, and caller detects the channel incoming level in real time, and feeds back to calledly with best transfer rate work according to testing result, thereby has higher efficiency of transmission.
2. the utility model adopts rate adaptation controller 14 can carry out network IP transfer of data, first the group of stability road rate transition of scatter communication equipment is arrived the ip network number certificate of many speed, widened the range of application of scattering equipment, make communication quality that tangible improvement has been arranged simultaneously, have also that speed is harmless to be switched, that the traffic can cover is little, full rate scatter communication such as big neutralizes.
3. the utility model circuit block adopts extensive field programmable device to make, and therefore can realize neatly modification to running parameter the structure of equipment being simplified greatly by disposing different programs, and cost is showing and reduces.
Description of drawings
Fig. 1 is an electric functional-block diagram of the present utility model.
Fig. 2 is the electrical schematic diagram of the utility model channel detector 13 embodiment.
Fig. 3 is the electrical schematic diagram of the utility model rate adaptation controller 14 embodiment.
Embodiment:
Referring to figs. 1 through Fig. 3, the utility model is made up of network protocol converter 1, rate adaptation multiplexer 2, rate adaptation Low Medium Frequency modulator 3, D/A converter 4, local oscillator module 5, frequency mixer 6, band pass filter 7, amplifier 8, intermediate frequency amplifier 9, A/D converter 10, rate adaptation demodulator 11, rate adaptation coupler 12, channel detector 13, rate adaptation controller 14, digital phase-locked loop 15, power supply 28.Fig. 1 is an electric principle calcspar of the present utility model, and embodiment presses Fig. 1 connection line.Wherein the effect of network protocol converter 1 is that the network data that external network port A, B import is converted to synchronous code stream, 2 pairs of network data code streams of rate adaptation multiplexer multiple connection framing, its output letter sign indicating number is sent into rate adaptation Low Medium Frequency modulator 3 and is modulated, behind D/A converter 4, convert simulation Low Medium Frequency signal to, the local carrier signal that produces with local oscillator module 5 obtains mixed frequency signal by frequency mixer 6 mixing, obtain required intermediate-freuqncy signal by band pass filter 7 then, after amplifier 8 amplifies, deliver to upconverter through port D.The effect of rate adaptation controller 14 is in the beginning of frame and finishes to change the multiple connection clock cycle of rate adaptation multiplexer 2 and the continuity that clock is switched in assurance, changes the modulated carrier frequencies of rate adaptation Low Medium Frequency modulator 3 simultaneously.Embodiment rate adaptation multiplexer 1, rate adaptation Low Medium Frequency modulator 2, rate adaptation Low Medium Frequency modulator 3 adopt U.S. Alterna company to produce Stratix Series FPGA chip manufacturing.D/A converter 4 adopts the AD9763 chip manufacturing of U.S. AD company.Local oscillator module 5 adopts the si4112 chip manufacturing of U.S. Si Corporation.Frequency mixer 6 adopts the HSB-3 chip manufacturing of the company in sky.Band pass filter 7 adopts the CF70-12 chip manufacturing of Beijing Chang Feng company.Amplifier 8 adopts the ERA-3sm chip manufacturing of U.S. MINI company.
The effect of the utility model channel detector 13 is the level signals that receive A/D converter 10, and its frequency spectrum is weighted merging, sends into rate adaptation controller 14 and carries out level ratio, thereby select the operating rate that meets the current demand signal transmission.It is made up of code element A/D merging module group 16-1 to 16-4, interface and sequential control module group 17-1 to 17-4, FFT processing module group 18-1 to 18-4, calibration module group 19-1 to 19-4, amplitude delivery module group 20-1 to 20-4, amplitude merging module 21, data cache module 22, Fig. 2 is the electrical schematic diagram of the utility model channel detector 13, and embodiment presses Fig. 2 connection line.Wherein code element A/D merges module group 16-1 to 16-4 and is used for preceding half code element and closes the road with corresponding half code element tributary signal afterwards in time domain, forms the continuous tributary signal of four tunnel time domains; Interface and sequential control module group 17-1 to 17-4 are used to receive the Channel Detection signal that merges output port 1,2,3,4 outputs of module group 16-1 to 16-4 from code element A/D, and by data and control bus control FFT processing module group 18-1 to 18-4 these data are carried out spectrum analysis; The effect of FFT processing module group 18-1 to 18-4 is to finish the Channel Detection signal Spectrum Analysis under the control of interface and sequential control module group 17-1 to 17-4, and module group 19-1 to 19-4 is calibrated in real-time the sending into of testing result; The floating data that calibration module group 19-1 to 19-4 is used for that FFT processing module group 18-1 to 18-4 is handled recovers to become input range delivery module group 20-1 to 20-4 after the fixed-point data of representing its true amplitude value; Amplitude delivery module group 20-1 to 20-4 is used for that the fixed-point data that calibration module group 19-1 to 19-4 is produced is carried out the modulo operation input range and merges module 21; Amplitude merges module 21 and is used for mould value weighting merging is calculated in 4 tunnel of amplitude delivery module group 20-1 to 20-4 output, to obtain the mould value of received signal level; Data cache module 22 is used to preserve the mould value of some group of received signal levels, and it is carried out statistical average, compare by 14 pairs of incoming level moulds of rate adaptation controller value, and the iptimum speed value that will wherein select sends in rate adaptation multiplexer 2, rate adaptation Low Medium Frequency modulator 3, rate adaptation demodulator 11, the rate adaptation coupler 12, to realize the adaptive tracing of channel transmission rate.Embodiment code element A/D merging module group 16-1 to 16-4, interface and sequential control module group 17-1 to 17-4, FFT processing module group 18-1 to 18-4, calibration module group 19-1 to 19-4, amplitude delivery module group 20-1 to 20-4, amplitude merge module 21, data cache module 22 all adopts U.S. Alterna company to produce Stratix Series FPGA chip manufacturing.
The effect of the utility model rate adaptation controller 14 is that the operating rate between control appliance caller receiving end and called the making a start is switched.It is made up of level comparator 23, error code comparator 24, rate selection timer 25, rate controlled module 26, rate selection device 27.Fig. 3 is the electrical schematic diagram of the utility model rate adaptation controller 14, and embodiment presses Fig. 3 connection line.Wherein level comparator 23 is used for channel and receives FFT mould value level and benchmark FFT mould value level ratio, matches best transfer rate and sends into rate controlled module 26; Error code comparator 24 is used to add up the number of errors of every frame and some frames, matches best transfer rate and sends into rate controlled module 26; Rate selection timer 25 is used for the 26 rate selection times of rate controlled module regularly, level and error code data that periodic refreshing detects; Rate controlled module 26 is used for the processing of rate controlled flow process, and the running parameter weighted analysis to current level comparator 23 and error code comparator 24 match comprehensively goes out current optimal transmission rate; Rate selection device 27 is used for the transmission rate of rate controlled module 26 is carried out the time slot adjustment, one the tunnel selects speed input adaptive multiplexer 2 and rate adaptation Low Medium Frequency modulator 3 to change corresponding transmission rate, another road selects speed input rate adaptive demodulation device 11 and rate adaptation coupler 12 to change corresponding receiving velocity, guarantees transmitting-receiving speed switching instant alignment work.Embodiment level comparator 23, error code comparator 24, rate selection timer 25, rate controlled module 26, rate selection device 27 all adopt U.S. Alterna company to produce Stratix Series FPGA chip manufacturing.
The utility model intermediate frequency amplifier 9 input ports 1 receive the intermediate-freuqncy signal that exports port D from low-converter to, and the intermediate-freuqncy signal that receives is amplified back input A/D converter 10 carry out data sampling, A/D converter 10 becomes the simulation Low Medium Frequency signal of input port 1 and is divided into 2 the tunnel after the digital signal and is input to channel detector 13 and rate adaptation demodulator 11; The effect of channel detector 13 is the channel level that receives to be made FFT calculate also weighting merging, and its merging FFT value is input to rate adaptation controller 14 and carries out level ratio; The effect of rate adaptation demodulator 11 is to demodulate the letter sign indicating number of variable Rate and clock input rate self adaptation coupler 12 under the selection speed of rate adaptation controller 14; The effect of rate adaptation coupler 12 is to divide information such as picking out network data under the selection speed of rate adaptation controller 14, and the data message that branch is picked out by network protocol converter 1 is converted to network data and is connected to output port E, F.15 effects of the utility model digital phase-locked loop are the high steady clock signals by its input port 1 receive clock input port G input, offer rate adaptation Low Medium Frequency modulator 3,11 1 high steady clocks of rate adaptation demodulator source by its outbound port 2,3 after its phase-locked processing.Embodiment intermediate frequency amplifier 9 adopts commercially available XN402 type integrated amplifier to make.AD9218 type and AD6604 integrated chip that A/D converter 10 adopts U.S. A/D company to produce are made.The digital field programmable device EP1S40 that channel detector 13, rate adaptation controller 14, rate adaptation demodulator 11, rate adaptation coupler 12, digital phase-locked loop 15 all adopt U.S. Alterna company to produce makes.
The utility model power supply 28 provides the direct-current working volts of whole demodulator, and embodiment adopts commercially available general integrated constant voltage dc source module making, and its output+V voltage is 1A for+3.3V, supply current.
The concise and to the point operation principle of the utility model is as follows:
Sending under the working method, network protocol converter 1 is converted to synchronous code stream with the network data of external network port A and B input, at a high speed network data cushioned with reduction of speed handle so that adapt to synchrodata stream rate transmission requirement, the letter sign indicating number of its output is sent into rate adaptation multiplexer 2; The multiple connection speed of rate adaptation multiplexer 2 is by 14 controls of rate adaptation controller, transmission rate is a fixed rate in every frame, frame head behind some frames and postamble switching rate clock also keep clock phase continuous, the letter sign indicating number that forms be input to rate adaptation Low Medium Frequency modulator 3 after the clock phase strictness is alignd, rate adaptation Low Medium Frequency modulator 3 modulated carriers are by the corresponding control of control speed of rate adaptation controller 14, Low Medium Frequency digital signal after its modulation converts analog signal to through D/A converter 4, the local oscillation signal mixing mutually that in frequency mixer 6, produced of this signal then with local oscillator module 5, finish the transformation of Low Medium Frequency analog signal to analog intermediate frequency signal again, this signal is more successively by band pass filter 7 at last, can send into after amplifier 8 carries out bandpass filtering and amplifies it and finish intermediate frequency moving in upconverter to radio spectrum.
Receiving under the working method, the intermediate frequency received signal that low-converter output port D is exported is through intermediate frequency amplifier 9, the digital signal that is converted into Low Medium Frequency behind the A/D converter 10 divides two-way to send into channel detector 13 and rate adaptation demodulator 11 respectively, the channel level of 13 pairs of receptions of channel detector is done FFT calculating and merges to handle, the test level value is sent into rate adaptation controller 14 do the speed analysis, rate adaptation demodulator 11 demodulates letter sign indicating number and the clock rate controlled by rate adaptation controller 14, the letter sign indicating number and the clock of output are sent into rate adaptation coupler 12, rate adaptation coupler 12 divides information such as picking out network data under the rate controlled of rate adaptation controller 14, it detects error code and sends into rate adaptation controller 14 and do the speed analysis, separates out speed through rate adaptation controller 14 total scores and feeds back to rate adaptation multiplexer 2 again, rate adaptation Low Medium Frequency modulator 3, rate adaptation demodulator 11, rate adaptation coupler 12.The data transaction that the rate adaptation coupler was picked out in 12 minutes by network protocol converter 1 becomes the network format data again, by output port E and F output.
The utility model mounting structure is as follows:
The utility model mounting structure is as follows: Fig. 1, Fig. 2, all circuit devcies are installed in the printed board of 3 size length * wide 280 * 140mm of being among Fig. 3, then 3 printed boards being installed in 3 long * wide * height respectively is in the shielding box plug-in unit of 290 * 150 * 30mm, the shielding box plug-in unit is installed in the modulator-demodulator cabinet, shielding box plug-in unit front panel is installed network port A, B, E, the F quad socket and the outbound port C that transmits, two cable sockets of received signal inbound port D, external clock is installed on the rear board goes into to hold G and power supply to go into to hold socket, the assembly cost utility model.
Claims (3)
1, a kind of rate adaptation scatter communication modulator-demodulator, it comprises network protocol converter (1), rate adaptation multiplexer (2), rate adaptation Low Medium Frequency modulator (3), D/A converter (4), local oscillator module (5), frequency mixer (6), band pass filter (7), amplifier (8), intermediate frequency amplifier (9), A/D converter (10), rate adaptation demodulator (11), rate adaptation coupler (12), digital phase-locked loop (15), power supply (28), it is characterized in that: also comprise channel detector (13), rate adaptation controller (14), described network protocol converter (1) input port 7,8 by holding wire respectively with input port A, B connects, its input port 1,2 export clock port 1 with rate adaptation multiplexer (2) respectively, control port 2 links to each other, and its output port 3 links to each other with rate adaptation multiplexer (2) input letter sign indicating number port 3; The input port 1,2 of rate adaptation Low Medium Frequency modulator (3) links to each other with output letter sign indicating number port 4, the clock port 5 of rate adaptation multiplexer (2) respectively, and its output port 3 links to each other with D/A converter (4) input port 1 by data/address bus; Frequency mixer (6) input port 1,2 links to each other with D/A converter (4) output port 2, local oscillator module (5) output port 1 by holding wire respectively, and its output port 3 links to each other with band pass filter (7) input port 1 by holding wire; Amplifier (8) input port 1 links to each other with band pass filter (7) output port 2 by holding wire, and output port 2 links to each other with the outbound port C that transmits by holding wire; Intermediate frequency amplifier (9) input port 1 links to each other with received signal inbound port D by immediate frequency cable, the outbound port C that transmits is connected by wireless transmission/received signal with received signal inbound port D, and intermediate frequency amplifier (9) output port 2 links to each other with A/D converter (10) input port 1; Rate adaptation demodulator (11) input port 1 links to each other with A/D converter (10) output port 2 by data/address bus, and its output port 2,3 links to each other with rate adaptation coupler (12) input letter sign indicating number port one, clock port 2 respectively; The input port 4,5,6 of network protocol converter (1) links to each other with letter sign indicating number port 3, clock port 4, the control port 5 of rate adaptation coupler (12) output respectively, and its output port 9,10 is connected with output port E, F respectively by holding wire; Each input port 7 of rate adaptation coupler (12), output port 6,8,9 link to each other with each output port 6 of rate adaptation controller (14), input port 2,7,8 respectively; Channel detector (13) input port 1 to 8 pin links to each other with A/D converter (10) output port 3 to 10 respectively by data/address bus, and its output port 9 links to each other with rate adaptation controller (14) input port 1 by data/address bus; Rate adaptation controller (14) output port 3,4,5 links to each other with the input port 6 of rate adaptation multiplexer (2), the input port 4 of rate adaptation Low Medium Frequency modulator (3), the input port 4 of rate adaptation demodulator (11) respectively by control bus; Digital phase-locked loop (15) input port 1 links to each other by the steady clock port G of immediate frequency cable and height, and output port 2,3 links to each other with rate adaptation demodulator (11) input port 5, rate adaptation Low Medium Frequency modulator (3) input port 5 respectively; Power supply (28) output+corresponding power end with each parts of V voltage end also connects.
2, rate adaptation scatter communication modulator-demodulator according to claim 1, it is characterized in that: channel detector (13) comprises that code element A/D merges module group (16-1 to 16-4), interface and sequential control module group (17-1 to 17-4), FFT processing module group (18-1 to 18-4), calibration module group (19-1 to 19-4), amplitude delivery module group (20-1 to 20-4), amplitude merges module (21), data cache module (22), described code element A/D merge each input port 1 pin of module group (16-1 to 16-4) respectively with the output port 3 of A/D converter (10), 5,7,9 link to each other, its each input port 2 pin respectively with the output port 4 of A/D converter (10), 6,8,10 link to each other, and its each output port 3 pin are connected in series interface and sequential control module group (17-1 to 17-4) successively by data/address bus respectively, FFT processing module group (18-1 to 18-4), calibration module group (19-1 to 19-4), amplitude delivery module group (20-1 to 20-4) is respectively gone into, outbound port 1, merge each input port 3 of module (21) with amplitude behind 2 pin, 1,2,4 pin connect; Data cache module (22) input port 1 pin is connected with output port 5 pin that amplitude merges module (21) by data/address bus, and its output port 2 pin are connected by the input port 1 of data/address bus with rate adaptation controller (14); Code element A/D merges module group (16-1 to 16-4), interface and sequential control module group (17-1 to 17-4), FFT processing module group (18-1 to 18-4), calibration module group (19-1 to 19-4), amplitude delivery module group (20-1 to 20-4), amplitude and merges module (21), each input 7 pin of data cache module (22) and go out with power supply (28) that end+V voltage end is connected, each input 8 pin is held with ground and is connected.
3, rate adaptation scatter communication modulator-demodulator according to claim 1 and 2, it is characterized in that: rate adaptation controller (14) comprises level comparator (23), error code comparator (24), rate selection timer (25), rate controlled module (26), rate selection device (27), and described channel detector (13) output port 1 is connected with level comparator (23) input port 1 pin in the rate adaptation controller (14) by data/address bus; Level comparator (23) output port 2 pin are connected with input port 1 pin of rate controlled module (26); The output port 7,8 of rate adaptation coupler (12) is connected with input port 2,3 pin of rate controlled module (26) respectively, its output port 9 is connected with input port 1 pin of error code comparator (24), and output port 2 pin of error code comparator (24) are connected with input port 4 pin of rate controlled module (26); Output port 1 pin of rate selection timer (25) is connected with input port 5 pin of rate controlled module (26); Input port 1 pin of rate selection device (27) is connected with output port 6 pin of rate controlled module (26), and its output port 2,3,4,5 pin are connected with the input port 6 of rate adaptation multiplexer (2), the input port 4 of rate adaptation Low Medium Frequency modulator (3), the input port 4 of rate adaptation demodulator (11), the input port 6 of rate adaptation coupler (12) respectively; Level comparator (23), error code comparator (24), rate selection timer (25), rate controlled module (26), each input 9 pin of rate selection device (27) go out with power supply (16) that end+V voltage end is connected, each input 10 pin links to each other with the ground end.
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| CNU2008201056343U CN201252555Y (en) | 2008-08-27 | 2008-08-27 | Speed self-adaptive scatter communication modem |
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| CNU2008201056343U CN201252555Y (en) | 2008-08-27 | 2008-08-27 | Speed self-adaptive scatter communication modem |
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| CN104468435A (en) * | 2014-12-18 | 2015-03-25 | 中国电子科技集团公司第五十四研究所 | Microwave communication equipment of offshore buoy |
| CN104579555A (en) * | 2014-12-02 | 2015-04-29 | 中国电子科技集团公司第五十四研究所 | Scatter communication link control device based on level detection |
| CN105306133A (en) * | 2015-11-13 | 2016-02-03 | 中国电子科技集团公司第五十四研究所 | Channel intelligent cognition based unattended scattering opposite end control device |
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| CN104579555A (en) * | 2014-12-02 | 2015-04-29 | 中国电子科技集团公司第五十四研究所 | Scatter communication link control device based on level detection |
| CN104579555B (en) * | 2014-12-02 | 2017-11-14 | 中国电子科技集团公司第五十四研究所 | Scatter communication link data unit based on level detection |
| CN104468435A (en) * | 2014-12-18 | 2015-03-25 | 中国电子科技集团公司第五十四研究所 | Microwave communication equipment of offshore buoy |
| CN104468435B (en) * | 2014-12-18 | 2017-11-24 | 中国电子科技集团公司第五十四研究所 | A kind of microwave telecommunication devices of marine marker |
| CN105306133A (en) * | 2015-11-13 | 2016-02-03 | 中国电子科技集团公司第五十四研究所 | Channel intelligent cognition based unattended scattering opposite end control device |
| CN105306133B (en) * | 2015-11-13 | 2018-04-20 | 中国电子科技集团公司第五十四研究所 | It is a kind of based on the unattended scattering of channel intelligent cognition to control device |
| CN106027442A (en) * | 2016-05-03 | 2016-10-12 | 中国电子科技集团公司第五十四研究所 | Modem based disperse pilots |
| CN106027442B (en) * | 2016-05-03 | 2019-05-07 | 中国电子科技集团公司第五十四研究所 | Modem based on scattered pilot |
| CN112816972A (en) * | 2020-12-25 | 2021-05-18 | 中国电子科技集团公司第五十四研究所 | Water surface speed measuring radar speed sensor |
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