CN101359993B - High-speed burst modem - Google Patents

High-speed burst modem Download PDF

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Publication number
CN101359993B
CN101359993B CN2008100792221A CN200810079222A CN101359993B CN 101359993 B CN101359993 B CN 101359993B CN 2008100792221 A CN2008100792221 A CN 2008100792221A CN 200810079222 A CN200810079222 A CN 200810079222A CN 101359993 B CN101359993 B CN 101359993B
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module
input
pin
port
signal
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CN2008100792221A
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CN101359993A (en
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张永杰
王东
王晓明
李志勇
倪光华
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中国电子科技集团公司第五十四研究所
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Abstract

The invention discloses a high-speed burst modem, which relates to a modem device with non-(short) preamble burst transmission, strong frequency deviation resistance and high transmission rate in the communication field. The modem comprises parts of a modulator, a demodulator, an auxiliary multiplexer/demultiplexer, an intermediate frequency amplifier, a D/A converter, a low-pass filter, a local oscillating module, an IQ modulator, a band-pass filter, a power supply and the like. The modem adopts the blind estimation technique to estimate the parameters of signals, and has the same performance with the traditional closed-loop estimation, overcomes the disadvantages of long synchronization time and poor frequency deviation resistance, and realizes the high-speed burst modulation and demodulation. The invention also has advantages of high degree of integration, small volume, light weight and good maneuverability, and is particularly suitable for being used in modulation and demodulation devices with large capacity non-(short) preamble burst transmission of wireless data.

Description

High-speed burst modem

Technical field

The present invention relates to a kind of high-speed burst modem in the communications field, be specially adapted to the modulation-demodulation device that big capacity wireless data does not have the transmission of (weak point) preamble burst.

Background technology

Traditional modulator-demodulator adopts closed-loop structure to estimate to finish coherent detection more, the estimated accuracy height, simple in structure be its outstanding advantage, be particularly suitable for continuous communiction.There are two outstanding defectives in this technology when being used for burst communication: lock in time, long (overhead is big) and anti-deviation capability were poor, in big capacity point is communicated by letter to multipoint wireless, the burst communication time between each point is short, so the application that closed-loop structure is estimated is greatly limited.

Summary of the invention

The objective of the invention is to avoid the weak point in the above-mentioned background technology and a kind of nothing (weak point) preamble burst, the high-speed burst modem that anti-deviation capability is strong, transmission rate is high are provided.The present invention not only has and traditional closed loop is estimated identical systematic function, and has overcome the problem of long and anti-deviation capability difference lock in time, also has characteristics such as integrated degree height, volume is little, in light weight, mobility is good.

The object of the present invention is achieved like this:

It comprises again auxiliary/coupler 1, modulator 2, demodulator 3, intermediate frequency amplifier 4, D/A converter groups 5-1,5-2, low pass filter group 6-1,6-2, local oscillator module 7, IQ modulator 8, band pass filter 9, power supply 21; Modulator 2 is made of serial to parallel conversion module 10, differential coding module 11, base band shaping module group 12-1,12-2, DA interface module group 13-1,13-2, control module 14; Demodulator 3 by A/D converter 22, Digital Down Converter Module 15, matching module 16, regularly recover module 17, carrier frequency recovery module 18, carrier phase recovery module 19, differential decoding module 20 and constitute;

Described input port 1 of assisting multiple/coupler 1,2,5,6 respectively with the input information code current A port, symbol clock B port, the output port 3 of demodulator 3,4 link to each other, its output port 3,4 respectively with modulator 2 input ports 1,2, output port 7,8 respectively with output information code current C port, symbol clock D port links to each other, the input port 1 of auxiliary multiplexer-demultiplexer 1,2 receive A port information code stream respectively, B port symbol clock, input port 5,6 information code currents that demodulate of receiving demodulation device 3 respectively, symbol clock, output port 3,4 export the information code current after subdivision connects respectively, symbol clock is to modulator 2, output port 7,8 respectively by C, information code current after the D port output tap, symbol clock; Modulator 2 output ports 3,4 link to each other with each input port 1 of D/A converter groups 5-1,5-2 respectively, each output port 2 of D/A converter groups 5-1,5-2 links to each other with each input port 1 of low pass filter group 6-1,6-2 respectively, signal code stream, the symbol clock of multiple/coupler 1 input that modulator 2 will be assisted is modulated into baseband modulation signal and exports D/A converter groups 5 respectively to and carry out digital to analog conversion, and D/A converter groups 5 is carried out input IQ modulator 8 after the low-pass filtering with the input of the signal after digital to analog conversion low pass filter group 6; The input port 1,2 of IQ modulator 8 is connected with each output port 2 of low pass filter group 6-1,6-2 respectively, input port 3 links to each other with the output port 1 of local oscillator module 7, signal after the low-pass filtering that IQ modulator 8 is exported the local oscillation signal of local oscillator module 7 output and low pass filter group 6 is modulated into intermediate-freuqncy signal, and the signal after the modulation exports band pass filter 9 to; The input port 1 of band pass filter 9 links to each other with the output port 4 of IQ modulator 8, and its output port 2 links to each other with sender input port E by immediate frequency cable, and band pass filter 9 carries out the modulation signal of IQ modulator 8 outputs to export behind the bandpass filtering; The input port 1 of intermediate frequency amplifier 4 links to each other with receiver port F by immediate frequency cable, its output port 2 is connected with the input port 1 of demodulator 3, intermediate frequency amplifier 4 carries out automatic gain control with the intermediate-freuqncy signal of receiver input, and the signal after automatic gain control exports demodulator 3 to; Demodulator 3 carries out demodulation with the automatic gain signals of 4 inputs, draw behind information code current, the symbol clock input auxiliary multiple/coupler 1 answers/export after the tap; Power supply 21 goes out the corresponding power end with each parts of end+V voltage end and connects, and each parts working power is provided.

Serial to parallel conversion module 10 inputs 1 pin in the described modulator 2 links to each other with again auxiliary/coupler 1 output port 3, its output 2,3 pin link to each other with input 1,2 pin of differential coding module 11 respectively, the serial code stream of multiple/coupler 1 output that serial to parallel conversion module 10 will be assisted carries out obtaining the parallel code stream input difference coding module 11 of two-way behind the serial to parallel conversion, and differential coding module 11 carries out the parallel code stream of the two-way of input to export base band shaping module 12 to behind the differential coding; Each input 1 pin of base band shaping module group 12-1,12-2 links to each other with differential coding module 11 each output 3,4 pin respectively, each output 2 pin links to each other with each input 1 pin of DA interface module group 13-1,13-2 respectively, base band shaping module group 12-1, the 12-2 signal after with the differential coding of differential coding module 11 input carries out base band shaping, obtains the square root raised cosine signal.DA interface module group 13-1,13-2 export the signal after base band shaping module group 12-1, the 12-2 conversion to D/A converter 5 respectively; Control module 14 inputs 1 pin links to each other with again auxiliary/coupler 1 output port 4, and its output 2,3 pin link to each other with serial to parallel conversion module 10 inputs 4,5 pin; Input 5 pin of difference block 11, base band shaping module 12, DA interface module 13 inputs 3 pin link to each other with control module 14 outputs 3 pin respectively; The control signal that control module 14 produces is controlled each corresponding module and is carried out signal processing; Serial to parallel conversion module 10, differential coding module 11, base band shaping module group 12-1,12-2, DA interface module group 13-1,13-2, control module 14 each input 9 pin are with power supply 21 outputs+the V voltage end is connected, each input 10 pin is connected with earth terminal, power supply provides the operating voltage of each module, and earth terminal connects common with each module.

Input 1 pin of the A/D converter 22 in the described demodulator 3 links to each other with the output port 2 of intermediate frequency amplifier 4 respectively, Digital Down Converter Module 15 inputs 1 pin links to each other with A/D converter 22 outputs 2 pin, the output 2 of Digital Down Converter Module 15,3 pin are connected in series matching module 16 respectively successively, regularly recover module 17, carrier frequency recovery module 18, carrier phase recovery module 19, differential decoding module 20 each end 1 of coming in and going out, 2 pin link to each other, differential decoding module 20 goes out end 3 pin and is connected with assisting multiple/coupler 1 inbound port 6, regularly recovers module 17 and goes out to hold 5 pin to be connected with again auxiliary/coupler 1 inbound port 5; A/D converter 22 carries out analog to digital conversion with the intermediate frequency amplifying signal of input, and the signal after the analog to digital conversion exports Digital Down Converter Module 15 respectively to and transforms to zero intermediate frequency, and zero intermediate frequency signals exports matching module 16 to and finishes Signal Matching; Regularly recover module 17 recovers each sampled point from the matched signal of input I, Q two-way baseband signal exact value and clock; Carrier frequency recovery module 18 is removed the modulating frequency of I, Q two-way baseband signal; Carrier frequency recovery module 19 is removed the additional phase shift of I, Q two-way baseband signal; Differential decoding module 20 will recover the I after the phase place, two-way digital code stream that the demodulation of Q two-way baseband signal obtains carry out finishing behind the parallel serial conversion differential decoding export to auxiliary multiple/coupler 1; A/D converter 22, Digital Down Converter Module 15, matching module 16, regularly recover module 17, carrier frequency recovery module 18, carrier phase recovery module 19, differential decoding module 20 each input 9 pin and go out with power supply 21 that end+V voltage end is connected, each input 10 pin is connected with earth terminal, power supply 21 provides the operating voltage of each module, and earth terminal connects common with each module.

Demodulator 3 of the present invention adopts blind algorithm for estimating to realize demodulation.

The present invention compares background technology and has following advantage:

1. demodulator 3 of the present invention adopts the blind estimated signal parameter of signal processing technology, adopts the mode of " storage-processing " to finish coherent detection, need not extra leading (expense), has improved the throughput of system.

2. the frequency estimation algorithm that demodulator 3 of the present invention adopts, but the maximum estimation range is 10% of a character rate.Processing clock required for the present invention in addition is low, only is four times of character rate.

3. building block of the present invention adopts extensive field programmable device to make, and therefore can realize neatly modification to running parameter structure being simplified greatly by disposing different programs, and cost significantly reduces.

4. the integrated degree height of the present invention, so volume is little, in light weight, stable and reliable for performance, easy to maintenance, the equipment maneuverability obviously improves.

Description of drawings

Fig. 1 is an electric functional-block diagram of the present invention.

Fig. 2 is the electrical schematic diagram of modulator 2 embodiment of the present invention.

Fig. 3 is the electrical schematic diagram of demodulator 3 embodiment of the present invention.

Embodiment

Referring to figs. 1 through Fig. 3, the present invention is made up of again auxiliary/coupler 1, modulator 2, demodulator 3, intermediate frequency amplifier 4, D/A converter groups 5-1,5-2, low pass filter group 6-1,6-2, local oscillator module 7, IQ modulator 8, band pass filter 9, power supply 21.Fig. 1 is an electric functional-block diagram of the present invention, and embodiment presses Fig. 1 connection line.Wherein the effect of again auxiliary/coupler 1 is by port B incoming symbol clock, by port A input external information code stream, carry out the branch frame and handle, and information code current, the symbol clock that will divide frame to handle offers modulator 2 by output port 3,4; Composite bit stream and symbol clock that while receiving demodulation device 3 demodulates go frame to handle, and isolate business information and are exported by port D by letter sign indicating number port C output, symbol clock.Embodiment assists, and multiple/coupler 1 adopts U.S. altera corp to produce Stratix Series FPGA chip manufacturing.

The input port 1,2 of modulator 2 of the present invention is imported information code current, the clock of output port 3,4 outputs of again auxiliary/coupler 1 respectively, and information code current is modulated into two-way Low Medium Frequency time orthogonal frequency division multiplexing signal, by the output port 3,4 of modulator 2 the two-way baseband signal that forms is delivered to D/A converter groups 5-1,5-2 respectively.It is made up of serial to parallel conversion module 10, differential coding module group 11-1,11-2, base band shaping module group 12-1,12-2, DA interface module group 13-1,13-2, control module 14.Fig. 2 is the electrical schematic diagram of modulator 2 of the present invention, and embodiment presses Fig. 2 connection line.

The effect of described serial to parallel conversion module 10 is that the information code current of/coupler 1 output multiple with assisting carries out serial to parallel conversion, and it is divided into 2 road parallel signal bit streams, delivers to differential coding module 11 respectively.The effect of differential coding module group 11-1,11-2 is that the code stream information of input is carried out exporting to base band shaping module group 12-1,12-2 behind the differential coding.The code stream information of base band shaping module group 12-1,12-2 input difference coding module group 11-1,11-2 output, and it is carried out base band shaping handle formation square root raised cosine signal.Two-way base band shaping signal is by output D/A conversion module group 5 behind DA interface module group 13-1, the 13-2.Control module 14 is handled the clock signal of input, forms the clock control signal of each module of modulator 2.Embodiment serial to parallel conversion module 10, differential coding module 11-1 and 11-2, base band shaping module 12-1 and 12-2, DA interface module 13-1 and 13-2, control module 14 all adopt a U.S. altera corp to produce Stratix Series FPGA chip manufacturing.

This effect of using novel D/A converter groups 5-1,5-2 is respectively that the two-way digital baseband signal by modulator 2 outputs is become analog signal, and sends into low pass filter group 6-1,6-2 respectively.The effect of low pass filter group 6-1,6-2 is respectively two-way to be simulated the Low Medium Frequency signal to carry out exporting IQ modulator 8 to after the low-pass filtering.Local oscillator module 7 produces modulated carrier, and sends into IQ modulator 8.8 effects of IQ modulator are that the two-way baseband signal is modulated to needed intermediate frequency, export band pass filter 9 to.Band pass filter 9 exports sender port E to after the modulated intermediate frequency signal of importing is carried out bandpass filtering.The DAC5675 cake core that embodiment D/A converter groups 5-1,5-2 adopt American TI Company to produce is made.The PLP-50 cake core that low pass filter group 6-1,6-2 adopt Mini company to produce is made.The PMP-1500 cake core that local oscillator module 7 adopts U.S. UMC company to produce is made.The ADL5375 cake core that IQ modulator 8 adopts U.S. AD company to produce is made.The 7MB/C-1200 type band pass filter that electric company 13 was produced during band pass filter 9 adopted is made.

The intermediate-freuqncy signal that intermediate frequency amplifier 4 input ports 1 of the present invention receive from receiver F port is carried out automatic gain control intermediate frequency to it and is amplified, and exports to demodulator 3 by port 2.The integrated amplifier that electric company 13 was produced during embodiment intermediate frequency amplifier 4 adopted is made.

The effect of demodulator 3 of the present invention is that the Low Medium Frequency modulation signal conversion that will receive obtains baseband signal, and regularly recovery of process, carrier frequency recovery and carrier phase recovery are finished the coherent demodulation to signal, recover source code flow information.Demodulator 3 of the present invention adopts the blind estimated signal parameter of signal processing technology, adopts the mode of " storage one is handled " to finish coherent detection, need not extra leading (expense), has improved the throughput of system; The frequency estimation algorithm that demodulator 3 of the present invention adopts, but the maximum estimation range is 10% of a character rate, and processing clock required for the present invention in addition is low, only is four times of character rate.Demodulator 3 by A/D converter 22, Digital Down Converter Module 15, matching module 16, regularly recover module 17, carrier frequency recovery module 18, carrier phase recovery module 19, differential decoding module 20 and form, Fig. 3 is the electrical schematic diagram of demodulator 3 of the present invention, and embodiment presses Fig. 3 connection line.Wherein A/D converter 22 receives the simulation Low Medium Frequency modulation signal of the output port 2 of intermediate frequency amplifier 4, and by sampling it is become digital signal.The Low Medium Frequency modulation signal of A/D converter 22 output inputs to Digital Down Converter Module 15, and Digital Down Converter Module 15 is down-converted to zero intermediate frequency with it, obtains 2 tunnel parallel I, Q baseband signals, exports by port 2,3 pin.The effect of matching module 16 is that the 2 roadbed band signals that Digital Down Converter Module 15 is exported are mated, and makes its output signal-to-noise ratio maximum.Regularly recover module 17 and obtain the timing error amount by the baseband signal after the coupling is carried out nonlinear transformation, the timing that the error amount control figure interpolater of reprocessing is finished input signal recovers.Carrier frequency recovery module 18 finishes receiving I, the Q baseband signal of regularly recovering, and obtains frequency values by the Nonlinear Processing estimation to baseband signal, thereby finishes carrier frequency recovery.Carrier phase recovery module 19 obtains the additive phase value by non-linear estimations, then it is carried out phase compensation, recovers digital information values simultaneously.The effect of differential decoding module 20 is to carry out differential decoding recovering digital information, determines original digital information, finishes parallel serial conversion simultaneously and recovers original transmitted information, exports the input port 6 of again auxiliary/coupler 1 to.Embodiment Digital Down Converter Module 15, matching module 16, regularly recover module 17, carrier frequency recovery module 18, carrier phase recovery module 19, differential decoding module 20 and all adopt a U.S. altera corp to produce Stratix Series FPGA chip manufacturing.The ADS5463 integrated chip that A/D converter 14 adopts American TI Company to produce is made.

Power supply 21 of the present invention provides the direct-current working volts of each parts, and embodiment adopts commercially available general integrated constant voltage dc source piece to make, and its output+V voltage is+3.3V, supply current are 5A.

Demodulator 3 of the present invention adopts blind algorithm for estimating demodulation, regularly recovering blind algorithm for estimating among the embodiment is: the I of input, Q two-way baseband signal are at first carried out the quadratic nonlinearity conversion, do 4 FFT computings then, two paths of data after the computing is accumulated L symbol respectively, asks the phase angle of the two paths of data after the accumulation to be the timing estimation value at last; The blind algorithm for estimating of carrier frequency recovery is: the I of input, Q two-way baseband signal at first postpone to do calculus of differences with current demand signal behind the symbol period, obtain the phase angle of two paths of differential signals then and multiply by 4, obtain sine, cosine two paths of signals according to the phase angle of asking, respectively two paths of signals is accumulated L symbol, asked the phase angle of two-way accumulation results and be the estimating carrier frequencies value divided by 4; The blind algorithm for estimating of carrier phase recovery is: at first obtain input I, Q two-way baseband signal phase angle and multiply by 4 and remove modulation intelligences, obtain sine, cosine two paths of signals according to the phase angle of asking, respectively two paths of signals is accumulated L symbol, asked the phase angle of two-way accumulation results and be the carrier phase estimated value divided by 4.

The concise and to the point operation principle of the present invention is as follows:

During transmission information, again auxiliary/coupler 1 carries out the processing of branch frame with the continuous letter sign indicating number of external business information end A input.The framing information of 2 again auxiliary/coupler 1 outputs of modulator is divided into 2 tunnel parallel code streams and carries out differential coding, carries out the base band shaping processing then and forms the square root raised cosine baseband signal.After process D/A conversion of two-way baseband signal and the low-pass filtering, the two-way analog baseband signal, carries out can sending into sender behind the bandpass filtering to it by the IQ modulators modulate to required intermediate frequency.

During reception information, the Low Medium Frequency signal that intermediate frequency amplifier 4 receives from receiver port F is through sending into demodulator 3 after the automatic gain control.In demodulator 3, after the Low Medium Frequency signal carried out A/D sampling, finish conversion from the Low Medium Frequency to the zero intermediate frequency by Digital Down Convert, Low Medium Frequency signal transformation is 2 tunnel parallel zero intermediate frequency signals, this signal carries out matched filtering subsequently, and the signal after the matched filtering is finished regularly recovery, carrier frequency recovery and carrier phase recovery successively and realized coherent detection.Can recover original transmitted information behind digital information process differential decoding that recovers and the parallel serial conversion.

Mounting structure of the present invention is as follows:

It is in the printed board of 160 * 160mm that all circuit devcies among Fig. 1 to Fig. 3 are installed in a length and width, then printed board being installed in a length is in the cabinet of 320 * 285 * 128mm, the cable socket of letter sign indicating number inbound port A, symbol clock inbound port B, letter sign indicating number outbound port C, symbol clock outbound port D is installed on the front panel of cabinet, install sender in the back on the plate and go out cable socket and the power input socket that inbound port E, receiver go out inbound port F, the assembly cost invention.

Claims (2)

1. high-speed burst modem, it comprises again auxiliary/coupler (1), intermediate frequency amplifier (4), D/A converter groups (5-1,5-2), low pass filter group (6-1,6-2), local oscillator module (7), IQ modulator (8), band pass filter (9), power supply (21), it is characterized in that: also comprise modulator (2), demodulator (3); Modulator (2) is made of serial to parallel conversion module (10), differential coding module (11), base band shaping module group (12-1,12-2), DA interface module group (13-1,13-2), control module (14); Demodulator (3) recovers module (17), carrier frequency recovery module (18), carrier phase recovery module (19), differential decoding module (20) formation by A/D converter (22), Digital Down Converter Module (15), matching module (16), timing;
Described input port 1 of assisting multiple/coupler (1), 2,5,6 respectively with the input information code current A port, symbol clock B port, the output port 2 of demodulator (3), 3 link to each other, described output port 3 of assisting multiple/coupler (1), 4 respectively with modulator (2) input port 1,2 link to each other, described output port 7 of assisting multiple/coupler (1), 8 respectively with output information code current C port, symbol clock D port links to each other, the input port 1 of again auxiliary/coupler (1), 2 receive A port information code stream respectively, B port symbol clock, input port 5, the information code current that 6 difference receiving demodulation devices (3) demodulate, symbol clock, output port 3,4 export the information code current after subdivision connects respectively, symbol clock is to modulator (2), output port 7,8 respectively by C, information code current after the D port output tap, symbol clock; Modulator (2) output port 3,4 respectively with D/A converter groups (5-1, each input port 1 5-2) links to each other, D/A converter groups (5-1, each output port 2 5-2) respectively with low pass filter group (6-1, each input port 1 6-2) links to each other, the signal code stream of multiple/coupler (1) input that modulator (2) will be assisted, symbol clock is modulated into baseband modulation signal and exports D/A converter groups (5-1 respectively to, 5-2) carry out digital to analog conversion, D/A converter groups (5-1,5-2) with the input of the signal after digital to analog conversion low pass filter group (6-1,6-2) carry out importing IQ modulator (8) after the low-pass filtering; The input port 1,2 of IQ modulator (8) is connected with each output port 2 of low pass filter group (6-1,6-2) respectively, input port 3 links to each other with the output port 1 of local oscillator module (7), signal after the low-pass filtering that IQ modulator (8) is exported the local oscillation signal of local oscillator module (7) output and low pass filter group (6-1,6-2) is modulated into intermediate-freuqncy signal, and the signal after the modulation exports band pass filter (9) to; The input port 1 of band pass filter (9) links to each other with the output port 4 of IQ modulator (8), the output port 2 of band pass filter (9) links to each other with sender input port E by immediate frequency cable, and band pass filter (9) carries out the modulation signal of IQ modulator (8) output to export behind the bandpass filtering; The input port 1 of intermediate frequency amplifier (4) links to each other with receiver port F by immediate frequency cable, the output port 2 of intermediate frequency amplifier (4) is connected with the input port 1 of demodulator (3), intermediate frequency amplifier (4) carries out automatic gain control with the intermediate-freuqncy signal of receiver input, and the signal after automatic gain control exports demodulator (3) to; Demodulator (3) carries out demodulation with the automatic gain signal of intermediate frequency amplifier (4) input, draw behind information code current, the symbol clock input auxiliary multiple/coupler (1) answers/export after the tap; Power supply (21) goes out the corresponding power end with each parts of end+V voltage end and connects, and each parts working power is provided;
Serial to parallel conversion module (10) input 1 pin in the described modulator (2) links to each other with again auxiliary/coupler (1) output port 3, output 2,3 pin of described serial to parallel conversion module (10) link to each other with input 1,2 pin of differential coding module (11) respectively, the serial code stream of multiple/coupler (1) output that serial to parallel conversion module (10) will be assisted carries out obtaining the parallel code stream input difference coding module (11) of two-way behind the serial to parallel conversion, and differential coding module (11) carries out the parallel code stream of the two-way of input to export base band shaping module group (12-1,12-2) to behind the differential coding; Each input 1 pin of base band shaping module group (12-1,12-2) links to each other with each output 3,4 pin of differential coding module (11) respectively, each output 2 pin of described base band shaping module group (12-1,12-2) link to each other with each input 1 pin of DA interface module group (13-1,13-2) respectively, the signal of base band shaping module group (12-1,12-2) after with the differential coding of differential coding module (11) input carries out base band shaping, obtains the square root raised cosine signal; DA interface module group (13-1,13-2) exports the signal after base band shaping module group (12-1, the 12-2) conversion to D/A converter groups (5-1,5-2) respectively; Control module (14) input 1 pin links to each other with again auxiliary/coupler (1) output port 4, and described control module (14) output 2,3 pin link to each other with serial to parallel conversion module (10) input 4,5 pin; Input 5 pin of difference block (11), base band shaping module group (12-1,12-2), DA interface module group (13-1,13-2) input 3 pin link to each other with control module (14) output 3 pin respectively; The control signal that control module (14) produces is controlled each corresponding module and is carried out signal processing; Output+the V voltage end is connected, each input 10 pin is connected with earth terminal with power supply (21) for serial to parallel conversion module (10), differential coding module (11), base band shaping module group (12-1,12-2), DA interface module group (13-1,13-2), each input 9 pin of control module (14), power supply provides the operating voltage of each module, and earth terminal connects common with each module;
Input 1 pin of the A/D converter (22) in the described demodulator (3) links to each other with the output port 2 of intermediate frequency amplifier (4); Digital Down Converter Module (15) input 1 pin links to each other with A/D converter (22) output 2 pin, and output 2,3 pin of Digital Down Converter Module (15) link to each other with input 1,2 pin of matching module (16) respectively; Output 3,4 pin of matching module (16) link to each other with input 1,2 pin that regularly recover module (17) respectively; Output 3,4 pin that regularly recover module (17) link to each other with input 1,2 pin of carrier frequency recovery module (18) respectively; Output 3,4 pin of carrier frequency recovery module (18) link to each other with input 1,2 pin of carrier phase recovery module (19) respectively; Output 3,4 pin of carrier phase recovery module (19) link to each other with input 1,2 pin of differential decoding module (20) respectively, differential decoding module (20) goes out end 3 pin and is connected with again auxiliary/coupler (1) input port 6, regularly recovers module (17) output 5 pin and is connected with assisting multiple/coupler (1) input port 5; A/D converter (22) carries out analog to digital conversion with the intermediate frequency amplifying signal of input, and the signal after the analog to digital conversion exports Digital Down Converter Module (15) respectively to and transforms to zero intermediate frequency, and zero intermediate frequency signals exports matching module (16) to and finishes Signal Matching; Regularly recover module (17) recovers each sampled point from the matched signal of input I, Q two-way baseband signal exact value and clock; Carrier frequency recovery module (18) is removed the modulating frequency of I, Q two-way baseband signal; Carrier phase recovery module (19) is removed the additional phase shift of I, Q two-way baseband signal; Differential decoding module (20) will recover the I after the phase place, two-way digital code stream that the demodulation of Q two-way baseband signal obtains carry out finishing behind the parallel serial conversion differential decoding export to auxiliary multiple/coupler (1); A/D converter (22), Digital Down Converter Module (15), matching module (16), regularly recover module (17), carrier frequency recovery module (18), carrier phase recovery module (19), each input 9 pin of differential decoding module (20) and go out with power supply (21) that end+V voltage end is connected, each input 10 pin is connected with earth terminal, power supply (21) provides the operating voltage of each module, and earth terminal connects common with each module.
2. high-speed burst modem according to claim 1 is characterized in that: demodulator (3) adopts clock, carrier frequency, the carrier phase parameter of the blind estimated signal of signal processing technology.
CN2008100792221A 2008-08-20 2008-08-20 High-speed burst modem CN101359993B (en)

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