CN101281889A - Loading plate structure for embedded burying semiconductor chip - Google Patents
Loading plate structure for embedded burying semiconductor chip Download PDFInfo
- Publication number
- CN101281889A CN101281889A CNA2007100922381A CN200710092238A CN101281889A CN 101281889 A CN101281889 A CN 101281889A CN A2007100922381 A CNA2007100922381 A CN A2007100922381A CN 200710092238 A CN200710092238 A CN 200710092238A CN 101281889 A CN101281889 A CN 101281889A
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- Prior art keywords
- opening
- embedded
- semiconductor chip
- semi
- loading plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a loading plate structure for embedding a semiconductor chip. The loading plate structure mainly includes a loading plate with a first surface and a corresponding second surface, the loading plate has at least one opening with a advance angle, the semiconductor chip is easy to arrange in the opening through the advance angle, adhesive material can be filled in the opening uniformly and enough through the advance angle, air bubble generation and stress reduction can be avoided.
Description
Technical field
The present invention relates to a kind of carrying plate structure of embedded with semi-conductor chip, particularly relate to and a kind of semiconductor is embedded into structure in loading plate.
Background technology
Evolution along with semiconductor packaging, semiconductor device (Semiconductor device) has been developed different encapsulation kenels, it mainly is a first device semiconductor chip on a base plate for packaging (package substrate) or lead frame, again semiconductor chip is electrically connected on this base plate for packaging or the lead frame, then encapsulates with colloid; Spherical grid array type (Ball gridarray wherein, BGA) be a kind of advanced person's semiconductor packaging, its characteristics are to adopt a base plate for packaging to settle semiconductor chip, and utilize automatic contraposition (Self-alignment) technology to put the tin ball (Solder ball) that a plurality of one-tenth grid arrays are arranged to plant in this base plate for packaging back side, make that can to hold more I/O links (I/Oconnection) on the semiconductor chip carrier of same units area required with the semiconductor chip that meets height aggregationization (Integration), with by these a little tin balls with whole encapsulation unit weldering knot and be electrically connected to external device (ED).
But, the conventional semiconductor package structure is that semiconductor chip is sticked in substrate top surface, carry out routing and engage (wire bonding) or chip bonding (Flip chip) encapsulation, plant in the back side of substrate again with the tin ball electrically connecting, so, though can reach the purpose of high pin number, but when high frequency more uses or during high speed operation, it will cause impedance to increase because of the lead access path is long, and the usefulness of electrical characteristic can't be promoted, and restriction to some extent.
With Given this, meet down the application of product from generation to generation in order to promote electrical quality effectively, industry is studied employing one after another with in the chip buried circuit board, does directly to electrically connect, shorten electrical conducting path, and reduce the loss of signal, distorted signals and be lifted at the ability of high speed operation.
The preparation flow chart of the circuit board of existing embedded with semi-conductor chip is shown in Figure 1A to Fig. 1 D, one loading plate 10 at first is provided, this loading plate 10 has first surface 10a and reaches and this first surface opposing second surface 10b, and this loading plate 10 is insulation board, metallic plate or the single or multiple lift circuit board of finishing leading portion circuit processing procedure, and forms the opening of at least always wearing 100 (shown in Figure 1A) in this loading plate 10; Then at least one semiconductor chip 11 with a plurality of electronic padses 110 is placed the opening 100 (shown in Figure 1B) of this loading plate 10, must be formed with a tool stickiness and the follow-up removable plate (not shown) that sticks together in the second surface 10b of this loading plate 10; In the opening 100 of this loading plate 10, fill adhesion material 12 and through solidify (Curing) processing procedure with the opening 100 that this semiconductor chip 11 is fixed in this loading plate 10 in (shown in Fig. 1 C); Afterwards in first and second surperficial 10a of this loading plate 10,10b carries out circuit and increases a layer processing procedure, with in first and second surperficial 10a of this loading plate 10,10b forms at least one first dielectric layer 13a and the second dielectric layer 13b respectively in regular turn, and in this first and second dielectric layer 13a, the 13b surface forms first and second line layer 14a and 14b respectively, and this line layer 14a electroplates via 142 to electrically connect this first and second line layer 14a and 14b (shown in Fig. 1 D) by being formed at the electronic pads 110 of conductive blind hole 140 to be electrically connected to this semiconductor chip 11 among this first dielectric layer 13a, being formed with in this loading plate 10 again.
See also Fig. 2, the method for making of the circuit board of another existing embedded with semi-conductor chip is to form at least one opening 100 ' that does not run through in a loading plate 10 again, then has the semiconductor chip 11 of electronic pads 110 then in this opening 100 ' with at least one, and in this opening 100 ', fill adhesion material 12, and be cured processing procedure so that this semiconductor chip 11 is fixed in this opening 100 ', carry out circuit afterwards in the surface of this loading plate 10 and increase layer processing procedure and comprise the circuit layer reinforced structure of at least one dielectric layer 13 and line layer 14, and this line layer 14 is by being formed at the electronic pads 110 of conductive blind hole 140 to be electrically connected to this semiconductor chip 11 in this dielectric layer 13 with formation.
Though the circuit board according to the made embedded with semi-conductor chip of the above manufacture process can shorten electrical conducting path, and the ability that reduces the loss of signal, distorted signals and be lifted at the high frequency operation connects the many disadvantages that places circuit board surface to overcome existing semiconductor chip.But the manufacture process of above-mentioned prior art is to form measure-alike vertical openings up and down in loading plate, is unfavorable for this semiconductor chip is seated in the opening of this loading plate.
Again, the manufacture process of above-mentioned prior art is directly to fill adhesion material in this opening, because the gap of this semiconductor chip and opening is narrow and small straight finedraw, when adhesion material injects this finedraw, this opening 100 material of failing to get adhered is fully filled up, and then make that the adhesion material filling is inhomogeneous in this opening, and easy residual air and the plate bursting phenomenon takes place in subsequent thermal circulation processing procedure, have a strong impact on the successive process reliability.
And, be in loading plate, to form measure-alike vertical opening up and down in the manufacture process of prior art, because thermal coefficient of expansion difference, place opening and carry out follow-up thermal cycle processing procedure when producing thermal expansion effects when this semiconductor chip connects, the edge of this semiconductor chip is subjected to the extruding of edge of opening and impaired easily; Or semiconductor chip active surface periphery and opening periphery stress are excessive, and cause follow-up circuit to increase the used insulating barrier of layer processing procedure and the opening periphery produces lamination, and then influence the quality that circuit board is embedded into chip.
Therefore, how a kind of board structure of circuit of new embedded with semi-conductor chip is proposed, to avoid prior art to be unfavorable for this semiconductor chip is positioned in the vertical openings of circuit board, filler is inhomogeneous, and easy residual bubble, easily because of the stress damage semiconductor chip that thermal expansion produced, or the semiconductor chip periphery increases problems such as layer processing procedure with the excessive and unfavorable follow-up circuit of opening week fiber stress, the real problem that has become the anxious desire solution of dealer.
Summary of the invention
In view of the various shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of carrying plate structure of embedded with semi-conductor chip, does well out of semiconductor chip is connect the opening that places this loading plate.
Another purpose of the present invention is to provide a kind of carrying plate structure of embedded with semi-conductor chip, does well out of the adhesion material filling in the opening of loading plate, to avoid residual air in this opening.
A further object of the present invention is to provide a kind of carrying plate structure of embedded with semi-conductor chip, avoids thermal stress to influence the semiconductor chip that is embedded in loading plate.
A further object of the present invention is to provide a kind of carrying plate structure of embedded with semi-conductor chip, avoids the excessive and unfavorable follow-up circuit of semiconductor chip periphery and opening week fiber stress to increase a layer processing procedure problem.
For reaching above-mentioned and other purpose, the present invention proposes a kind of carrying plate structure of embedded with semi-conductor chip, comprising: a loading plate, and tool first surface and opposing second surface, and this loading plate has the opening of at least one tool lead angle; At least one semiconductor chip connects and places this opening, this semiconductor chip to have active surface and relative non-active surface, and the active surface of this semiconductor chip has a plurality of electronic padses; And adhesion material, be filled in this opening and this gaps between semiconductor chips.
In one embodiment of this invention, the opening of above-mentioned tool lead angle runs through first and second surface of this loading plate, and this lead angle is full lead angle or half lead angle.The carrying plate structure of the embedded with semi-conductor chip of present embodiment comprises that again one first dielectric layer is to be formed at the first surface of this loading plate and the active surface of this semiconductor chip, and second dielectric layer is to be formed at the second surface of this loading plate and the non-active surface of this semiconductor chip.The carrying plate structure of the embedded with semi-conductor chip of present embodiment comprises that again one is formed at this first and second dielectric layer wherein circuit layer reinforced structure of one of group that the surface is formed again, and be formed with a plurality of conductive structures in this circuit layer reinforced structure being electrically connected to this semiconductor chip, and this circuit layer reinforced structure surface is formed with a plurality of electric connection pads.
Than prior art, the carrying plate structure of embedded with semi-conductor chip of the present invention forms the opening with lead angle, thereby can be beneficial to this semiconductor chip is connect the opening that places this loading plate, and can be by this lead angle with even and sufficient being filled in this opening of this adhesion material, avoiding residual air in the opening of this loading plate, and can avoid the thermal stress that the thermal coefficient of expansion difference produces and influence this semiconductor chip.
Description of drawings
Figure 1A to Fig. 1 D is the preparation flow chart of prior art embedded with semi-conductor chip;
Fig. 2 is another structure cutaway view of prior art embedded with semi-conductor chip;
Fig. 3 A to Fig. 3 E is the preparation flow chart of carrying plate structure first embodiment of demonstration embedded with semi-conductor chip of the present invention; And
Fig. 4 is the cutaway view of another embodiment of opening lead angle of the loading plate of demonstration embedded with semi-conductor chip of the present invention.
The component symbol explanation
10,20 loading plates
100,100 ', 21 openings
10a, 20a first surface
10b, 20b second surface
11,22 semiconductor chips
110,220 electronic padses
12,23 adhesion materials
13,260 dielectric layers
13a, 24 first dielectric layers
13b, 25 second dielectric layers
14,14a, 261 line layers
140 conductive blind holes
142,29 electroplate via
14a first line layer
14b second line layer
210,210 ' lead angle
The 22a active surface
The non-active surface of 22b
240,280 perforates
262 conductive structures
263 electric connection pads
28 welding resisting layers
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
Shown in Fig. 3 A to Fig. 3 E, be the method for making flow process of carrying plate structure first embodiment of embedded with semi-conductor chip of the present invention.
As shown in Figure 3A, at first, provide one have first surface 20a and with the loading plate 20 of this first surface opposing second surface 20b, in this loading plate 20, be formed with the opening 21 of at least one tool lead angle 210, and these opening 21 rounded or rectangles, this opening 21 runs through first and second surperficial 20a and 20b of this loading plate 20 again, and this lead angle 210 is full lead angle.In present embodiment, this opening 21 adopts one of them molding mode such as cutting, punching press, laser to form.
In the present embodiment, in this loading plate 20, form the opening 21 of tool lead angle 210, thereby in successive process, can place this opening 21 smoothly this semiconductor chip 22 is connect by this lead angle 210.
Shown in Fig. 3 B, at least semiconductor chip 22 is placed in this opening 21, and be formed with a tool stickiness and the follow-up removable plate (not shown) that sticks together in the second surface 20b of this loading plate 20, this semiconductor chip 22 has an active surface 22a and the non-active surface 22b relative with this active surface, and the active surface 22a of this semiconductor chip 22 has a plurality of electronic padses 220.In present embodiment, this semiconductor chip 22 is placed in this opening 21 with its non-active surface 22b.
Shown in Fig. 3 C, then fill for example adhesion material such as resin material or colloid 23 in the gap between this opening 21 and this semiconductor chip 22, and semiconductor chip 22 is fixed in this opening 21 through solidifying (Curing).In the present embodiment, because this opening 21 has lead angle 210, make the big up and small down funnel-form in gap between this opening 21 and the semiconductor chip 22, thereby make this adhesion material 23 smoothly drainage go in this opening 21, and be filled in really in this opening 21, residual air causes taking place in the subsequent thermal circulation processing procedure plate bursting phenomenon in this opening 21 to avoid.Again in the present embodiment, because this opening 21 has lead angle 210, do not just win and make this adhesion material 23 even fillings, and the edge of this semiconductor chip 22 and this opening 21 tools have bigger spacing with the edge of lead angle 210, and the thermal stress that can avoid the thermal coefficient of expansion difference to produce causes the edge of this semiconductor chip 22 to be subjected to the extruding at opening 21 edges and be impaired; Or avoid semiconductor chip 22 peripheries and the excessive and unfavorable follow-up circuit of opening 21 all fiber stress to increase the problem of layer processing procedure.
Shown in Fig. 3 D, form one first dielectric layer 24 in the first surface 20a of this loading plate 20 and the active surface 22a of this semiconductor chip 22, and form one second dielectric layer 25 in the second surface 20b of this loading plate 20 and the non-active surface 22b of this semiconductor chip 22.Be formed with the electronic pads 220 of a plurality of perforates 240 in this first and second dielectric layer 24,25 respectively to expose this semiconductor chip 22.This first and second dielectric layer 24,25 can for example be epoxy resin (Epoxyresin), policapram (Polyimide), cyanogen fat (Cyanate ester), glass fibre (Glassfiber), bismaleimide/three nitrogen trap (BT, Bismaleimide triazine), polypropylene (PP, polypropylene), ABF or materials such as blending epoxy and glass fibre constitute.
Shown in Fig. 3 E, afterwards, can form a circuit layer reinforced structure 26 in this first dielectric layer 24 and second dielectric layer, 25 surfaces again, and this circuit layer reinforced structure 26 comprises dielectric layer 260, be stacked and placed on the line layer 261 on this dielectric layer, and be formed at conductive structure 262 in this dielectric layer, and this part conductive structure 262 is electrically connected to the electronic pads 220 of this semiconductor chip 22, and be formed with electric connection pad 263 in these circuit layer reinforced structure 26 surfaces, and the circuit layer reinforced structure 26 that is positioned at this first dielectric layer 24 and second dielectric layer, 25 surfaces electrically connects by at least one plating via 29.
In addition, these circuit layer reinforced structure 26 surface replica Cheng Youyi welding resisting layers 28, and have a plurality of perforates 280 in this welding resisting layer, thereby to appear the electric connection pad 263 on this circuit layer reinforced structure surface.
See also Fig. 4, be another embodiment of the present invention, the lead angle 210 ' of above-mentioned opening 21 also can be half lead angle (for opening 21 not being cut sth. askew fully, cut sth. askew and make its opening form part, the kenel that part is vertical), can reach equally to be beneficial to this semiconductor chip 22 is placed this opening 21, and can be convenient to these adhesion material 23 fillings in this opening 21, and can avoid producing bubble, and avoid thermal stress and the edge that influences this semiconductor chip 22 is subjected to the extruding at opening 21 edges and is impaired; Or avoid semiconductor chip 22 peripheries and the excessive and unfavorable follow-up circuit of opening 21 all fiber stress to increase a layer processing procedure problem.
Carrying plate structure by the formed embedded with semi-conductor chip of above-mentioned method for making comprises: a loading plate 20, the opening 21 of at least one tool lead angle 210, at least one semiconductor chip 22 and adhesion material 23.This loading plate 20 has first surface 20a and reaches and this first surface 20a opposing second surface 20b, and is formed with the opening 21 of at least one tool lead angle 210 in this loading plate 20; Wherein, this opening 21 runs through the first surface 20a and the second surface 20b of this loading plate 20, and this lead angle 210 is full lead angle or half lead angle.This semiconductor chip 22 connects and places this opening 21, and this semiconductor chip 22 has an active surface 22a and the non-active surface 22b relative with this active surface, and this active surface 22a has a plurality of electronic padses 220.This adhesion material 23 is filled in the gap between this opening 21 and this semiconductor chip 22, so that this semiconductor chip 22 is fixed in this opening 21.
In present embodiment, the carrying plate structure of this embedded with semi-conductor chip comprises that again one is formed at first dielectric layer 24 of the active surface 22a of the first surface 20a of this loading plate 20 and this semiconductor chip 22, and second dielectric layer 25 that is formed at the non-active surface 22b of the second surface 20b of this loading plate 20 and this semiconductor chip 22; Be formed with circuit layer reinforced structure 26 in this first dielectric layer 24 and second dielectric layer, 25 surfaces again, these circuit layer reinforced structure 26 surface replica Cheng Youyi welding resisting layers 28, and have a plurality of perforates 280 in this welding resisting layer 28, thereby to appear the electric connection pad 263 on this circuit layer reinforced structure surface.
The carrying plate structure of embedded with semi-conductor chip of the present invention, the main opening (as opening 21) that forms at least one tool lead angle in loading plate by the lead angle of this opening, can be beneficial to this semiconductor chip connect and places this opening.
In addition, the present invention, can pass through the lead angle of this opening just like funnel-form, evenly be filled in adhesion material in the opening of loading plate fully thereby can be beneficial to, and avoid filling the inhomogeneous and not enough bubble that comprises of loading because of this adhesion material in this opening, cause taking place in the subsequent thermal circulation processing procedure phenomenon of plate bursting, have a strong impact on the successive process reliability.
Moreover, opening owing to loading plate among the present invention has lead angle, make the edge of this semiconductor chip and the edge of this opening that bigger spacing be arranged, and the thermal stress that can avoid the thermal coefficient of expansion difference to produce cause the edge of this semiconductor chip to be subjected to the extruding of edge of opening and is impaired.
Moreover, because the opening of loading plate has lead angle, avoid making the edge of this semiconductor chip and this opening periphery stress excessive among the present invention, and cause follow-up circuit to increase used insulating barrier of layer processing procedure and opening periphery generation lamination.
The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims of the present invention.
Claims (10)
1. the carrying plate structure of an embedded with semi-conductor chip comprises:
One loading plate, tool first surface and opposing second surface, and this loading plate has the opening of at least one tool lead angle;
At least one semiconductor chip is placed in this opening, and this semiconductor chip has active surface and relative non-active surface, and the active surface of this semiconductor chip has a plurality of electronic padses; And
Adhesion material is filled in this opening and this gaps between semiconductor chips.
2. the carrying plate structure of embedded with semi-conductor chip according to claim 1, wherein, this loading plate is insulation board, metallic plate and the circuit board with circuit wherein.
3. the carrying plate structure of embedded with semi-conductor chip according to claim 1, wherein, this opening runs through first and second surface of this loading plate.
4. the carrying plate structure of embedded with semi-conductor chip according to claim 1, wherein, the lead angle of this opening is wherein one of full lead angle and half lead angle.
5. the carrying plate structure of embedded with semi-conductor chip according to claim 1, comprise one first dielectric layer again, it is formed at the first surface of this loading plate and the active surface of this semiconductor chip, and one second dielectric layer, it is formed at the second surface of this loading plate and the non-active surface of this semiconductor chip.
6. the carrying plate structure of embedded with semi-conductor chip according to claim 5, comprise that again one is formed at this first and second dielectric layer wherein circuit layer reinforced structure of one of group that the surface is formed, and be formed with a plurality of conductive structures in this circuit layer reinforced structure to be electrically connected to the electronic pads of this semiconductor chip, this circuit layer reinforced structure surface is formed with a plurality of electric connection pads again.
7. the carrying plate structure of embedded with semi-conductor chip according to claim 6 comprises again: have a welding resisting layer in this circuit layer reinforced structure surface, and this welding resisting layer surface has a plurality of perforates, thereby to appear the electric connection pad of circuit layer reinforced structure.
8. the carrying plate structure of embedded with semi-conductor chip according to claim 6, wherein, this circuit layer reinforced structure includes dielectric layer, is stacked and placed on the line layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
9. the carrying plate structure of embedded with semi-conductor chip according to claim 1, wherein, this opening is one of them person of circle and rectangular aperture.
10. the carrying plate structure of embedded with semi-conductor chip according to claim 1, wherein, this adhesion material is one of them person of resin material and colloid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100922381A CN101281889A (en) | 2007-04-02 | 2007-04-02 | Loading plate structure for embedded burying semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100922381A CN101281889A (en) | 2007-04-02 | 2007-04-02 | Loading plate structure for embedded burying semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101281889A true CN101281889A (en) | 2008-10-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100922381A Pending CN101281889A (en) | 2007-04-02 | 2007-04-02 | Loading plate structure for embedded burying semiconductor chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN101281889A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376676A (en) * | 2010-08-04 | 2012-03-14 | 欣兴电子股份有限公司 | Package substrate embedded with semiconductor chip |
-
2007
- 2007-04-02 CN CNA2007100922381A patent/CN101281889A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376676A (en) * | 2010-08-04 | 2012-03-14 | 欣兴电子股份有限公司 | Package substrate embedded with semiconductor chip |
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Open date: 20081008 |