CN101266589B - Method for processor accessing external equipment and device thereof - Google Patents
Method for processor accessing external equipment and device thereof Download PDFInfo
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- CN101266589B CN101266589B CN2008101044124A CN200810104412A CN101266589B CN 101266589 B CN101266589 B CN 101266589B CN 2008101044124 A CN2008101044124 A CN 2008101044124A CN 200810104412 A CN200810104412 A CN 200810104412A CN 101266589 B CN101266589 B CN 101266589B
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Abstract
The invention discloses a device for a processor which can access peripheral equipment. The invention adds an address latch, a write data latch, a read data latch, control signal latch, a buffer, a latch control circuit between the processor and the peripheral equipment, which are respectively communicated with the processor and the peripheral equipment, data is latched and released according to a processor command in process read peripheral equipment and process write peripheral equipment, the process is synchronously operated that peripheral equipment waits for read data or write data and does other operation. The invention also discloses a technical scheme for a processor which can access peripheral equipment. The invention is widely applicable in computer technology filed, promotes work efficiency that the processor operates read and write to the peripheral equipment.
Description
Technical field
The invention belongs to field of computer technology, particularly a kind of method of processor accessing external equipment and device.
Background technology
In the Computers and Communication field, often there is the situation of processor accessing external equipment, the model of processor and peripheral hardware is a lot, and external signal pin separately also is not quite similar, and corresponding access mode is also different.Traditional peripheral hardware and processor connected mode, as shown in Figure 1, have basic data bus, address bus, chip selection signal, read-write control signal, answer signal and other signal pins, the characteristics of this connected mode are that the reading and writing data processing speed is slower, when being located at processing procedure in addition when intact, do not send answer signal, processor is in waiting status, after the peripheral hardware inter-process is finished, just send answer signal, the outside processor of notice can be finished operation this time.
For this kind peripheral hardware, the mode of processor access has two kinds usually, mode 1 as shown in Figure 1, the processor that uses in this kind mode has the WAIT signal pins, directly (or through simple logic device) links to each other with the answer signal of peripheral hardware, when the visit peripheral hardware, peripheral hardware sends before the answer signal, and processor is in waiting status, when peripheral hardware sends answer signal, after processor detected by the WAIT signal pins, processor was finished current processing procedure.
Method 2, processor does not have the WAIT signal, but use the I/O pin of processor and the answer signal pin of peripheral hardware to link to each other, when the processor access peripheral hardware, processor detects the peripheral hardware answer signal by the I/O pin, simultaneously processor is in wait, and after detecting peripheral hardware and replying, processor is finished operation this time.
The shortcoming of said method is, the leg signal of processor is had requirement, must have WAIT signal or I/O pin, and simultaneously, the efficient of waste processor is bide one's time waiting, and processor can not be done other work.
Summary of the invention
The objective of the invention is to solve the problems of the technologies described above, a kind of device of processor accessing external equipment be provided, comprise processor, peripheral hardware, it is characterized in that:
Latch control circuit, address latch, write data latch device, read data latch, control signal latch and impact damper between processor and peripheral hardware, have been increased;
Described each several part connected mode is as follows: processor links to each other with address latch, write data latch device, read data latch, control signal latch, impact damper and latch control circuit; The latch control circuit links to each other with impact damper with processor, address latch, write data latch device, read data latch, control signal latch; Address latch links to each other with peripheral hardware with processor, latch control circuit, write data latch device; The write data latch device links to each other with peripheral hardware with processor, latch control circuit; Read data latch links to each other with peripheral hardware with processor, latch control circuit; The control signal latch links to each other with peripheral hardware with processor, latch control circuit; Impact damper links to each other with peripheral hardware with processor, latch control circuit; Peripheral hardware links to each other with impact damper with address latch, write data latch device, read data latch, control signal latch.
The concrete model of described address latch, write data latch device, read data latch and control signal latch is 74HC573.
The concrete model of described impact damper is 74HC244.
Described latch control circuit is a programmable logic chip, and concrete model is EPM7128SQC100.
The present invention also provides a kind of method of processor accessing external equipment, it is characterized in that comprising the following steps:
---between processor and peripheral hardware, increased latch control circuit, address latch, write data latch device, read data latch, control signal latch and impact damper;
Processor links to each other with address latch, write data latch device, read data latch, control signal latch, impact damper and latch control circuit; The latch control circuit links to each other with impact damper with processor, address latch, write data latch device, read data latch, control signal latch; Address latch links to each other with peripheral hardware with processor, latch control circuit, write data latch device; The write data latch device links to each other with peripheral hardware with processor, latch control circuit; Read data latch links to each other with peripheral hardware with processor, latch control circuit; The control signal latch links to each other with peripheral hardware with processor, latch control circuit; Impact damper links to each other with peripheral hardware with processor, latch control circuit; Peripheral hardware links to each other with impact damper with address latch, write data latch device, read data latch, control signal latch;
The processor of---is wherein carried out following steps:
Processor detects certain programmed instruction and need conduct interviews and judge that reading peripheral hardware instruction still is to write the peripheral hardware instruction peripheral hardware;
Then carry out the following step if write peripheral hardware:
Processor sends the address signal of peripheral hardware to address latch, send the data that will write to peripheral hardware to the write data latch device, send the control signal that the instruction peripheral hardware begins to prepare to accept data to the control signal latch, and get up by latch control circuit instruction address latch, write data latch device and control signal latch signal latch with input end;
Processor is by the answer signal of impact damper scanning peripheral hardware, up to scan answer signal effectively till;
Processor sends the control signal that the instruction peripheral hardware receives data according to the answer signal that receives to the control signal latch, writes the peripheral hardware operation and finishes;
Then carry out the following step if read peripheral hardware:
Processor sends the address signal of peripheral hardware to address latch, send the control signal that the instruction peripheral hardware begins to be ready for sending data to the control signal latch, and get up by latch control circuit instruction address latch and control signal latch signal latch with input end;
Processor is by the answer signal of impact damper scanning peripheral hardware, up to scan answer signal effectively till;
Processor is according to the answer signal that receives, and instruction latch control circuit becomes pass-through state with read data latch, and reading of data is read the peripheral hardware operation and finished.
Beneficial effect of the present invention:
The invention provides a kind of mode of processor accessing external equipment, reduced restriction to the processor pin, be that processor not necessarily must have WAIT pin or I/O pin, but by signals such as data bus and address buss, just the peripheral hardware that can finish having answer signal conducts interviews, when the reaction time of peripheral hardware was slow, processor can also be done other operations (comprising operations such as other peripheral hardwares of visit) during this peripheral hardware of visit, raise the efficiency.
Description of drawings
Accompanying drawing 1 is a conventional processors visit peripheral hardware connection diagram;
Accompanying drawing 2 is processor access peripheral hardware connection diagrams of the present invention;
Accompanying drawing 3 is processor schematic flow sheets of processor access peripheral hardware of the present invention.
Embodiment
The invention will be further described below in conjunction with accompanying drawing:
As Fig. 2 is processor access peripheral hardware connection diagram of the present invention, latch control circuit (programmable logic chip U2 is hereinafter to be referred as logic chip), address latch U3, write data latch device U4, read data latch U5, control signal latch U6 and impact damper U8 have been increased between processor U1 of the present invention (CPU) and the peripheral hardware U7 (IC).
Logic chip U2 selects EPM7128SQC100 for use; Address latch U3, write data latch device U4, read data latch U5 and control signal latch U6 select 74HC573 for use; Impact damper U8 selects 74HC244 for use.
The data bus D0-D7 of processor U1 is connected on the data bus of logic chip U2 among Fig. 2, is connected on the output pin of the input of latch U4 and U5.The D0 pin is connected to the input pin D0 (as DS indicator signal) of latch U6 and is connected to the output pin 1Y1 (being used to introduce the answer signal of peripheral hardware) of impact damper U8 in the processor U1 data bus.Processor U1 address bus A0-A15 is connected on the address bus A0-A15 of logic chip U2, wherein the A0-A5 pin of processor address bus is also connected to the input pin D0-D5 of latch U3, select a processor address bus pin that exceeds the peripheral hardware address size to be connected to the input pin D6 of latch U3 (the peripheral hardware address is 6 in this example, has therefore selected the A6 pin to be connected to the input pin D6 of U3) in addition in processor address bus A6-A15.Processor U1 /WR write signal pin and/RD read signal pin is connected to the input pin of logic chip U2.
The LE_A_R_W_CS pin of logic chip is connected to the LE control pin of latch U3, U4.The CS_A chip selection signal pin of logic chip U2 is connected on the input pin D7 of latch U3.The OE_DATA pin of logic chip is connected on the control pin OE of latch U5.The LE_DS pin of logic chip is connected on the control pin LE of latch U6.The OE_DTA pin of logic chip is connected on the 1G and 2G control pin of impact damper U8.
The output pin Q0-Q5 of latch U3 is connected to the address bus A0-A5 of peripheral hardware IC, the output pin Q6 of latch U3 is connected to the R/W pin of peripheral hardware IC and the control pin OE of latch U4, and the output pin Q7 of latch U3 is connected to the chip selection signal of peripheral hardware IC/CS pin.The control pin OE of latch U3 ground connection all the time is " 0 ".
The output pin D0-D7 of latch U4 is connected on the data bus D0-D7 of peripheral hardware IC.
The output pin D0-D7 of latch U5 is connected on the data bus D0-D7 of processor U1.
The output pin Q0 of latch U6 is connected to the DS signal pins of peripheral hardware IC, and the control pin OE of latch U6 ground connection all the time is " 0 ".
The DTA answer signal pin of peripheral hardware IC is connected to the DTA pin of logic chip U2, is connected to the LE control pin of latch U5, is connected to the input pin 1A1 of impact damper U8.
Logic chip U2 of the present invention is a programmable logic chip, realizes following logic function by design programming:
Input signal pin: A0-A15 ,/WR and/RD;
Output signal pin: LE_A_R_W_CS, OE_DTA, OE_DATA, LE_DS and CS_A;
Standby pin: D0-D7.
The logical relation such as the following table of correspondence between the input and output pin:
For an embodiment this method is described below in conjunction with Fig. 3.
As Fig. 3 is the processor schematic flow sheet of processor access peripheral hardware of the present invention.
Step 301: processor detects certain programmed instruction and need conduct interviews and judge that reading peripheral hardware instruction still is to write the peripheral hardware instruction peripheral hardware;
Then carry out the following step if write peripheral hardware:
Step 302: processor sends the address signal of peripheral hardware to address latch, send the data that will write to peripheral hardware to the write data latch device, send the control signal that the instruction peripheral hardware begins to prepare to accept data to the control signal latch, and get up by latch control circuit instruction address latch, write data latch device and control signal latch signal latch with input end.
---processor U1 sends particular address signal ADD_DS on address wire, processor sends complete " 0 " signal to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again, the OE pin of latch U6 ground connection all the time is " 0 ", and " 0 " of the input of D0 pin is input to the D0 input pin of U6 in the processor data line.
A latch signal high impulse (become " 1 " by " 0 " and become " 0 " again) is sent in address signal ADD_DS that logic chip U2 sends according to processor and the low pulse of pin/WR on the LE_DS pin.
Latch U6 gets off the D0 signal latch according to the high impulse latch signal that receives on the LE pin, is sent to the DS pin of peripheral hardware IC by output pin Q0, even the DS pin of peripheral hardware IC remains " 0 ".
---processor is gone up the address signal ADD_WR_IC that sends peripheral hardware to address wire A0-A5, and A6 is set to " 0 ", and processor sends " DATA_WR_IC " signal to data line, and promptly the data that write to peripheral hardware send low pulse at write signal pin/WR.
Logic chip is according to the low pulse of address signal ADD_WR_IC and pin/WR, chip selection signal pin CS_A is become effective status (becoming " 0 " by " 1 ") by disarmed state, on the LE_A_R_W_CS pin, send a latch signal high impulse (become " 1 " by " 0 " and become " 0 " again).
Latch U3 is according to the high impulse latch signal that receives on the LE pin, latch the address signal ADD_WR_IC (A0-A5) of input, A6 is " 0 " in addition, make output pin Q6 be " 0 ", and then make the R/W pin of IC and the OE control pin of U4 remain " 0 ", pin CS_A simultaneously, make IC /CS remains " 0 ").
Latch U4 latchs the data-signal " DATA_WR_IC " of input according to the high impulse latch signal that receives on the LE pin, remains on the data bus of IC.This moment, the R/W pin of IC was " 0 ", and IC is in and is write state.
---processor U1 sends particular address signal ADD_DS on address wire, processor sends complete " 1 " signal to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again, the OE pin of latch U6 ground connection all the time is " 0 ", and " 1 " of the input of D0 pin is input to the D0 input pin of U6 in the processor data line.
A latch signal high impulse (become " 1 " by " 0 " and become " 0 " again) is sent in address signal ADD_DS that logic chip U2 sends according to processor and the low pulse of pin/WR on the LE_DS pin.
Latch U6 gets off the D0 signal latch according to the high impulse latch signal that receives on the LE pin, is sent to the DS pin of peripheral hardware IC by output pin Q0, even the DS pin of peripheral hardware IC remains " 1 ".
Peripheral hardware prepares to receive data according to chip selection signal CS_IC (logic chip CS_A-〉latch U3 CS_IC), address signal A0H～A6H, signal R/W (" 0 "), DS (become " 1 " by " 0 ", and keep stable).Because the reaction velocity of peripheral hardware is slower, when also being not ready for, data do not produce answer signal.
Peripheral data is ready to, and produces answer signal DTA (becoming " 0 " by " 1 ") and is input to impact damper U8, and remain unchanged.
Step 303: processor is by the answer signal of impact damper scanning peripheral hardware, up to scan answer signal effectively till.
---processor scans U8, and processor U1 sends particular address signal ADD_DTA on address wire, and processor read signal pin/RD becomes effective status (becoming " 0 " by " 1 ") by disarmed state.Processor is read signal from the data line D0 pin always, up to having read " 0 ", promptly scans DTA and becomes " 0 ", thinks that then IC has been ready to receive data.
The address signal ADD_DTA that logic chip U2 sends according to processor sends a low level pulse (becoming " 0 " by " 1 ") on the OE_DTA pin.U8 becomes straight-through, the DTA signal is delivered on the data line D0 pin of U1.
---processor U1 sends particular address signal ADD_DS on address wire, processor sends complete " 0 " signal to data line, wherein the D0 pin becomes " 0 " by original " 1 ", produce a negative edge, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again.
A latch signal high impulse (become " 1 " by " 0 " and become " 0 " again) is sent in address signal ADD_DS that logic chip U2 sends according to processor and the low pulse of pin/WR on the LE_DS pin.
Latch U6 gets off the D0 signal latch according to the high impulse latch signal that receives on the LE pin, is sent to the DS pin of peripheral hardware IC, and promptly the DS pin becomes " 0 " by " 1 ", produces a negative edge.
Peripheral hardware IC locks the data DATA_WR_IC on the data bus according to the negative edge of DS, and with the level of DTA pin by " 0 " change " 1 ".
Step 304: processor sends the control signal that the instruction peripheral hardware receives data according to the answer signal that receives to the control signal latch, writes the peripheral hardware operation and finishes.
Processor sends specific address signal ADD_CLR on address wire, processor sends " DATA_CLR " signal (these data use less than) to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again.The processor write operation is finished.
Logic chip according to address signal ADD_CLR and/the low pulse of WR, with chip selection signal pin CS_A by " 0 " become " 1 "), on the LE_A_R_W_CS pin, send a latch signal high impulse (become " 1 " by " 0 " and become " 0 " again).
Latch U3 latchs the address signal A0～A6 of input according to the high impulse latch signal that receives on the LE pin, pins CS_A simultaneously, so, IC /the CS pin is " 1 ", IC is in not selected state.Write operation finishes.
Then carry out the following step if read peripheral hardware:
Step 305: processor sends the address signal of peripheral hardware to address latch, send the control signal that the instruction peripheral hardware begins to be ready for sending data to the control signal latch, and get up by latch control circuit instruction address latch and control signal latch signal latch with input end.
---processor U1 sends particular address signal ADD_DS on address wire, processor sends complete " 0 " signal to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again, the OE pin of latch U6 ground connection all the time is " 0 ", and " 0 " of the input of D0 pin is input to the D0 input pin of U6 in the processor data line.
A latch signal high impulse (become " 1 " by " 0 " and become " 0 " again) is sent in address signal ADD_DS that logic chip U2 sends according to processor and the low pulse of pin/WR on the LE_DS pin.
Latch U6 gets off the D0 signal latch according to the high impulse latch signal that receives on the LE pin, is sent to the DS pin of peripheral hardware IC by output pin Q0, even the DS pin of peripheral hardware IC remains " 0 ".
Step 309: processor sends the address signal ADD_RD_IC of peripheral hardware on address wire, is connected with address latch U3 but the pin that do not send the peripheral hardware address is set to " 1 ", sends low pulse at write signal pin/WR.
Logic chip is according to the low pulse of address signal ADD_WR_IC and pin/WR, chip selection signal pin CS_A is become effective status (becoming " 0 " by " 1 ") by disarmed state, on the LE_A_R_W_CS pin, send a latch signal high impulse (become " 1 " by " 0 " and become " 0 " again).
Latch U3 is according to the high impulse latch signal that receives on the LE pin, latchs the address signal ADD_WR_IC (A0 wherein～A6) of input.
Latch U4 latchs the data-signal " 1 " of input according to the high impulse latch signal that receives on the LE pin, and this moment, the R/W pin of IC was " 1 ", and IC is in read states.The OE pin of U4 is " 1 " (A6 of from processor), does not open.
----processor U1 sends particular address signal ADD_DS on address wire, processor sends complete " 1 " signal to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again, the OE pin of latch U6 ground connection all the time is " 0 ", and " 1 " of the input of D0 pin is input to the D0 input pin of U6 in the processor data line.
A latch signal high impulse (become " 1 " by " 0 " and become " 0 " again) is sent in address signal ADD_DS that logic chip U2 sends according to processor and the low pulse of pin/WR on the LE_DS pin.
Latch U6 gets off the D0 signal latch according to the high impulse latch signal that receives on the LE pin, is sent to the DS pin of peripheral hardware IC by output pin Q0, even the DS pin of peripheral hardware IC remains " 1 ".
Peripheral hardware (becomes " 1 " by " 0 " according to chip selection signal CS_IC (logic chip CS_A-〉latch U3 CS_IC), address signal A0H～A6H, signal R/W (" 1 "), DS, and keep stable) the preparation data, be ready to afterwards produce answer signal DTA (becoming " 0 ") and remain unchanged, do not produce answer signal when unripe by " 1 ".
Peripheral hardware prepares to receive data according to chip selection signal CS_IC (logic chip CS_A-〉latch U3 CS_IC), address signal A0H～A6H, signal R/W (" 0 "), DS (" 1 ").Because the reaction velocity of peripheral hardware is slower, when also being not ready for, data do not produce answer signal.
Peripheral hardware is ready to data " DATA_RD ", is put into data line D0H～D7H, produces answer signal DTA (becoming " 0 " by " 1 ") and is input to impact damper U8, and remain unchanged.Answer signal DTA (becoming " 0 " by " 1 ") is connected to the LE pin of latch U5, and U5 latchs data " DATA_RD ".
Step 306: processor is by the answer signal of impact damper scanning peripheral hardware, up to scan answer signal effectively till.
Processor scans U8, and processor U1 sends particular address signal ADD_DTA on address wire, and processor read signal pin/RD becomes effective status (becoming " 0 " by " 1 ") by disarmed state.Processor is read signal from the data line D0 pin always, up to having read " 0 ", promptly scans DTA and becomes " 0 ", thinks that then IC has been ready to send data.
The address signal ADD_DTA that logic chip U2 sends according to processor sends a low level pulse (becoming " 0 " by " 1 ") on the OE_DTA pin.U8 becomes straight-through, the DTA signal is delivered on the data line D0 pin of U1.
Step 307: processor is according to the answer signal that receives, and instruction latch control circuit becomes pass-through state with read data latch, and reading of data is read the peripheral hardware operation and finished.
---processor sends particular address signal ADD_RD_DATA according to the answer signal that receives on address wire, read signal pin/RD becomes effective status by disarmed state.
The address signal ADD_RD_DATA that logic chip U2 sends according to processor, on the OE_DATA pin, send a low level (becoming " 0 ") by " 1 ", be sent to the OE pin of read data latch U5, U5 becomes pass-through state, and the data " DATA_RD " that the IC that latchs before sends are delivered on data line D0～D7 pin of U1.
---processor U1 sends particular address signal ADD_DS on address wire, processor sends complete " 0 " signal to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again, the OE pin of latch U6 ground connection all the time is " 0 ", and " 0 " of the input of D0 pin is input to the D0 input pin of U6 in the processor data line.
A latch signal high impulse (become " 1 " by " 0 " and become " 0 " again) is sent in address signal ADD_DS that logic chip U2 sends according to processor and the low pulse of pin/WR on the LE_DS pin.
Latch U6 gets off the D0 signal latch according to the high impulse latch signal that receives on the LE pin, and the DS pin by output pin Q0 is sent to peripheral hardware IC even the DS pin of peripheral hardware IC becomes " 0 " by " 1 ", produces a negative edge.IC is according to the negative edge of DS, with the level of DTA pin by " 0 " change " 1 ".
---processor sends specific address signal ADD_CLR on address wire, processor sends " DATA_CLR " signal (these data use less than) to data line, write signal pin/WR becomes effective status (becoming " 0 " by " 1 ") by disarmed state, after keeping a period of time, become invalid (" 1 ") again.The processor read operation is finished.
Logic chip is cancelled the chip selection signal to peripheral hardware according to address signal ADD_CLR and write signal action that processor sends.
Logic chip according to address signal ADD_CLR and/the low pulse of WR, with chip selection signal pin CS_A by " 0 " become " 1 "), on the LE_A_R_W_CS pin, send a latch signal high impulse (become " 1 " by " 0 " and become " 0 " again).
Latch U3 latchs the address signal A0～A6 of input according to the high impulse latch signal that receives on the LE pin, pins CS_A simultaneously, so, IC /the CS pin is " 1 ", IC is in not selected state.Read operation finishes.
Above-described embodiment is a more preferably embodiment of the present invention, and common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.
Claims (5)
1. device that is used for processor accessing external equipment, comprise processor, peripheral hardware, between processor and peripheral hardware, increase address latch, write data latch device and read data latch, it is characterized in that between processor and peripheral hardware, also having increased latch control circuit, control signal latch and impact damper;
Described each several part connected mode is as follows: processor links to each other with address latch, write data latch device, read data latch, control signal latch, impact damper and latch control circuit; The latch control circuit links to each other with impact damper with processor, address latch, write data latch device, read data latch, control signal latch; Address latch links to each other with peripheral hardware with processor, latch control circuit, write data latch device; The control signal latch links to each other with peripheral hardware with processor, latch control circuit; Impact damper links to each other with peripheral hardware with processor, latch control circuit; Peripheral hardware links to each other with impact damper with address latch, write data latch device, read data latch, control signal latch.
2. the device that is used for processor accessing external equipment according to claim 1 is characterized in that the concrete model of described control signal latch is 74HC573.
3. the device that is used for processor accessing external equipment according to claim 1 is characterized in that the concrete model of described impact damper is 74HC244.
4. the device that is used for processor accessing external equipment according to claim 1 is characterized in that described latch control circuit is a programmable logic chip, and concrete model is EPM7128SQC100.
5. the method for a processor accessing external equipment is characterized in that comprising the following steps:
---between processor and peripheral hardware, increased latch control circuit, address latch, write data latch device, read data latch, control signal latch and impact damper;
Processor links to each other with address latch, write data latch device, read data latch, control signal latch, impact damper and latch control circuit; The latch control circuit links to each other with impact damper with processor, address latch, write data latch device, read data latch, control signal latch; Address latch links to each other with peripheral hardware with processor, latch control circuit, write data latch device; The write data latch device links to each other with peripheral hardware with processor, latch control circuit; Read data latch links to each other with peripheral hardware with processor, latch control circuit; The control signal latch links to each other with peripheral hardware with processor, latch control circuit; Impact damper links to each other with peripheral hardware with processor, latch control circuit; Peripheral hardware links to each other with impact damper with address latch, write data latch device, read data latch, control signal latch;
The processor of---is wherein carried out following steps:
Processor detects certain programmed instruction and need conduct interviews and judge that reading peripheral hardware instruction still is to write the peripheral hardware instruction peripheral hardware;
Then carry out the following step if write peripheral hardware:
Processor sends the address signal of peripheral hardware to address latch, send the data that will write to peripheral hardware to the write data latch device, send the control signal that the instruction peripheral hardware begins to prepare to accept data to the control signal latch, and get up by latch control circuit instruction address latch, write data latch device and control signal latch signal latch with input end;
Processor is by the answer signal of impact damper scanning peripheral hardware, up to scan answer signal effectively till;
Processor sends the control signal that the instruction peripheral hardware receives data according to the answer signal that receives to the control signal latch, writes the peripheral hardware operation and finishes;
Then carry out the following step if read peripheral hardware:
Processor sends the address signal of peripheral hardware to address latch, send the control signal that the instruction peripheral hardware begins to be ready for sending data to the control signal latch, and get up by latch control circuit instruction address latch and control signal latch signal latch with input end;
Processor is by the answer signal of impact damper scanning peripheral hardware, up to scan answer signal effectively till;
Processor is according to the answer signal that receives, and instruction latch control circuit becomes pass-through state with read data latch, and reading of data is read the peripheral hardware operation and finished.
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| CN101937537A (en) * | 2010-10-25 | 2011-01-05 | 上海申瑞电力科技股份有限公司 | Parallel access method of power grid historical data |
| CN108153703A (en) * | 2016-12-05 | 2018-06-12 | 深圳市中兴微电子技术有限公司 | A kind of peripheral access method and apparatus |
| CN106933763A (en) * | 2017-02-22 | 2017-07-07 | 中国银行股份有限公司 | Data processing method and device |
| CN107832239A (en) * | 2017-09-13 | 2018-03-23 | 东莞市爱协生智能科技有限公司 | A kind of transfer control method and device based on ahb bus |
| CN114860630B (en) * | 2022-04-27 | 2023-04-18 | 深圳市洛仑兹技术有限公司 | Digital processing circuit and signal processing method |
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| CN101266589A (en) | 2008-09-17 |
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