CN1161693C - One-step debugging card unit with PCJ interface and its operation process - Google Patents
One-step debugging card unit with PCJ interface and its operation process Download PDFInfo
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- CN1161693C CN1161693C CNB001348582A CN00134858A CN1161693C CN 1161693 C CN1161693 C CN 1161693C CN B001348582 A CNB001348582 A CN B001348582A CN 00134858 A CN00134858 A CN 00134858A CN 1161693 C CN1161693 C CN 1161693C
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Abstract
The present invention relates to a single step debugging card with the application of PCI buses. Frame signals on a PCI main are maintained at a low level, the address and the instruction of a PCI bus cycle are latched and displayed, ROM control signals and IRDY# and TRDY# preparation signals on the PCI bus are simultaneously maintained at a low level, and the data and the bit set enabling property of the PCI bus cycle are latched and displayed. When a target device is detected, a device selecting signal is sent out; when the device selecting signal is maintained at a low level, and the IRDY# and the TRDY# preparation signals are simultaneously maintained at a low level, the PCI bus cycle is intercepted; before the PCI bus cycle ends, a PCI host machine also offers the retrial function. Consequently, the function of single step interruption debugging is reached.
Description
Technical field
The present invention relates to a kind of one-step debugging card, particularly a kind of application peripheral component connects (Peripheral Component Interconnect, PCI) one-step debugging card at interface alternately.
Background technology
Fig. 1 shows the structure calcspar of present the computer system of widely using.CPU 10 is connected with NB (North bridge is a wafer set) 30 by cpu bus 20; And NB 30 also links to each other with AGP VGA card 60 by AGP bus 50 except joining with storer 40 (can be storeies such as SDRAM, EDORAM).In addition, 30 of NB join with SB (South bridge also is a wafer set) 80 via pci bus 70, in order to Data transmission and signal; And SB80 except with hard disk (HD) 90, CD player (CD ROM) 100, USB (universal serial bus) (UniversalSerial Bus, USB) 110, input media (such as mouse, keyboard etc.) 120 joins, outside access or input data, also respectively by XD bus 130 and isa bus 140, join with Basic Input or Output System (BIOS) (BIOS) 150 and acoustic apparatus (Audio, for example adlib) 160.
Traditional one-step interrupt debugging card is applied in industrial standard architectures form bus (IndustryStandard Architecture BUS, ISA BUS) on, force by the IOCHRDY signal that is used for finishing the isa bus cycle and to maintain low level, reaching the purpose that prolongs these bus cycles, and make relevant address and data line bus state be able to be inspected.
And on pci bus, CPU needs by the PCI/ISA bridge read cycle to be transferred to isa bus by pci bus for reading of legacy system BIOS, treat that the BIOS data by after being positioned at ROM on the isa bus and reading, send data back to pci bus by ISA BUS by the PCI/ISA bridge again.Because the BIOS data read cycle must be responded by the PCI/ISA bridge on pci bus, that is relevant pci cycle control signal such as DEVSEL#, TRDY# etc. produce by the PCI/ISA bridge, also therefore can not just reach the purpose of suspending the bus cycles merely by maintaining high level in order to signal such as the TRDY# that finishes pci cycle.
And the present Debug Card that is applied on the market on the PCI BUS, or still need to interrupt Debug Card by isa bus, maintain low level by forcing in order to the IOCHRDY signal that finishes the isa bus cycle, and reach the purpose that prolongs these bus cycles, or just part BIOS data and address bolt-lock are read to memory buffer more one by one in the start initial stage, and tool does not really suspend the bus cycles, and and then makes the function inspect immediately.
Summary of the invention
With regard to a normal pci bus cycle, when the FRAME# signal becomes low level by high level, promptly represent the beginning of pci bus cycle.At this moment, what present on the AD bus is the address of addressing that pci bus cycle is desired, and on the C/BE# bus, present be the instruction.Whether all devices can be decoded to this address and instruction on the pci bus cycle, itself be the destination apparatus (target device) of this pci bus cycle to determine.If then send DEVSEL# signalisation host pci and carry out follow-up data transfer operation.If destination apparatus can't be finished read-write operation, that is can't respond the TRDY# signal, then can send a STOP# signal, should the cycle in order to notice host pci retry.
The one-step debugging card at application PCI interface proposed by the invention promptly utilizes described retray function.Its with the address of the pci bus cycle desiring to inspect, data, instruction, after signal conditions such as BE# are latched and are shown by LED, forcing the DEVSEL# signal in following one-period is that low level is responded this pci bus cycle to try to be the first, and the TRDY# signal maintained high level, to prolong this cycle.Previous address of being latched, data, instruction, signal condition such as BE# thereby always be shown on the LED is as the foundation of inspecting of step-by-step debugging.And switch by switching (SWITCH) circuit at last, send a STOP# signal, should the cycle in order to notice host pci retry.Also simultaneously the DEVSEL# signal is drawn during the STOP# signal ended to be high level, the notice host pci finishes the cycle that this is blocked.When this cycle was carried out retry, repeating said steps was to reach the function of step-by-step debugging.
The invention provides a kind of method of using the step-by-step debugging of pci bus, this method comprises the following step at least: (FRAME#) maintains low level with the frame signal on this pci bus; Latch the address and instruction of this pci bus cycle; With the address decoder of this pci bus cycle of latching, to determine that this address is this address of ROM (read-only memory) read cycle; Show this address and this instruction of this pci bus cycle; IRDY# ready signal, TRDY# ready signal on ROM (read-only memory) control signal (ROMCE#) and this pci bus are maintained low level simultaneously; The data and the hyte that latch this pci bus cycle enable (BE#); These data and this hyte that show this pci bus cycle enable; Wait is sent a device by destination apparatus and is selected signal (DEVSEL#), and this device selection signal maintains low level, and this IRDY# ready signal, when this TRDY# ready signal maintains low level simultaneously, intercepts this pci bus cycle; And when before this pci bus cycle finishes, when this destination apparatus can't be responded the TRDY# ready signal, host pci provided the function of a retry.
The present invention also provides a kind of one-step debugging card of using pci bus, and this Debug Card comprises at least: first latch, in order to latch the address of pci bus cycle; The address light emitting diode is in order to show this address; Second latch is in order to latch the data of pci bus cycle; The data light emitting diode is in order to show this data; The 3rd latch is in order to latch the instruction of pci bus cycle; The instruction light emitting diode is in order to show this instruction; Quad latch enables (BE#) in order to the hyte that latchs pci bus cycle; Hyte enables light emitting diode, enables in order to show this hyte; Device is selected signal (DEVSEL#) control circuit, comprise the counter and first d type flip flop, select signal in order to control this device, and intercepting pci bus cycle, described counter utilizes the input of ROM (read-only memory) control signal (ROMCE#) as this counter, stops the output of counting as this counter; And commutation circuit, produce a stop signal (STOP#), and according to this this pci bus cycle of stop signal retry, described commutation circuit also comprises spring and suppresses circuit, d type flip flop and one shot multivibrator.
Description of drawings
Fig. 1 is the structure calcspar of known computer systems;
Fig. 2 is the present embodiment sequential chart, shows the different bus transmission frequency, the relation of the timing that is produced with foundation pci bus transmission frequency;
Fig. 3 is the step-by-step debugging signal flow graph of the embodiment of the invention;
Fig. 3 A is the synoptic diagram of latching of the embodiment of the invention and explicit address and data; And
Fig. 3 B is that latching of the embodiment of the invention and idsplay order and hyte enable the synoptic diagram of (Byte enable).
Embodiment
Relevant detailed content of the present invention and technology, accompanying drawings is as follows.
The sequential chart of the embodiment of the invention as shown in Figure 2, the sequential chart of Fig. 2 shows the relation of different bus transmission frequency and the timing that is produced according to the pci bus transmission frequency.With regard to a normal pci bus cycle,, promptly represent the beginning of pci bus cycle when frame signal (FRAME#) when becoming low level by high level.At this moment, what present on the AD bus is the address (Address) of addressing that pci bus cycle is desired, and on the C/BE# bus, present be the instruction (Command).Whether and all devices can be decoded to this address and instruction on the pci bus cycle, itself be the device (target device) of this pci bus cycle target to determine.If then will install and select signal (DEVSEL#) to maintain low level as response.Data on the AD bus (Data) are active data, and IRDY# ready signal, TRDY# ready signal be simultaneously when low, and the data of expression pci bus are done read-write at this moment and handled.If before end cycle, when destination apparatus can't be responded a TRDY# ready signal, host pci provided the function of a retry, that is sent a stop signal (STOP#) by destination apparatus, and host pci can should the cycle according to STOP# signal retry.
The one-step debugging card at application PCI interface proposed by the invention that is utilize the function of described retry, address with the normal ROM read cycle, after signal conditions such as data latch and show by LED, forcing the DEVSEL# signal in following one-period is that low level is to intercept this cycle, and since one-step debugging card the TRDY# signal is maintained high level, make this cycle can't finish and preceding address of latching, data, instruction and BE# be shown on the LED always.By the switching of commutation circuit, send a STOP# signal at last, should the cycle in order to notice host pci retry.One-step debugging card draws the DEVSEL# signal for high level finishes this cycle with the notice host pci, and carries out retry.
Fig. 3 is the step-by-step debugging signal flow graph of the embodiment of the invention, cooperates Fig. 2 to further specify as follows:
When the FRAME# signal becomes low level by a phase inverter 200, then by first latch, 210 latch addresses and by second latch, 220 latch datas, and show this address and show these data by address LED230 respectively by data LED 240, then simultaneously the Address that latchs is decoded in demoder 250, to determine whether this address is the address (as shown in Figure 3A) of ROM read cycle; When this moment, IRDY# signal and FRAME# signal be high level simultaneously via a Sheffer stroke gate (NAND) 260, with described by demoder 250 decoded addresses by one and (AND) 270, the ROMCE# signal is maintained high level to wait for following one-period.What must further emphasize at this is when the FRAME# signal is high level, the IRDY# signal does not maintain low level as yet immediately, this moment pci clock rising edge (rising edge) still to meet the FRAME# signal be low level, the IRDY# signal maintains high level, so the FRAME# signal is a high level, and the IRDY# signal does not occur in the rising edge of pci clock when maintaining high level, therefore for to avoid producing an invalid control signal, must postpone by 280 pairs of FRAME# signals of delayer.
When IRDY# ready signal, TRDY# ready signal and ROM (read-only memory) control signal (ROMCE#) by a rejection gate (NOR) when becoming low level simultaneously, then by the 3rd latch 290 latch instructions with latch BE# by quad latch 300, and show this instruction and show these BE# (shown in Fig. 3 B) by BE#LED 320 by instruction LED 310.
Preset device is sent the DEVSEL# signal control circuit of a DEVSEL# signal with that, reaches the switching by commutation circuit, sends a STOP# signal and makes following further instruction.
When PCIRST# is low level, perhaps when FRAME# signal and IRDY# ready signal are high level, first of first d type flip flop 330 set output Q 340 be 1 preset input (PRESET).In bus cycles at the beginning the time, when the FRAME# signal is a low level, when the IRDY# ready signal was high level, it was 0 removing input (CLR) that second of second d type flip flop 350 is set output Q 360.At this moment, Q 340 is 1, and DEVSEL# closes; Q 360 is 0, so the STOP# signal also is closed.
Utilize of the input of ROMCE# signal as counter 370, stop counting (TerminalCount, TC) as the output of counter, when clock (CLK) input of first d type flip flop 330 produced rising edge, the width that stops counting depended on the cycle (equaling ROMCE# signal rising edge 2 times) of time clock input, that is after the 2nd ROMCE# signal rising edge, Q 340 transfers 0 to by 1, and counter 370 stops counting, and DEVSEL# opens, signal becomes low level, reaches the purpose in intercepting cycle.
Switching by commutation circuit 380, suppress (De-bounce) circuit 390 via a spring, produce a low paramount time clock, second of second d type flip flop 350 is set output Q 360 and is become 1 by 0, and then make one shot multivibrator (Monostable Multivibrator) 400 produce a STOP# pulse, make the DEVSEL# signal become high level, and counter 370 is normally counted, wait the rising edge of ROMCE# signal.
When the STOP# signal produces, after the rising edge of next pci clock pulse, the IRDY# signal is become high level, to finish this cycle.Then continuing retry should the cycle, reaches the function of step-by-step debugging.
Though the present invention is described in conjunction with preferred embodiment; but this embodiment is not in order to limit the present invention; those of ordinary skill in the art; can modify the present invention under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion by the scope of accompanying Claim.
Claims (7)
1. method of using the step-by-step debugging of pci bus, this method comprises the following step at least:
(FRAME#) maintains low level with the frame signal on this pci bus;
Latch the address and instruction of this pci bus cycle;
With the address decoder of this pci bus cycle of latching, to determine that this address is this address of ROM (read-only memory) read cycle;
Show this address and this instruction of this pci bus cycle;
IRDY# ready signal, TRDY# ready signal on ROM (read-only memory) control signal (ROMCE#) and this pci bus are maintained low level simultaneously;
The data and the hyte that latch this pci bus cycle enable (BE#);
These data and this hyte that show this pci bus cycle enable;
Wait is sent a device by destination apparatus and is selected signal (DEVSEL#), and this device selection signal maintains low level, and this IRDY# ready signal, when this TRDY# ready signal maintains low level simultaneously, intercepts this pci bus cycle; And
When before this pci bus cycle finishes, when this destination apparatus can't be responded the TRDY# ready signal, host pci provided the function of a retry.
2. the method for claim 1, wherein said frame signal maintains the beginning that low level step is represented this pci bus cycle.
3. the method for claim 1, the function of wherein said retry is to send a stop signal (STOP#) by this destination apparatus, and according to this this pci bus cycle of stop signal retry.
4. method as claimed in claim 3, wherein said stop signal are to switch circuit, spring inhibition circuit, d type flip flop and one shot multivibrator by one to produce.
5. the method for claim 1, this address of wherein said this pci bus cycle of demonstration and the step of this instruction are to show by address light emitting diode and instruction light emitting diode respectively.
6. the method for claim 1, the step that these data of wherein said this pci bus cycle of demonstration and this hyte enable is to enable light emitting diode by data light emitting diode and hyte respectively to show.
7. one-step debugging card of using pci bus, this Debug Card comprises at least:
First latch is in order to latch the address of pci bus cycle;
The address light emitting diode is in order to show this address;
Second latch is in order to latch the data of pci bus cycle;
The data light emitting diode is in order to show this data;
The 3rd latch is in order to latch the instruction of pci bus cycle;
The instruction light emitting diode is in order to show this instruction;
Quad latch enables (BE#) in order to the hyte that latchs pci bus cycle;
Hyte enables light emitting diode, enables in order to show this hyte;
Device is selected signal (DEVSEL#) control circuit, comprise the counter and first d type flip flop, select signal in order to control this device, and intercepting pci bus cycle, described counter utilizes the input of ROM (read-only memory) control signal (ROMCE#) as this counter, stops the output of counting as this counter; And
Commutation circuit produces a stop signal (STOP#), and according to this this pci bus cycle of stop signal retry, described commutation circuit also comprises spring and suppresses circuit, d type flip flop and one shot multivibrator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001348582A CN1161693C (en) | 2000-12-06 | 2000-12-06 | One-step debugging card unit with PCJ interface and its operation process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001348582A CN1161693C (en) | 2000-12-06 | 2000-12-06 | One-step debugging card unit with PCJ interface and its operation process |
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| Publication Number | Publication Date |
|---|---|
| CN1357833A CN1357833A (en) | 2002-07-10 |
| CN1161693C true CN1161693C (en) | 2004-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB001348582A Expired - Fee Related CN1161693C (en) | 2000-12-06 | 2000-12-06 | One-step debugging card unit with PCJ interface and its operation process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100419704C (en) * | 2005-09-06 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | Test device and method for external device extended interface |
| CN100424667C (en) * | 2004-11-23 | 2008-10-08 | 笙泉科技股份有限公司 | Data reading and writing method on bridging interface |
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| CN100362485C (en) * | 2003-11-18 | 2008-01-16 | 神达电脑股份有限公司 | Automatic detection of activation earlier stage single step executire program and information collection method and device |
| CN100373348C (en) * | 2003-11-18 | 2008-03-05 | 神达电脑股份有限公司 | Notebook eomputer sturt earlier stage single step interrupt error eliminating device and method |
| CN100388227C (en) * | 2003-11-18 | 2008-05-14 | 神达电脑股份有限公司 | Computer bus periodic single step interrupt error eliminating information automatic collection method and device |
| CN100349128C (en) * | 2003-11-25 | 2007-11-14 | 神达电脑股份有限公司 | Notebook computer PCI bus cycle debugging device and method |
| CN100445956C (en) * | 2004-12-24 | 2008-12-24 | 鸿富锦精密工业（深圳）有限公司 | Device and method for debugging interconnection bus of peripheral devices |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100424667C (en) * | 2004-11-23 | 2008-10-08 | 笙泉科技股份有限公司 | Data reading and writing method on bridging interface |
| CN100419704C (en) * | 2005-09-06 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | Test device and method for external device extended interface |
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| Publication number | Publication date |
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| CN1357833A (en) | 2002-07-10 |
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