CN100362485C - Automatic detection of activation earlier stage single step executire program and information collection method and device - Google Patents
Automatic detection of activation earlier stage single step executire program and information collection method and device Download PDFInfo
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- CN100362485C CN100362485C CNB2003101165450A CN200310116545A CN100362485C CN 100362485 C CN100362485 C CN 100362485C CN B2003101165450 A CNB2003101165450 A CN B2003101165450A CN 200310116545 A CN200310116545 A CN 200310116545A CN 100362485 C CN100362485 C CN 100362485C
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Abstract
The present invention relates to a method and a device for the automatic detection and the information collection of a one-step executive program before a computer is activated. A one-step interruption error-eliminating device comprises a latching control circuit for addresses and commands, a latching control circuit for data actuating signals and byte actuating signals, a decoding circuit for addresses and commands, a signal selecting and generating circuit of a target device and a signal generation circuit for informing bus to stop data transmission. Associated error-eliminating information of the bus cycle of the computer to be detected is latched, when the next bus cycle is started, the signal selecting and generating circuit of a target device actuates a target device to select a signal to a collecting device for error-eliminating information, and the bus cycle is paused. When the signal generation circuit for informing bus to stop data transmission receives a switching simulation signal sent from the collecting device of error-eliminating information of a remote main control station, an STOP# signal is produced, and the bus cycle of the computer to be detected is informed for recovering. The bus cycle interrupted by the one-step error-eliminating device is retried, and the same step is repeated until the data of all standard samples is compared.
Description
Technical field
The debug technology is interrupted in the single step that the present invention relates to a kind of computer system, is meant that especially a kind of computer system activates single step in early stage executive routine and detects automatically and information search method and device.
Background technology
In the general computer system architecture, include nextport hardware component NextPorts such as central processing unit, disk set, input media, output unit, internal memory, these assemblies are to reach by bus to connect and data transmit, the function of control.
When computing machine activates, the basic input/output system of computing machine (BIOS) can carry out a series of test to system hardware, display, keyboard, internal memory, the hard disk to being connected in this computer system for example ... wait and test, system's self test program (Power On Self Test) of being carried out during this start generally abbreviates POST as.In start self test program,, promptly can produce corresponding start test errors sign indicating number (POST Code) if when having detected arbitrary device and existing mistake in computer system.The technician can be according to the definition of this error code, and inquires system mistake place.And for computing machine is made manufacturer, assembling manufacturer or maintenance manufacturer, the important especially detecting information of this start test errors sign indicating number.
Yet, for computer main frame panel that can't normal boot-strap (especially can't carry out first POST code output order smoothly), the technician generally can use the apparatus for debugging (for example being applied in the one-step interrupt debugging card of isa bus or pci bus) that possesses the single step interrupt function to assist case study and trouble hunting.The operating principle of this type of apparatus for debugging is earlier to suspend a certain bus cycles (Bus Cycle), the information that debug is relevant such as the address of bus cycles to be detected (Address), data (Data) and control signal latchs and show by display circuit.At this moment, but the just shown content of this display circuit of interpretation of technician, and contents such as the address in itself and the known normal computer main frame panel start process, data are compared.If content conforms to, just the technician can press the change-over switch on the apparatus for debugging, stop the time-out of these bus cycles, and make computing machine continue to carry out next bus cycles.The technician progressively repeats this process, can finish the program that debug is interrupted in single step.
But carrying out debug in this way has following defective:
1. need progressively to detect and compare the shown debug relevant information of display circuit with manual type, not only consuming time, also be easy to generate erroneous judgement.
2. need to press change-over switch one by one, cause continuous button because of the button bounce or because of finger muscles is tired easily, cause the mistake of key bus cycles debug relevant information with manual type.
In view of this, the present invention is special to be proposed a computing machine and activates single step in early stage executive routine and detect automatically and information search method and device, the debug process of the mode speed-up computation machine that the Ji is detected with robotization, and get rid of possible human error.
Summary of the invention
Fundamental purpose of the present invention promptly provides automatic detection and the information search method that a kind of computing machine activates the executive routine of single step in earlier stage, and the debugging information collector that interrupts an apparatus for debugging and a long-range master station by a single step is desired the bus cycles debug relevant information that quilt is captured in the sense cycle to collect a computing machine to be detected when activating early stage.
Another object of the present invention provides automatic detection and the information search method that a kind of computing machine activates single step in early stage executive routine, be after the debug relevant information that this single step interruption apparatus for debugging will be selected the computer bus to be detected cycle of desire detection is latched, choose signal (DEVSEL#), switch simulate signal and inform that bus stops the processing that data transfer signals (STOP#) produces by the target device, and finish the collection of computing machine to be detected in the debug relevant information in the computer bus to be detected cycle that desire detects.
Wherein this method comprises the following steps:
Step 5, after single step interruption apparatus for debugging receives this switch simulate signal, produce one and inform that bus stops data transfer signals, notify computing machine to be detected to recover the carrying out of bus cycles, and these bus cycles of being interrupted by the single step apparatus for debugging of retry, so repeatedly step 1 to step 5 till all master sample data of master sample data buffer were all compared.
Another object of the present invention provides automatic detection and the information search device that a kind of computing machine activates single step in early stage executive routine, this device includes the debugging information collector that an apparatus for debugging and a long-range master station are interrupted in a single step, and it is connected in this single step by signal connecting line and interrupts apparatus for debugging.Single step is interrupted including in the apparatus for debugging in order to produce the target device and is chosen signal (DEVSEL#) and inform that bus stops the circuit of data transfer signals (STOP#).
In order to realize the invention described above purpose, single step of the present invention is interrupted apparatus for debugging and is mainly included an address and order latch control circuit, in order to latch the address and the order in the computer bus to be detected cycle that desire detects; One data and byte enable signal latch control circuit are in order to latch the data and the byte enable signal in the computer bus to be detected cycle that desire detects; One address and command decoder circuit, the address and the order in the computer bus to be detected cycle of detecting in order to the desire that will be latched are deciphered; One target device is chosen signal generating circuit, after the debug relevant information in the computer bus to be detected cycle that selected desire detects latchs, this single step is interrupted apparatus for debugging when the next bus cycles begin, choose signal generating circuit activation one target device by this target device and choose signal (DEVSEL#), and suspend the carrying out of this next one bus cycles to the debugging information collector; One informs that bus stops data transfer signals and produces circuit, when receiving this switch simulate signal of being sent here by the debugging information collector of long-range master station, deliver to this target device in order to generation STOP# signal and choose in the signal generating circuit, so that the interrupted bus cycles of computing machine retry to be detected.This debugging information collector includes: a steering logic produces circuit, in order to producing this switch simulate signal, and deliver to that single step interrupts apparatus for debugging inform that bus stops data transfer signals and produces circuit; At least one impact damper interrupts the debug relevant information that apparatus for debugging is sent here in order to temporary this single step; One interrupt request singal produces circuit, interrupt the target device that apparatus for debugging sends here and choose signal in order to receive this single step, and produce the central processing unit of an interrupt request singal according to this to this long-range master station, write one by one in the debug relevant information buffer zone of internal memory in the long-range master station with the debugging information that this single step interruption apparatus for debugging is sent here.
Under foregoing structure, after the debugging information collector receives this DEVSEL# signal, the debug relevant information that apparatus for debugging latched is interrupted in this single step write one by one in the debugging information buffer zone of long-range master station.The signal condition and master sample data of the debug relevant information of this new collection are compared,, then produce switch simulate signal a to single step and interrupt apparatus for debugging by the debugging information collector if be consistent.After single step interruption apparatus for debugging receives this switch simulate signal, produce one and inform that bus stops data transfer signals (STOP#), notify computing machine to be detected to recover the carrying out of bus cycles, and these bus cycles of being interrupted by the single step apparatus for debugging of retry, so same repeatedly step was till all master sample data were all compared.
Other purpose of the present invention and design thereof will be further described by following preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1 shows system of the present invention connection diagram;
Fig. 2 is the system's connection diagram that shows between a computing machine to be detected and single step of the present invention interruption apparatus for debugging and the long-range master station;
Fig. 3 is the circuit block diagram that shows single step interruption apparatus for debugging of the present invention;
Fig. 4 is the system's connection diagram that shows long-range master console of the present invention and debugging information collector;
Fig. 5 is the circuit block diagram of debugging information collector in the displayed map 4;
Fig. 6 shows between single step interruption apparatus for debugging of the present invention, computing machine to be detected, debugging information collector carrying out the sequential chart that the single step interruption removes each coherent signal of staggering the time.
Wherein, description of reference numerals is as follows:
1 computing machine to be detected
11 central processing units
12 storeies
13 PCI bridges
14 PCI/ISA bridges
151 system buss
152 pci buss
153 isa bus
Apparatus for debugging is interrupted in 2 single steps
21 addresses and order latch control circuit
Control logic circuit is latched in 211 addresses and order
212 addresses and order latch/buffer
213 addresses and commands buffer control logic circuit
214 addresses and commands buffer
22 addresses and command decoder circuit
23 target devices are chosen (DEVEL#) signal generating circuit
24 data and byte enable signal (DATA/BE#) latch control circuit
241 data and byte enable signal latch control logic circuit
242 data and byte enable signal latch/buffer
25 display device
251 addresses and order display unit
252 data and byte enable signal display unit
26 operating switchs
261 bounce-back jumping circuits
27 inform that the bus terminating number reportedly send (STOP#) signal generating circuit
281 signal input connectors
282 signal output connectors
3 long-range master stations
30 debugging information collectors
300 connectors
301 interrupt request singals produce circuit
302 I/O address buffers
303 I/O data buffers
304 I/O control signal impact dampers
305 steering logics produce circuit
306 wrong warning circuits
31 central processing units
32 storeies
321 debugging information buffer zones
322 master sample data buffers
33 PCI bridges
34 PCI devices
35 PCI/ISA bridges
36 ISA devices
371 system buss
372 pci buss
373 isa bus
4 signal connecting lines
Embodiment
At first consulting shown in Figure 1ly, is the system's connection diagram that shows between a computing machine to be detected and single step of the present invention interruption apparatus for debugging and the long-range master station.Basically, system of the present invention can interrupt the debugging information collector 30 that apparatus for debugging 2 and is installed on long-range master station 3 by a single step that is installed on computing machine 1 to be detected and constituted.The debugging information collector 30 that apparatus for debugging 2 and long-range master station 3 are interrupted in this single step can be connected by a signal connecting line 4 (for example with signal cable or tool thimble mode) between the two, and this signal connecting line 4 is in order to transmit debugging information and to carry out the required associated control signal of signal exchange (Handshaking) as single step interruption apparatus for debugging 2, debugging information collector 30 between the two.
In a typical computing machine 1 to be detected (consulting shown in Figure 2), mainly include central processing unit 11, storer 12, PCI bridge 13 (PCI Bridge), PCI/ISA bridge 14 (PCI/ISA Bridge).Central processing unit 11 is to be connected in system bus 151 with storer 12, and this system bus 151 connects a pci bus 152 (Peripheral Component Interconnect) by PCI bridge 13 again.Pci bus 152 is the bus specifications that proposed by PCISIG association, can be for connecting various PCI devices (for example interface devices such as LAN interface card, presentation card, output inputting interface card) on this pci bus 152.This pci bus 152 connects an isa bus 153 (Industry StandardArchitecture) by PCI/ISA bridge 14, and configurable several ISA slots on this isa bus 153 are for the various ISA devices of pegging graft.
Single step interrupt apparatus for debugging 2 be can plug-in card mode be plugged in pci bus 152 slots of computing machine 1 to be detected.In the pci bus specification of standard, its pin can be divided into system according to function and support pin, address and data pin, interface control signal, bus arbitration signal, reaches the error informing signal.Pin function related to the present invention and definition outline as follows:
PCICLK (Clock, pci system clock pulse): the pci bus clock signal is provided.
AD[31..0] (Address Bus, address bus): the address/data signal of 32 pci bus.
C/BE#[3..0] (Command/Byte Enable, order/byte enable signal): the order and the byte enable signal of multitask output.When address phase, the corresponding byte of indication will be referred to the data transfer if activate then; When data phase, be function as order, the type of indication bus.
FRAME# (Frame, data transmit the frame signal) is activated by bus controller, the beginning that designation data shifts, and continue during the whole action.
IRDY# (Initiator Ready, main end device is ready for) is activated by bus controller, and indication is placed in the data of setting up on the bus, or has been ready for reading of data in bus.
TRDY# (Target Ready, the target device is ready for) is activated by the device that is selected, and indication is placed on data on the bus, or has been ready for reading of data in bus.
DEVSEL# (Device Select, the target device is chosen) is activated by the device that is selected, and informs bus controller, its cognitive setting position to oneself.
STOP# (Target Ready, I/O inform that the bus terminating number reportedly send) is activated by the device that is selected, and informs that bus controller stops present ongoing data transfer action.
The circuit block diagram that apparatus for debugging 2 is interrupted in single step among the present invention please refer to shown in Figure 3, and it mainly includes, and an address and order latch control circuit 21, an address and command decoder circuit 22, a target device are chosen (DEVEL#) signal generating circuit 23, data and byte enable signal (DATA/BE#) latch control circuit 24, a display device 25, an operating switch 26, informs that the bus terminating number reportedly send (STOP#) signal generating circuit 27.
Address among Fig. 3 and order latch control circuit 21 include an address and control logic circuit 211 (Address/Command Latch Control Logic), an address and order latch/buffer 212 (Address/Command Latch Register), an address and commands buffer control logic circuit 213 (Address/Command Buffer Control Logic), an address and commands buffer 214 (Address/Command Buffer) are latched in order.Wherein this address and order latch control logic circuit 211 can be in order to produce an address and order latch control signal to address and order latch/buffer 212, with address bus AD[31..0] in address (Address) and C/BE#[3..0] in order (Command) signal latch to this address and order latch/buffer 212.This address and order latch/buffer 212 are first in first out buffers (FIFO), and address and commands buffer 214 also are a first-in first-out buffer (FIFO), and its action is controlled by the impact damper control signal that impact damper control logic circuit 213 is produced.
Address and command decoder circuit 22 are deciphered in order to address and the order of the bus cycles to be detected that will be latched.
DEVSEL# signal generating circuit 23 is after the bus cycles to be detected finish, at next pci bus cycle at the beginning, the FRAME# signal is after the low state, activation one DEVSEL# signal is to debugging information collector 30, after the STOP# pulse wave signal produced, this DEVSEL# signal was then replied and is high state.
Include data and byte enable signal in data and the byte enable signal latch control circuit 24 and latch control logic circuit 241 (Data/BE#Latch Control Logic) and data and byte enable signal latch/buffer 242 (Data/BE#Latch Register).Wherein these data and byte enable signal latch control logic circuit 241 can be during the bus cycles to be detected in, during the IRDY# in the pci bus and TRDY# all are low state, with AD[31..0] data (Data) and C/BE#[3..0 in the bus] in byte enable signal BBE# be latching in these data and the byte enable signal latch/buffer 242.These data and byte enable signal latch/buffer 242 are to be a first in first out buffer (FIFO).
Include an address and order display unit 251 and data and byte enable signal (BE#) display unit 252 in the display device 25.Wherein this address and order display unit 251 be connected in this address and order in the latch control circuit 21 the address and the output terminal of commands buffer 214, in order to show desire sense cycle be latched address and coomand mode.Data and byte enable signal display unit 252 are to be connected in the data in these data and the byte enable signal latch control circuit 24 and the output terminal of byte enable signal (BE#) latch/buffer 242, in order to show the state that is latched data and byte enable signal (BE#) of desiring sense cycle.
Operating switch 26 is under user's manual operation, can produce an open/close switching signal to STOP# signal generating circuit 27, and this switching signal can be via a bounce-back jumping circuit 261, to eliminate this operating switch 26 in the open/close instantaneous unstable signal that is produced.
This STOP# signal generating circuit 27 is can be whenever receiving this operating switch 26 when being pressed the switching signal that is produced by the back or detecting the switch simulate signal SW-EMULATE that is sent here via signal input connector 281 by the debugging information collector 30 of long-range master station 3, in order to produce a STOP# signal.This STOP# signal can be sent in the aforesaid DEVSEL# signal generating circuit 23, so that the pci bus of mobile computer to be detected repeats the present bus cycles.
In the circuit block diagram shown in Figure 3, other includes a signal input connector 281 and a signal output connector 282, and wherein this signal input connector 281 is to deliver in the STOP# signal generating circuit 27 in order to the switch simulate signal SW-EMULATE that the debugging information collector 30 with long-range master station 3 is produced.And signal output connector 282 also is the debugging information collector 30 that is connected to long-range master station 3, so that signals such as address, data, order, BE#, DEVSEL# are delivered in this debugging information collector 30.
Fig. 4 is the system's connection diagram that shows long-range master console 3 of the present invention and debugging information collector 30.This long-range master console 3 can adopt the computer system of central processing unit, input and output interfaces and the operating system of any pattern to constitute, in the present embodiment be with the computer installation that can support pci bus interface be embodiment further specify as after.
This long-range master station 3 consists predominantly of central processing unit 31, storer 32, PCI bridge 33, PCI device 34, PCI/ISA bridge 35, ISA device 36.Central processing unit 31 is to be connected in system bus 371 with storer 32, and this system bus 371 connects a pci bus 372 by PCI bridge 33 again.Can be on this pci bus 372 for connecting various PCI devices 34.This pci bus 372 connects an isa bus 373 by PCI/ISA bridge 35, can be for connecting various ISA devices 36 on this isa bus 373.
Include a debugging information buffer zone 321 in the storer 32, it is in order to deposit the debug relevant information that all have collected each bus cycles (Bus Cycle), for example signal conditions such as the address of a certain bus cycles, data, control.Debugging information collector 30 is the pci buss 372 that are connected in long-range master station 3, and it is connected to single step and interrupts apparatus for debugging 2 via connector 300 and signal connecting line 4.Include a master sample data buffer 322 in the storer 32 in addition.
Fig. 5 is the circuit block diagram of debugging information collector 30 in the displayed map 4, and it mainly includes an interrupt request singal and produces circuit 301, an I/O address buffer 302 (I/O Address Buffer), an I/O data buffer 303 (I/O Data Buffer), an I/O control signal impact damper 304 (I/O Control Signal Buffer), steering logic generation circuit 305, one wrong warning circuit 306.
This steering logic produces circuit 305 is connected in long-range master station 3 via PCICLK, FRAME#, IRDY#, TRDY#, DEVSEL# equisignal line pci bus 372, and can produce one and remove interrupt request singal INT_DST and produce circuit 301 to interrupt request singal, and produce a control signal respectively and read RD_CONTROL, a data read RD_DATA, an address and read the RD_ADDRESS signal to I/O address buffer 302, I/O data buffer 303, and I/O control signal impact damper 304.
Fig. 6 shows between single step interruption apparatus for debugging of the present invention, computing machine to be detected, long-range master station carrying out the sequential chart that the single step interruption removes each coherent signal of staggering the time.Now cooperate simultaneously aforementioned circuit figure to control flow of the present invention do an explanation as after.
At first, the single step that is installed on computing machine 1 to be detected is interrupted after apparatus for debugging 2 latchs the signal conditions such as address (Address), data (Data) and control in a certain desire testbus cycle, apparatus for debugging 2 is interrupted in this single step can be when the next bus cycles begin, the activation DEVSEL# signal of trying to be the first, and the TRDY# signal is maintained forbid (Inactive) state, to suspend the carrying out of these bus cycles.
This one interrupts the DEVSEL# signal that apparatus for debugging 2 is produced by single step, can be sent to the debugging information collector 30 of long-range master station 3 by signal connecting line 4, this debugging information collector 30 produces circuit 301 by interrupt request singal immediately and triggers a hardware interrupts request signal INTA#, requires to handle this interrupt request via pci bus 372 to central processing unit 31.Again via the operation of interrupt handler software, debugging information collector 30 can make central processing unit 31 send that (I/O Read) read in a series of output input and internal memory writes (Memory Write) instruction, produce a control signal respectively by steering logic generation circuit 305 and read RD_CONTROL, one data read RD_DATA, the RD_ADDRESS signal is read to I/O address buffer 302 in one address, I/O data buffer 303, and I/O control signal impact damper 304, the debugging information that this single step interruption apparatus for debugging 2 is sent here is delivered to central processing unit 31 via pci bus 372 one by one, and in the debugging information buffer zone 321 of write store 32, that is be in order to deposit the debug relevant information of all each pci bus cycles of having collected at this debugging information buffer zone 321.
After debugging information has all write debugging information buffer zone 321, interrupt handling routine can make the steering logic of debugging information collector 30 produce circuit 305 and send a releasing interrupt request singal INT_DST to interrupt request singal generation circuit 301, produces circuit 301 with the notice interrupt request singal and removes interrupt request.
If should new address of collecting, signal conditions such as data, control compare with the master sample data content of master sample data buffer 322 and meet, then central processing unit 31 makes steering logic produce circuit 305 and produces a switch simulate signal SW_EMULATE, and this signal is sent back to single step via signal connecting line 4 and interrupted apparatus for debugging 2.Because in fact this switch simulate signal SW_EMULATE is equivalent to the switching of switch, therefore the STOP# signal generating circuit 27 automatic STOP# signals that produce of apparatus for debugging 2 are interrupted in single step, the carrying out of notifying computing machine to be detected 1 to recover the bus cycles, and these bus cycles of being interrupted by single step apparatus for debugging 2 of retry.Same repeatedly step like this was till all master sample data of master sample data buffer 322 were all compared.
And the operation by long-range master station software program via all each bus cycles debug relevant informations that debugging information buffer zone 321 was collected, can be stored into data memory device (as Winchester disk drive), with as the further usefulness of debug analysis and statistics.
To sum up say the automatic detection of aforementioned calculation machine activation single step in early stage executive routine provided by the present invention and information search method and the industrial utilization of installing true tool height.Above embodiment explanation only be preferred embodiment explanation of the present invention, allly is skillful in this technician when illustrating and do other all improvement and variation according to the above embodiment of the present invention.Yet all improvement and variation that these are done according to the embodiment of the invention are in the claim that still belongs to invention spirit of the present invention and defined.
Claims (13)
1. a computing machine activates the automatic detection and the information search method of single step in early stage executive routine, the debugging information collector that interrupts an apparatus for debugging and a long-range master station by a single step is to collect a computing machine to be detected in the debug relevant information in the computer bus to be detected cycle that desire detects, the bus that apparatus for debugging is connected in this computing machine to be detected is interrupted in this single step, and be connected to the debugging information collector of this long-range master station, wherein this method comprises the following steps:
Step 1, this single step interruption apparatus for debugging will be selected the debug relevant information in the computer bus cycle to be detected of desire detection and be latched;
Step 2, this single step are interrupted apparatus for debugging when the next bus cycles begin, and activation one target device is chosen signal (DEVSEL#), and suspends the carrying out of this next one bus cycles;
Step 3, this debugging information collector receive after this target device chooses signal, debug relevant information that apparatus for debugging latched is interrupted in this single step write one by one in the debugging information buffer zone of this long-range master station;
Step 4, the central processing unit of this long-range master station will write the master sample data of the master sample data buffer of signal condition and this long-range master station of the debug relevant information of this debugging information buffer zone storing and compare, if be consistent, then produce a switch simulate signal to this single step and interrupt apparatus for debugging by this debugging information collector;
Step 5, after this single step interruption apparatus for debugging receives this switch simulate signal, produce one and inform that bus stops data transfer signals (STOP#), notify computing machine to be detected to recover the carrying out of bus cycles, and retry one bus cycles of being interrupted by the single step apparatus for debugging, till step 1 all master sample data of storing up to this master sample data buffer to step 5 were all compared so repeatedly.
2. computing machine as claimed in claim 1 activates the automatic detection and the information search method of single step in early stage executive routine, wherein this debugging information collector interrupts after target device that apparatus for debugging sends here chooses signal in receiving single step, be by interrupt handling routine the debug relevant information that apparatus for debugging latched to be interrupted in this single step to write in the debugging information buffer zone, this interrupt handling routine comprises the following steps:
Interrupt request singal by the debugging information collector produces the central processing unit of circuit triggers one hardware interrupts request signal to long-range master station;
Send by the central processing unit of this long-range master station that a series of output input is read and internal memory writes instruction, steering logic by this debugging information collector produces that circuit produces respectively that a control signal reads, I/O address buffer to this debugging information collector of a data read, an address read number of winning the confidence, I/O data buffer, and I/O control signal impact damper, makes this single step interrupt the debug relevant information that apparatus for debugging sends here and writes one by one in the debugging information buffer zone of long-range master station internal memory;
After the debug relevant information has all write the debugging information buffer zone, produce circuit by this steering logic and send a releasing interrupt request singal to interrupt request singal generation circuit, remove interrupt request with notice.
3. computing machine as claimed in claim 1 activates the automatic detection and the information search method of single step in early stage executive routine, and wherein these master sample data are by in the pre-loaded master sample data buffer to this long-range master station internal memory.
4. computing machine as claimed in claim 1 activates the automatic detection and the information search method of single step in early stage executive routine, do not meet if wherein write signal condition and this master sample data comparison result of the debug relevant information of this debugging information buffer zone, then this long-range master station also has the function of a generation caution.
5. computing machine as claimed in claim 1 activates the automatic detection and the information search method of single step in early stage executive routine, comprises that more the debug relevant information in the computer bus to be detected cycle of the desire detection that this single step interruption apparatus for debugging is latched is presented at the step of a display device respectively.
6. computing machine as claimed in claim 1 activates the automatic detection and the information search method of single step in early stage executive routine, and wherein this single step debug relevant information of interrupting the computer bus cycle to be detected that desire that apparatus for debugging latchs detects comprises address, data, the command information of these bus cycles.
7. computing machine as claimed in claim 1 activates the automatic detection and the information search method of single step in early stage executive routine, and it more comprises this debug relevant information is stored into the step that data memory device is used for further debug analysis and statistics.
8. a computing machine activates the automatic detection and the information search device of single step in early stage executive routine, include a single step and interrupt a debugging information collector of an apparatus for debugging and a long-range master station, in order to collect computing machine to be detected in the debug relevant information in the debug cycle in the computer bus to be detected cycle that desire detects, wherein
This single step is interrupted apparatus for debugging and is included:
One address and order latch control circuit are in order to latch the address and the order in the computer bus to be detected cycle that desire detects;
One data and byte enable signal latch control circuit are in order to latch the data and the byte enable signal in the computer bus to be detected cycle that desire detects;
One address and command decoder circuit, the address and the order in the computer bus to be detected cycle of detecting in order to the desire that will be latched are deciphered;
One target device is chosen signal generating circuit, after the debug relevant information in the computer bus to be detected cycle that selected desire detects latchs, this single step is interrupted apparatus for debugging when the next bus cycles begin, choose signal generating circuit activation one target device by this target device and choose signal (DEVSEL#), and suspend the carrying out of this next one bus cycles to the debugging information collector;
One informs that bus stops data transfer signals and produces circuit, when the switch simulate signal of being sent here whenever the debugging information collector that receives this long-range master station, inform that in order to produce one bus stops data transfer signals and delivers to this target device and choose in the signal generating circuit, so that the interrupted bus cycles of computing machine retry to be detected;
This debugging information collector includes:
One steering logic produces circuit, in order to producing this switch simulate signal, and deliver to that single step interrupts apparatus for debugging inform that bus stops data transfer signals and produces circuit;
At least one impact damper interrupts the debug relevant information that apparatus for debugging is sent here in order to temporary this single step;
One interrupt request singal produces circuit, interrupt the target device that apparatus for debugging sends here and choose signal in order to receive this single step, and produce the central processing unit of an interrupt request singal according to this to this long-range master station, write one by one in the debugging information buffer zone of internal memory in the long-range master station with the debug relevant information that this single step interruption apparatus for debugging is sent here.
9. computing machine as claimed in claim 8 activates the automatic detection and the information search device of single step in early stage executive routine, and wherein this address and order latch control circuit include:
Control logic circuit is latched in one address and order, in order to produce an address and order latch control signal;
One address and order latch/buffer in receiving this address and order when latching address that control logic circuit produces and order latch control signal, are latched the address and the command signal of computing machine to be detected;
One address and commands buffer control logic circuit are in order to produce an impact damper control signal;
One address and commands buffer, under the control of the impact damper control signal that this address and commands buffer control logic circuit are produced, the address and the command signal that will be latched in address and the order latch/buffer are deposited in to address and commands buffer.
10. computing machine as claimed in claim 8 activates the automatic detection and the information search device of single step in early stage executive routine, and wherein these data and byte enable signal latch control circuit include:
One data and byte enable signal latch control logic circuit, in order to produce data and byte enable signal latch control signal;
One data and byte enable signal latch/buffer, in receiving these data and byte enable signal when latching data that control logic circuit produces and byte enable signal latch control signal, the data and the byte enable signal of computing machine to be detected latched.
11. computing machine as claimed in claim 8 activates the automatic detection and the information search device of single step in early stage executive routine, wherein this single step interruption apparatus for debugging is the pci bus that is plugged in computing machine to be detected, and this debugging information collector is the pci bus that is plugged in long-range master station, and single step is interrupted being connected via a signal connecting line between apparatus for debugging and the automatic collector of this debugging information.
12. computing machine as claimed in claim 8 activates the automatic detection and the information search device of single step in early stage executive routine, wherein this single step interruption apparatus for debugging more includes an address and order display unit, be connected to this address and order latch control circuit, be latched address and coomand mode in order to what show computer bus to be detected cycle that desire detects.
13. computing machine as claimed in claim 8 activates the automatic detection and the information search device of single step in early stage executive routine, wherein this single step interruption apparatus for debugging more includes data and byte enable signal display unit, be connected to these data and byte enable signal latch control circuit, in order to show the state that is latched data and byte enable signal in the computer bus to be detected cycle that desire detects.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101165450A CN100362485C (en) | 2003-11-18 | 2003-11-18 | Automatic detection of activation earlier stage single step executire program and information collection method and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101165450A CN100362485C (en) | 2003-11-18 | 2003-11-18 | Automatic detection of activation earlier stage single step executire program and information collection method and device |
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| CN1619503A CN1619503A (en) | 2005-05-25 |
| CN100362485C true CN100362485C (en) | 2008-01-16 |
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| CNB2003101165450A Expired - Fee Related CN100362485C (en) | 2003-11-18 | 2003-11-18 | Automatic detection of activation earlier stage single step executire program and information collection method and device |
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| CN100568205C (en) * | 2007-12-28 | 2009-12-09 | 威盛电子股份有限公司 | Data trade blocking method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297194A (en) * | 1999-11-18 | 2001-05-30 | 神达电脑股份有限公司 | Debugging device and method used in early phase of start for computer system |
| CN1357833A (en) * | 2000-12-06 | 2002-07-10 | 神达电脑股份有限公司 | One-step debugging card unit with PCJ interface and its operation process |
| CN1357834A (en) * | 2000-12-06 | 2002-07-10 | 神达电脑股份有限公司 | One-step interrupt debugging card unit for PCI bus period and its operation process |
| CN1393789A (en) * | 2001-06-21 | 2003-01-29 | 神达电脑股份有限公司 | Method and device for debuggin with single-step interrupt in peripheral element interconnection bus cycle |
| TW548544B (en) * | 2001-03-09 | 2003-08-21 | Mitac Int Corp | Method for single-step interruption debug for PCI bus cycle and the device thereof |
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2003
- 2003-11-18 CN CNB2003101165450A patent/CN100362485C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297194A (en) * | 1999-11-18 | 2001-05-30 | 神达电脑股份有限公司 | Debugging device and method used in early phase of start for computer system |
| CN1357833A (en) * | 2000-12-06 | 2002-07-10 | 神达电脑股份有限公司 | One-step debugging card unit with PCJ interface and its operation process |
| CN1357834A (en) * | 2000-12-06 | 2002-07-10 | 神达电脑股份有限公司 | One-step interrupt debugging card unit for PCI bus period and its operation process |
| TW548544B (en) * | 2001-03-09 | 2003-08-21 | Mitac Int Corp | Method for single-step interruption debug for PCI bus cycle and the device thereof |
| CN1393789A (en) * | 2001-06-21 | 2003-01-29 | 神达电脑股份有限公司 | Method and device for debuggin with single-step interrupt in peripheral element interconnection bus cycle |
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| CN1619503A (en) | 2005-05-25 |
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