CN101261974A - 电学互连和用于形成电学互连的方法 - Google Patents

电学互连和用于形成电学互连的方法 Download PDF

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CN101261974A
CN101261974A CNA2008100832341A CN200810083234A CN101261974A CN 101261974 A CN101261974 A CN 101261974A CN A2008100832341 A CNA2008100832341 A CN A2008100832341A CN 200810083234 A CN200810083234 A CN 200810083234A CN 101261974 A CN101261974 A CN 101261974A
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semiconductor chip
metal pad
substrate
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S·M·斯里-加亚塔
L·瓦尔德维特
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Ultratech Corp
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Abstract

本发明公开了一种电学互连和用于形成电学互连的方法。具体地公开了一种使用椭圆C4连接装配电子封装组件的构造，所述椭圆C4连接具有用于增强可靠性的最优取向。而且，公开了一种提供椭圆C4连接的方法，当与它们在电子封装组件中的安装相结合地实现时，所述椭圆C4拥有用于增强可靠性的最优取向。在半导体芯片的各个优选角落位置处采用基本上为椭圆形的焊盘或椭圆C4焊盘配置。

Description

电学互连和用于形成电学互连的方法
技术领域
本发明涉及一种使用椭圆C4连接装配电子封装组件(package)的构造，所述椭圆C4连接拥有用于增强可靠性的最优取向。此外，本发明还涉及提供椭圆C4连接的方法，当与它们在电子封装组件中的安装相联系地实现时，所述椭圆C4连接具有用于增强可靠性的最优取向。
背景技术
用于计算机的电子封装组件可以通过将例如拥有约15×15mm的典型尺寸的微处理器芯片连接到尺寸约50×50mm的基板而装配。芯片典型地由硅制成，而基板通常由复合结构构成，所述复合结构具有若干层的铜线和被嵌入到被泛称为“树脂”的聚合物基体中的平面。微处理器芯片和基板之间的电学连接通过被称为C4(可控塌陷芯片连接)的焊点阵列以可操作地确保的方式形成。每个C4将芯片的底表面上的金属焊盘钎焊(braze)或焊接(solder)到位于基板的顶表面上的相应的对称焊盘，其中C4钎焊工艺被定义为回流。在回流过程中，封装组件和C4经历高于焊接材料的熔点的温度(约185℃～230℃)；由此暴露于该温度范围的几分钟时间典型地足以获得部件之间良好的电学和机械连接。如下面更详细描述的，所得的C4的形状由焊盘的形状支配。
已知通常由锡/铅(Sn/Pb)或锡/银/铜(Sn/Ag/Cu-SAC)组成的焊接材料在经历循环应变时，遭遇有限的疲劳寿命，因此，在本现场，在C4中经受的循环应变是由电子封装组件维持的热循环的结果；其中芯片和基板具有不同的热膨胀系数(CTE)，且当暴露于温度变动时，它们相应的材料不同地变形，结果是剪切并损坏C4。为了减少施加到C4的剪切应变，添加了一层底层填充材料，从而在第一或初始回流工艺之后使芯片和基板结合。底层填充材料明显减少了芯片和基板表面之间的相对运动，由此迫使整个组件弯曲。对于C4连接而言，弯曲应力比剪切应力好很多，这将导致增强的可靠性和机械鲁棒性或电子封装组件的强度。
基于附图的图1(a)至1(c)说明了现有技术，示意了通过采用当前类型的C4连接安装在基板上的硅芯片。
在图1(a)中示出了安装在基板上的硅芯片的平面示意图；在图1(b)中示出了其截面图；且图1(c)放大地示出了一个C4的附近区域，其中芯片通过C4连接到基板。嵌入到芯片和基板二者的焊盘的圆形(circular)形状确保C4将具有两个圆形表面；从而在这方面，如图1(c)所示，与从回流工艺得出的突出外型一起，使得C4为接近球形的形状。由此，典型的C4在其中心可以具有约120μm的直径，且在接点处具有约100μm的直径，其高度约为100μm。在广泛采用的产业标准(‘4 on 8’)中，具有100μm焊盘直径的C4分布在节距为200μm方形栅格中。产业趋势是减小C4直径和分布节距，使得可以增加用于高输入/输出(I/O)连接所需要的接点密度。作为示例，产业上还对直径焊盘为25μm、高度为10-20μm且节距为50μm的微C4的性能进行了研究。
芯片-基板组件不仅需要承受现场中的温度循环，在出货之前还需要承受标准深度热循环(DTC)。在两种情况下，如上所述，芯片和基板之间的不同运动在C4中引入剪切应变；考虑这点，所经受的超过阈值(典型地0.1％)的剪切应变导致弹性形变，由此具有弹性形变的重复应变循环导致累积的损害过程，这最终在典型在1000至2000之间的相对少数目的循环下在C4的疲劳失效中达到顶点。距离芯片的中性点最远(距离中性点的距离-DNP)的C4在热循环过程中遭受最大的应变且已知它将最先失效，这得出这样的结论：芯片尺寸的增加必定会减小C4芯片接点的使用寿命期望值。
在给定的温度下到达失效的循环次数(N)由科芬/曼森(Coffin/Manson)在大约50年前提出的经验公式近似地表示如下：
N＝c/(Δen)
常数c和指数n(～2)与材料相关，而Δe代表了在循环过程中经受的弹性形变。在DTC的大多数时间内，焊料的温度足够高以使C4蔓延。这种效应的包含导致更复杂的公式；然而基本观察是：弹性应变的减少导致到达失效的循环次数的基本(非线性)改善。
具体而言，依照现有技术，描述了一种分析回流之后的焊料形状的方法，其中考虑椭圆和圆焊盘之间的比较来解决问题。由此，这方面在Kuo-Ning Chiang等撰写的名为“A Comparison of ThermalStress/Strain Behavior of Elliptical/Round Solder Pads”，Journal ofElectronic Packaging，June 2001，Volume 123，Pages 127-131的文章中得到处理。
发明内容
为了消除或减轻现有技术中尤其通过使用圆(round)C4连接或实质上圆焊盘经受的缺点和限制，相应地，本发明旨在在半导体芯片的各个位置采用基本上为椭圆形的焊盘或椭圆的C4焊盘配置。
常规C4焊盘形状是圆形的且在其应用中，所得的近球形的C4通常对于剪切的方向不敏感。然而，电子封装组件对于变形具有优选方向的倾向，典型地沿着从芯片的中心开始的径向。利用变形的特定图案，本发明独特地采用了椭圆C4配置以增强其疲劳寿命而不损害电子封装组件的电学性能。已经证实，对于给定截面面积的焊盘，对于给定的相对变形，具有最优取向的椭圆印迹(foot print)产生更低的应变和应变能。椭圆焊盘的短轴的取向必须沿顶和底焊盘的相对运动的面内投影排列。椭圆焊盘不仅增加了疲劳极限，还减少了焊料中的电流密度，结果充分缓解了电迁移导致的任何损坏。
因此，本发明的一个目的是提供一种使用处于用于增强其可靠性的最优取向的椭圆C4连接来装配电子封装组件的方法。
本发明的另一目的是提供一种构造，用于使用具有用于增强可靠性的最优取向的椭圆C4连接来装配电子封装组件。
附图说明
现在结合附图参考本发明的优选实施例的详细描述，附图中：
图1a至1c分别示出了根据现有技术的圆形C4连接或焊盘的各个方面。
图2a和2b示出了根据现有技术的C4连接的基本位移向量条件。
图3a示出了根据现有技术的基板上的C4阵列，包括图3b中的其放大部分表示；
图4a和4b分别示出了椭圆焊盘的片段部分和椭圆焊盘的放大部分；
图5示出了沿着短轴承受剪切应变的椭圆C4的示意性示例；
图6示出了椭圆C4的机械性能优点，如图表所示；
图7示出了椭圆C4从其理想位置错取向的影响。
图8示出了作用在椭圆C4上的应力和能量的错取向的影响的图示；
图9示出了在其三种表达方式中经过C4的示意性电流密度分布；
图10a和10b分别示出了分别用于圆形和椭圆C4连接的尺寸的示意表示；
图11a和11b分别示出了经过C4的电流密度分布；以及
图12示出了流经C4连接的电流密度的标准化比较图。
具体实施方式
如附图的图1a所示，示出了其上设置有电子封装组件的半导体芯片12的基板10。如本技术领域中当前采用的，从产生C4连接的图1b中的被环绕部分A，这种结构的半导体芯片12利用了在图1c中以放大尺度示出的基本上圆的球形焊球14(示出了一个)。如上所述，包括印刷电路板18的所有电子封装组件的部件在现有技术中已知。
进一步详细参考附图，如此处所述，图2a示出了由于上和下C4焊盘20、22的相对运动导致的C4连接14的变形状态。基板10的顶面上示出的箭头表示相对运动的向量。图2b示出了三维表达中C4连接的一般化的位移图案。由此，AB和CD代表了顶和底焊盘20、22的位移向量。圆形焊盘20、22的面内相对运动由向量BE给出。因而，向量BE是相对焊盘运动(称为相对运动向量)的面内投影。在这种表达中，假设焊盘20、22被设置为彼此平行。
图3a和3b示出了如现有技术中当前采用的基板10上的C4阵列14，以及其在热循环过程中典型的运动方向。在该示意表达中，假设相对运动或位移向量沿着面内投影的径向定向。特定电子封装组件的详细分析可以指示在电子封装组件实际形成原型或制造之前，运动方向可以被精密地投影。
参考附图的图4a，阐述了本发明的概念。如图4b所示，先前公开的圆形焊盘20、22现在被修改成椭圆焊盘26且每个焊盘26的短轴28被设置为与相对运动或位移向量平行。如图3a和3b中，配置了相同的栅格结构，表示椭圆C4的节距与圆形C4的节距相同。如图4a所示的实现方案的模式包括在基板10的角落附近仅沉积有限数目的椭圆形的C4 30，同时对于所有其它区域维持球形的C4 14。
C4 30向嵌入到半导体芯片12的晶体管(未示出)运送信号和电压，由此可以显示椭圆C4 30可以增强对电迁移的耐受性。因此，在不考虑疲劳的情况下，易于受电迁移影响的当前运送C4可以由椭圆C4 30制成，而其它的可以保留为圆形C4 14，则这可以是本发明的实现方案的第二模式。
C4连接的这些配置中的第一和第二模式的结合对于容易具有疲劳以及电迁移问题的半导体芯片是优选的。
图5示出了椭圆C4 30的示例，它沿着其短轴方向经受剪切应变。C4椭圆截面的纵横比(长轴/短轴)是2.25，通过从圆形开始沿着一个方向将半径拉伸50％并沿着垂直方向将半径减小33％并使得总表面积维持不变而获得。所计算的冯.米塞斯(von Mises)应力在焊盘边缘附近最大。图6示出了长轴的相对增加对应变能和冯.米塞斯应力的影响。这两个量都是通过对接近焊盘的C4的切片(切片的厚度＝7μm)做FE结果求平均而获得。注意，相对于相同截面面积的球形C4的对照物，当沿着其短轴负载时，具有125μm的长轴的椭圆C4减少了10％的应变能。应当强调这些估计基于线性弹性分析，而已知C4在热循环条件(在现场和DTC中)经历弹性形变。然而，在出产(yielding)之前，弹性应力(和应变能)的减少转换成弹性应变和能量方面的优点，且因此获得了电子组件的疲劳寿命的增加。
不像它们的球形对照物，基于椭圆截面的C4不是各向同性的，意味着梯度向量的任何误算或不确定性都将不可避免地使应力和能量增加到预测水平之上。为了使提出的方法简便，它需要是鲁棒的，意味着必须保证实际上可能的误算不将优点变成缺点。
图7说明了椭圆C4从其理想位置错取向的影响。峰值的位置和幅度改变，而图8示出了错取向对于应力和能量的影响。在此，值得注意的是，对于与图6中相同的纵横比，梯度向量中20％的误算仅导致小于4％的应力和能量的增加。换句话说，在选择椭圆截面的C4 30时获得的优点减少，但是没有被消除或更坏地变成潜在的缺点。
承受产业标准DTC循环比承受客户“使用条件”具有更多倍的挑战。DTC循环使得整个电子封装组件承受相同的温度条件，其中不同的位移向量(DDV)具有粘附方向响应(cohesive directions response)。
图9表示在3个高度的位置中通过C4连接的电流密度分布的图示，由此，可以观察到沿着焊盘边缘的电流密度峰。图10a和10b分别示出了用于圆形和椭圆C4的尺寸的示意表达。图11a和11b示出了当通过圆形和椭圆C4驱动200mA电流时的电流密度分布，其中椭圆C4提供较长的边缘以供电流分布，并且由此相当程度地减少了峰值幅度。最后，图12公开了电流密度的标准化比较图。如该示例中使用的，对于1.65的纵横比，获得了10％的峰值电流密度的减小。
上面清晰地描述了通过使用具有椭圆焊盘的C4获得的优于标准球形C4的优点。
总结而言，当沿着最优路径取向时，和产业标准球形C4相比，具有椭圆焊盘的C4具有下列优点：
(1)由于在相同的热循环条件下应力水平减小而获得的疲劳寿命的增加；以及
(2)由于峰值电流密度中获得的减小而获得的对电迁移的敏感度的减小。
本发明的实施方案包括在经受最大应变的半导体芯片区域(即，通常是芯片的角落区域)使用椭圆C4，C4焊盘的短轴沿相对位移向量(即，粗略地沿着从芯片中心开始的径向)排列；类似地，接收最高电流的C4将是椭圆的，其短轴沿向C4馈入功率的水平线排列。
重要的是，强调上述方法不需要任何新的制造工艺；所需要的仅是在半导体芯片和基板上沉积椭圆焊盘，且假设C4在经历回流工艺过程中将具有所期望的形状。
椭圆几何图案的优点可应用于要求使用疲劳倾向材料的附接的所有电学或非电学组件。
尽管已经参考其优选实施例专门示出和描述了本发明，本领域技术人员应当理解，可用做出形式和细节上的上述和其它改变而不偏离本发明的精神和范围。因此，意在说明，本发明不限于描述和说明的具体形式和细节，而是落在所附权利要求的精神和范围内。

Claims (22)

1.一种电子封装组件中的构造，用于在基板和半导体芯片之间提供电学互连，包括C4焊点阵列，每个焊点分别连接所述基板的表面上的金属焊盘和与其位置相对的、所述半导体芯片的表面上的对称金属焊盘，从而形成所述互连，其中所述C4焊点阵列的至少一部分在一致椭圆配置的所述基板和半导体芯片上具有相互面对的金属焊盘。
2.根据权利要求1的构造，其中，所述基板和所述半导体芯片上的非椭圆金属焊盘的剩余部分基本上是圆或圆形配置。
3.根据权利要求1的构造，其中所述基板和所述半导体芯片中每一个都基本上是矩形的，且所述基板和所述半导体芯片上的所述面对的椭圆金属焊盘位于所述半导体芯片的角落区域附近。
4.根据权利要求3的构造，其中所述椭圆金属焊盘的短轴大致沿着从所述面对的半导体芯片的中心朝向所述半导体芯片的分别与其相关的角落区域的径向排列。
5.根据权利要求1的构造，其中所述C4焊点包括位于所述基板和半导体芯片上相关的面对的金属焊盘之间并与其接触的初始球形焊球，在所述各部件的高温回流钎焊过程以及在制造基板与半导体芯片之间的机械和电学连接的过程中，所述焊球呈现所述金属焊盘的形状。
6.根据权利要求5的构造，其中位于所述基板和所述半导体芯片上的椭圆金属焊盘之间的初始球形焊球在其回流过程中永久地变形为与所述金属焊盘一致的基本上为椭圆形的配置。
7.根据权利要求4的构造，其中，响应所述电子封装组件的回流和操作，所述基板和半导体芯片上的椭圆金属焊盘的短轴与所述基板上的金属焊盘和所述半导体芯片上的面对的金属焊盘之间经受的相对运动向量平行地延伸。
8.根据权利要求6的构造，其中，对于所述基板和半导体芯片表面上的所述圆金属焊盘和所述椭圆金属焊盘，维持相同的栅格阵列图案。
9.根据权利要求6的构造，其中所述变形的基本上为椭圆形的C4焊料连接在所述半导体芯片的角落区域中经受的最大应变区域中承受较低的应力和应变。
10.根据权利要求1的构造，其中所述C4焊点选自锡/铅(Sn/Pb)合金和锡/银/铜(Sn/Ag/Cu)合金。
11.根据权利要求6的构造，其中电介质底层填充材料层被插入到所述基板和所述半导体芯片之间，以缓解所述C4焊点所经受的应变。
12.一种用于在基板和半导体芯片之间的电子封装组件中形成电学互连的方法，所述方法包括：
提供C4焊点阵列，每个焊点分别连接所述基板的表面上的金属焊盘和与其位置相对的、所述半导体芯片的表面上的对称金属焊盘；
形成互连，
其中C4焊点阵列的至少一部分在一致椭圆配置的所述基板和半导体芯片上具有相互面对的金属焊盘。
13.根据权利要求12的方法，其中，所述基板和所述半导体芯片上的非椭圆金属焊盘的剩余部分基本上是圆或圆形配置。
14.根据权利要求12的方法，其中所述基板和所述半导体芯片中每一个都基本上是矩形的，且所述基板和所述半导体芯片上的所述面对的椭圆金属焊盘位于所述半导体芯片的角落区域附近。
15.根据权利要求14的方法，其中所述椭圆金属焊盘的短轴大致沿着从所述面对的半导体芯片的中心朝向所述半导体芯片的分别与其相关的角落区域的径向排列。
16.根据权利要求12的方法，其中所述C4焊点包括位于所述基板和半导体芯片上相关的面对的金属焊盘之间并与其接触的初始球形焊球，在所述各部件的高温回流钎焊过程以及在制造基板与半导体芯片之间的机械和电学连接的过程中，所述焊球呈现所述金属焊盘的形状。
17.根据权利要求16的方法，其中位于所述基板和所述半导体芯片上的椭圆金属焊盘之间的初始球形焊球在其回流过程中永久地变形为与所述金属焊盘一致的基本上为椭圆形的配置。
18.根据权利要求12的方法，其中，响应所述电子封装组件的回流和操作，所述基板和半导体芯片上的椭圆金属焊盘的短轴被定向为与所述基板上的金属焊盘和所述半导体芯片上的面对的金属焊盘之间经受的相对运动向量平行地延伸。
19.根据权利要求17的方法，其中，对于所述基板和半导体芯片表面上的所述圆金属焊盘和所述椭圆金属焊盘，维持相同的栅格阵列图案。
20.根据权利要求17的方法，其中所述变形的基本上为椭圆形的C4焊点在存在于所述半导体芯片的角落区域中的最大应变区域中承受较低的应力和应变。
21.根据权利要求12的方法，其中所述C4焊点选自锡/铅(Sn/Pb)合金和锡/银/铜(Sn/Ag/Cu)合金。
22.根据权利要求17的方法，其中电介质底层填充材料层被插入到所述基板和所述半导体芯片之间从而缓解所述C4焊点承受的应变。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034779A (zh) * 2009-10-08 2011-04-27 台湾积体电路制造股份有限公司 具有坚固的拐角凸块的芯片设计
CN103036075A (zh) * 2011-10-03 2013-04-10 泰科电子日本合同会社 电连接器
CN104979315A (zh) * 2014-04-03 2015-10-14 台湾积体电路制造股份有限公司 具有预防金属线裂缝设计的封装件
CN106971945A (zh) * 2016-01-14 2017-07-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN110310929A (zh) * 2018-03-20 2019-10-08 台湾积体电路制造股份有限公司 封装、叠层封装结构及制造叠层封装结构的方法
CN117144455A (zh) * 2023-10-30 2023-12-01 圆周率半导体(南通)有限公司 一种改善MLO C4-PAD电镀dimple的方法

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8022543B2 (en) * 2008-03-25 2011-09-20 International Business Machines Corporation Underbump metallurgy for enhanced electromigration resistance
US20100283141A1 (en) * 2009-05-11 2010-11-11 Chun-Wei Chang Semiconductor chip package
US8742477B1 (en) * 2010-12-06 2014-06-03 Xilinx, Inc. Elliptical through silicon vias for active interposers
US9093332B2 (en) 2011-02-08 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structure for semiconductor devices
US9053943B2 (en) * 2011-06-24 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad design for improved routing and reduced package stress
US20120329263A1 (en) * 2011-06-24 2012-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a bond pad design for improved routing and reduced package stress
US8598691B2 (en) * 2011-09-09 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing and packaging thereof
US9553040B2 (en) 2012-03-27 2017-01-24 Mediatek Inc. Semiconductor package
US9768137B2 (en) * 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US8847391B2 (en) 2012-07-09 2014-09-30 Qualcomm Incorporated Non-circular under bump metallization (UBM) structure, orientation of non-circular UBM structure and trace orientation to inhibit peeling and/or cracking
CN103594443B (zh) * 2012-08-17 2017-04-12 台湾积体电路制造股份有限公司 用于封装件和衬底的接合结构
US9576926B2 (en) * 2014-01-16 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
JP6352644B2 (ja) * 2014-02-12 2018-07-04 新光電気工業株式会社 配線基板及び半導体パッケージの製造方法
US9824990B2 (en) * 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) * 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
CN105430938A (zh) * 2015-11-19 2016-03-23 广东威创视讯科技股份有限公司 一种pcb封装库结构及封装方法
TWI607536B (zh) * 2016-02-24 2017-12-01 矽品精密工業股份有限公司 封裝結構
US9865557B1 (en) 2016-08-30 2018-01-09 International Business Machines Corporation Reduction of solder interconnect stress
EP3588550A4 (en) * 2017-02-22 2021-01-13 Kyocera Corporation SWITCH SUBSTRATE, ELECTRONIC DEVICE AND ELECTRONIC MODULE
US10861773B2 (en) * 2017-08-30 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
TW202040780A (zh) * 2018-11-19 2020-11-01 美商天工方案公司 高耐久性之焊接端子
JP2022011066A (ja) * 2020-06-29 2022-01-17 日本電気株式会社 量子デバイス
US11705378B2 (en) * 2020-07-20 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US11830800B2 (en) * 2021-03-25 2023-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Metallization structure and package structure
US20230197658A1 (en) * 2021-12-21 2023-06-22 International Business Machines Corporation Electronic package with varying interconnects

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404047A (en) * 1992-07-17 1995-04-04 Lsi Logic Corporation Semiconductor die having a high density array of composite bond pads
US5875102A (en) * 1995-12-20 1999-02-23 Intel Corporation Eclipse via in pad structure
US5917702A (en) * 1997-11-26 1999-06-29 Intel Corporation Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
US6133134A (en) * 1997-12-02 2000-10-17 Intel Corporation Ball grid array integrated circuit package
US6268568B1 (en) * 1999-05-04 2001-07-31 Anam Semiconductor, Inc. Printed circuit board with oval solder ball lands for BGA semiconductor packages
US6274474B1 (en) * 1999-10-25 2001-08-14 International Business Machines Corporation Method of forming BGA interconnections having mixed solder profiles
US6774474B1 (en) * 1999-11-10 2004-08-10 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
US6911738B2 (en) * 2003-10-27 2005-06-28 Agilent Technologies, Inc. Method and apparatus for improving defective solder joint detection using x-ray inspection of printed assemblies

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CN102034779A (zh) * 2009-10-08 2011-04-27 台湾积体电路制造股份有限公司 具有坚固的拐角凸块的芯片设计
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US9929126B2 (en) 2014-04-03 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with metal line crack prevention design
US11056464B2 (en) 2014-04-03 2021-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with metal line crack prevention design
US11862606B2 (en) 2014-04-03 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with metal line crack prevention design
CN106971945A (zh) * 2016-01-14 2017-07-21 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN106971945B (zh) * 2016-01-14 2021-01-22 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN110310929A (zh) * 2018-03-20 2019-10-08 台湾积体电路制造股份有限公司 封装、叠层封装结构及制造叠层封装结构的方法
US11404341B2 (en) 2018-03-20 2022-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package and package-on-package structure having elliptical columns and ellipsoid joint terminals
CN117144455A (zh) * 2023-10-30 2023-12-01 圆周率半导体(南通)有限公司 一种改善MLO C4-PAD电镀dimple的方法

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