CN101246816A - Method of fabricating a semiconductor device - Google Patents
Method of fabricating a semiconductor device Download PDFInfo
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- CN101246816A CN101246816A CNA2008100056660A CN200810005666A CN101246816A CN 101246816 A CN101246816 A CN 101246816A CN A2008100056660 A CNA2008100056660 A CN A2008100056660A CN 200810005666 A CN200810005666 A CN 200810005666A CN 101246816 A CN101246816 A CN 101246816A
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Abstract
Disclosed is a method of fabricating a semiconductor device includes the steps of: depositing on a main surface of a semiconductor substrate a layer to be processed; depositing a base layer on the layer to be processed; depositing a first intermediate layer and then a second intermediate layer on the base layer; patterning the second intermediate layer while the base layer covers the layer to be processed; depositing a first mask pattern on the patterned second intermediate layer; patterning the second intermediate layer with the first mask pattern; patterning the first intermediate layer and the base layer with the patterned second intermediate layer to form a second mask pattern; and patterning the layer to be processed, with the second mask pattern.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly a kind of manufacture method that adopts the photoetching process more than 2 times to synthesize the semiconductor device of the pattern that can form minuteness space.
Background technology
In recent years, the progress of lithography technology causes the miniaturization of semiconductor circuit pattern to be strengthened, and it mainly is that short wavelengthization by exposure light source causes.
But, only the rise in price of short wave length exposure device does not cause economic problems, and the necessary device of short wavelength's photoetching law technology, material, mask etc. relate to many-sided technical problem, and address the above problem the difficulty height of itself, so the research of the fine patternsization that the method beyond the employing short wavelengthization is carried out begins to carry out from many aspects.
In addition, in the manufacturing of 32nm node apparatus, the resolution that liquid about NA～1.6 of use high index of refraction soaks the EUV exposure technique level of photoetching process or wavelength 13.5nm is very necessary, but is shown that by the completeness of present various technology exploitation may not be inconsistent with market demand.
Above-mentioned condition is, before and after 2005, M.Maenhoudt etc. have delivered by photolithographic synthetic more than 2 times in 1. at ☆, obtains not meet the method for the pattern-pitch of optical principle, hereafter, constantly increases about the research of using 2 photolithographic methods.
2006, ☆ 2. in, delivered by 2 the synthetic research that obtains the minuteness space of flash memories (Flash memory) of photoetching process by Hynix company, ☆ 3. in, in the same manner by Hynix company reported can cut down do the operation at quarter, use contains the low-cost production flow process of the BARC of Si.
In addition, in the manufacturing of semiconductor device, generally be included in dielectric film, polysilicon or multiple manufacturing procedures such as conducting film such as tungsten silicide, aluminium such as the silicon oxide film that forms on the Semiconductor substrate or silicon nitride film.
In the device of 65nm～45nm design proportion is made,, carry out so the processing of above-mentioned machined layer is following owing to adopt the ArF resist that lacks anti-dried property at quarter to carry out microfabrication.For example, on machined layer, form resist layer, expose and develop, form corrosion-resisting pattern after, be that etching mask is done quarter with this corrosion-resisting pattern, process machined layer thus.
At this moment, desirable exploring degree, exposure boundary or focusing boundary (focus margin) must make the thickness attenuation of resist during in order to ensure exposure.But the thickness of resist is crossed when thin, and having in the dried quarter of machined layer can not the etching corrosion-resisting pattern, and the problem that can not process machined layer.In order to address the above problem, adopt after coated pattern on the machined layer transmits material, painting erosion resistant agent is transferred to pattern with corrosion-resisting pattern and transmits on the material, does the multilayer resist method of carving machined layer.
☆①M.Maenhoudt，J.Versluijs，H.Struyf.J.Van?Olmen，M.Van?Hove，“Double?Patterning?scheme?for?sub-0.25kl?single?damascene?structures?atNA＝0.75，λ＝193nm”″Proc.of?SPIE?Vol.5754，P1508-1518(2005)，
☆②Chang-Moon?Lim，Seo-Min?Kim，Young-Sun?Hwang?et?al.，“Positive?and?Negative?Tone?Double?Patterning?Lithography?For?50nmFlash?Memory”Proc.of?SPIE?Vol.6154，615410-P1-8(2006)
☆③Sungkoo?Lee，Jaechang?Jung，SungyoonCho?et?al.，“Doubleexposure?technology?using?silicon?containing?materials”Proc.of?SPIE?Vol.6153，61531K-P1-7(2006)
Rayleigh (Rayleigh) formula of expression optical resolution is as shown in the formula shown in (1).
R＝k1·(λ/NA) …(1)
Need to prove that in the formula (1), R is a pattern exploring degree, λ is an exposure wavelength, and NA is the lens openings number, and k1 is process factor (process factor).
Herein, process factor k1 is lower than the pattern of the fine repetition interval of " 0.25 ", can not enter lens NA (pupil) according to 1 diffraction light of optical principle, therefore, even under the desirable optical condition that uses complete position phase-shift mask and the illumination of relevant (Coherent) fully, according to the optical principle of physics, can not present pattern.
So, when forming process factor k1 and being lower than the pattern of fine repetition interval of " 0.25 ", adopt behind the pattern that forms 2 times of spacings, between the pattern of this formation, newly form 2 processing methods of pattern again, form the pattern of minuteness space.
But a Synthetic 2 pattern as described above though it is synthetic easily to expect carrying out figure, in fact, as mask, carries out etching, transfer printing to the machined layer of various semiconductor manufacturing usefulness with the light corrosion-resisting pattern, will cause very complexity of technology.
It is generally acknowledged that if merely consider, in order to form synthesising pattern on machined layer, anticipation forms by repeating 2 identical operations of photoetching and etching, also is 2 times but the technology cost is minimum.
Summary of the invention
The present invention forms in view of above-mentioned problem, and its purpose is to provide a kind of manufacture method that can form the semiconductor device of fine pattern when suppressing the technology cost.
One of scheme of the manufacture method of the semiconductor device that the present invention relates to comprises following operation: the operation that forms machined layer on the first type surface of Semiconductor substrate; On machined layer, form the operation of bottom; On described bottom, form the operation in the 1st intermediate layer and the 2nd intermediate layer successively.And, be included in the operation that makes formation pattern in the 2nd intermediate layer under the state with bottom covering machined layer; On the 2nd intermediate layer that forms pattern, form the operation of the 1st mask pattern; Use the 1st mask pattern to make the 2nd intermediate layer form the operation of pattern.In addition, also comprise and use the 2nd intermediate layer that forms pattern, make the 1st intermediate layer and bottom form pattern, form the operation of the 2nd mask pattern; Use the 2nd mask pattern, make machined layer form the operation of pattern.
Other scheme of the manufacture method of the semiconductor device that the present invention relates to: comprise following operation: the operation that on the first type surface of Semiconductor substrate, forms machined layer; On machined layer, form the operation of bottom; On bottom, form the operation in the 1st intermediate layer and the 2nd intermediate layer successively.In addition, be included in to cover under the state of machined layer and make the 2nd intermediate layer form the operation of pattern with bottom; On the 1st intermediate layer that is positioned between the 2nd intermediate layer that forms pattern, form the operation of the 1st mask pattern.Also comprise the 2nd intermediate layer of using the 1st mask pattern and forming pattern, make the 1st intermediate layer form the operation of pattern; Use the 1st intermediate layer that forms pattern, make bottom form pattern, form the operation of the 2nd mask pattern; Use the 2nd mask pattern, make machined layer form the operation of pattern.
Other scheme of the manufacture method of the semiconductor device that the present invention relates to: comprise following operation: the operation that on the first type surface of Semiconductor substrate, forms machined layer; Form the operation of bottom on machined layer; Form the operation in the lamination intermediate layer that forms by the multilayer intermediate layer on bottom; Pattern is implemented repeatedly in the lamination intermediate layer formed, form the operation of lamination patterned layer; With the lamination pattern layer is mask, and bottom and machined layer are carried out etched operation.
According to the manufacture method of the semiconductor device that the present invention relates to, can suppress the rising of technology cost and can form fine pattern again.
By understand by accompanying drawing about following detailed description of the present invention, further set forth the above-mentioned of this invention and other purpose, feature, scheme and advantage.
Description of drawings
[Fig. 1] is the profile of the 1st operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 2] is the profile of the 2nd operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 3] is the profile of the 3rd operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 4] is the profile of the 4th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 5] is the profile of the 5th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 6] is the profile of the 6th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 7] is the profile of the 7th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 8] is the profile of the 8th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Fig. 9] is the profile of the 9th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 1.
[Figure 10] is the profile of the 1st operation of the manufacture method of the semiconductor device that relates to of expression execution mode 2.
[Figure 11] is the profile of the 2nd operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 2.
[Figure 12] is the profile of the 3rd operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 2.
[Figure 13] is the profile of the 4th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 2.
[Figure 14] is the profile of the 5th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 2.
[Figure 15] is the profile of the 6th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 2.
[Figure 16] is the profile of the 7th operation of the manufacturing process of the semiconductor device that relates to of expression execution mode 2.
[Figure 17] profile of operation after for the manufacturing process of expression semiconductor device shown in Figure 15.
[Figure 18] is the profile of the operation after the expression operation shown in Figure 17.
[Figure 19] is the profile of the 1st operation of the manufacturing process of the semiconductor device of expression the 2nd variation.
[Figure 20] is the profile of the operation after the expression manufacturing process shown in Figure 19.
[Figure 21] is the profile of the operation after the expression manufacturing process shown in Figure 20.
[Figure 22] is the profile of the operation after the expression manufacturing process shown in Figure 21.
[Figure 23] is the profile of the operation after the expression manufacturing process shown in Figure 22.
[Figure 24] is the profile of the operation after the expression manufacturing process shown in Figure 23.
[Figure 25] is the profile of the operation after the expression manufacturing process shown in Figure 24.
[Figure 26] is the profile of the operation after the expression manufacturing process shown in Figure 25.
[Figure 27] is the profile of the operation after the expression manufacturing process shown in Figure 26.
The plane graph of the 4th operation of the manufacturing process of the semiconductor device that [Figure 28] relates to for execution mode 1.
The plane graph of the 7th operation of the manufacturing process of the semiconductor device that [Figure 29] relates to for execution mode 1.
The plane graph of the 4th operation the when manufacturing process of the semiconductor device that [Figure 30] relates to for execution mode 1 is applicable to the diplopore form.
The plane graph of the 7th operation the when manufacturing process of the semiconductor device that [Figure 31] relates to for execution mode 1 is applicable to the diplopore form.
The plane graph of the 4th operation of the semiconductor device that [Figure 32] relates to for execution mode 2.
The plane graph of the 6th operation of the semiconductor device that [Figure 33] relates to for execution mode 2.
Embodiment
(execution mode 1)
Use Fig. 1 to Figure 10, the manufacture method of the semiconductor device that present embodiment is related to describes.Need to prove,, provide identical symbol, omit its explanation for identical or suitable formation.Fig. 1 is the profile of the 1st operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment.In this Fig. 1, on the first type surface of Semiconductor substrate 1, form the machined layer 52 (manufacturing process of machined layer finishes) of polysilicon (polysilicon) film etc.
This above machined layer 52 on, form bottom 53, described bottom 53 is for example by adopting chemical vapour deposition technique (CVD (the Chemical Vapor Deposition) method) amorphous carbon that forms, the formations such as polymer that contain aromatic rings such as phenyl, naphthyl that maybe can adopt spin-coating method to form.Need to prove, when adopting chemical vapour deposition technique to form bottom 53, also can form well by chemical vapour deposition technique at this film that forms above bottom 53, when adopting spin-coating method to form bottom 53, the film that forms on bottom 53 also can adopt spin-coating method to form well.
, when constituting bottom 53, can use parallel plate-type plasma CVD equipment or high-density plasma CVD device herein, pile up amorphous carbon film by plasma chemical vapor deposition by amorphous carbon.
As the hydrocarbon gas that becomes the carbon supply source, can from following gas, select: methane (CH
4), ethane (C
2H
6), propane (C
3H
8), butane (C
4H
10), acetylene (C
2H
2), propylene (C
3H
6), propine (C
3H
4) or organic class material dimethylformaldehyde (HCON (CH
3)
2).
This hydrocarbon gas is with helium (He), argon (Ar), nitrogen (N
2) at least a combustion chamber that together imports of waiting carrier (mixing) gas.Then, in 300 ℃～550 ℃ scope, the using plasma chemical vapour deposition technique is piled into the amorphous carbon film (α-c) of the about 300nm of thickness under the pressure below the 10Torr.
As mentioned above, on machined layer 52 on, form that the using plasma chemical vapour deposition technique is piled up, be the bottom 53 that forms of the amorphous carbon more than the 90 weight % (bottom form operation end) by carbon content.
As mentioned above, on the bottom 53 that adopts chemical vapour deposition technique to form, for example form the 1st intermediate layer 54 that pecvd silicon oxide film etc. can form by chemical vapour deposition technique.
, when forming the 1st intermediate layer 54, adopt parallel flat or high-density plasma CVD device herein, use monosilane (SiH with the pecvd silicon oxide film
4), disilane (Si
2H
6), trimethyl silane (Si (CH
3)
4), TEOS gas (Si (OC
2H
5)
4) wait silane gas source (silanesource gas) and, O
2, O
3Oxidation class gases such as gas, CO gas carry out plasma activated chemical vapour deposition.Thus, pecvd silicon oxide film (P-SiO) is for example piled up (the formation operation in the 1st intermediate layer finishes) with the thickness of about 30nm.
Then, on the 1st intermediate layer 54 of adopting chemical vapour deposition technique to form, for example can form the 2nd intermediate layer 55 that plasma silicon nitride film etc. forms by chemical vapour deposition (CVD).For example, when forming this 2nd intermediate layer 55, adopt parallel flat or high-density plasma CVD device, use monosilane (SiH by the plasma silicon nitride film
4), disilane (Si
2H
6), trimethyl silane (Si (CH
3)
4), TEOS gas (Si (OC
2H
5)
4) wait the silane gas source and, N
2O, NH
3Nitrogenize class gases such as gas by plasma chemical vapor deposition, are piled up plasma silicon nitride film (P-SiN), make thickness be about 20nm.
Herein, be benchmark, the 2nd intermediate layer 55 selection ratio with the 1st intermediate layer 54, and be benchmark, the 1st intermediate layer 54 selection ratio with respect to described the 2nd intermediate layer 55 with the 2nd intermediate layer 55 with respect to the 1st intermediate layer 54, for example can be for more than 2.
Have as mentioned above the 1st intermediate layer 54 and the 2nd intermediate layer 55 of bigger selection ratio mutually by on bottom 53, forming; when making the 2nd intermediate layer 55 form pattern; can make the diaphragm performance function of the 1st intermediate layer 54, form the 2nd intermediate layer 55 (formation in the 2nd intermediate layer finishes) than unfertile land simultaneously as bottom 53.
As mentioned above, form bottom 53 that covers above the machined layer 52 and the lamination intermediate layer that on this bottom 53, forms on machined layer 52 with the 1st intermediate layer 54 and the 2nd intermediate layer 55.
As mentioned above, by the layered product (P-SiN (about 20nm)/P-SiO (about 30nm)/α-C (about 300nm)) that forms by amorphous carbon, pecvd silicon oxide film and plasma silicon nitride film lamination when being difficult to control reflectivity, perhaps chemically interacting when causing producing the phenomenon of pattern crimping of resist layer that forms on this layered product and substrate surface can form anti-reflection layer 56 on this layered product.Need to prove that as anti-reflection layer 56, (antireflection coating: daily output chemistry system ARC83 Anti Reflective Coating) etc. for example can be coated with the thickness of about 40nm can to adopt first commercially available minimum organic ARC.
This above anti-reflection layer 56 on, the coating ArF is had photosensitive chemically amplified photo resist agent, afterwards, carry out baking processing (PAB:post applied bake) after the coating about 100 ℃.
Fig. 2 is the profile of the 2nd operation of the manufacturing process of expression semiconductor device.Use mask that above-mentioned resist layer is carried out exposure-processed.2. the mask that uses in this exposure-processed for example can wait the mask of record for ☆, is to be used to form by minimum to eliminate width (the order I width of cloth) (for example, 32nmSpace) and the mask of the partial circuit pattern that constitutes of its residual width of 3 times (96nm Line).Use this mask, resist layer is carried out exposure-processed.
After the exposure, under about 100 ℃ to 140 ℃, carry out the heat treatment about 1 minute, carried out development treatment about 30 seconds～1 minute with 2.38wt% tetrahydrochysene amine-oxides (TMAH) solution.After the development of carrying out under about 100 ℃ about 1 minute, bake, form corrosion-resisting pattern 57.At this moment, as required,, also can use and open 2006-267521 communique, spy as the spy and open external protection on the resist of putting down in writing in the 2006-227632 communique (formation of the 1st corrosion-resisting pattern finishes) on the upper strata of resist layer.
Fig. 3 is the profile of the 3rd operation of the manufacturing process of expression semiconductor device.As shown in Figure 3, use corrosion-resisting pattern 57, pattern is carried out in above-mentioned the 2nd intermediate layer 55 form, on pattern transfer to the 2 intermediate layers 55 with corrosion-resisting pattern 57, form intermediate layer pattern 55a.Need to prove that the etching condition in intermediate layer 55 is to use CF as fluorocarbons class gas
4, CHF
3, CH
2F
2, CH
3The mist class of F or above-mentioned fluorocarbons class.For with the contraposition exactly of following mask, configured in advance can read the alignment mark (formation of the 2nd intermediate layer pattern finishes) of wafer position optically.
Fig. 4 is the profile of the 4th operation of the manufacturing process of expression semiconductor device, and Figure 28 is the plane graph of this 4th operation.As this Fig. 4 and shown in Figure 28, behind the formation intermediate layer pattern 55a, pass through O
2Plasma treatment, ashing are removed corrosion-resisting pattern 57a and anti-reflection layer 56a.In addition, as required, also can and peel off with the wet type resist of sulfuric acid hydrogen peroxide etc.Need to prove, Figure 28, expression is applicable to the situation of double channel mode, but is not limited thereto.Figure 30 is the plane graph of the 4th operation when being applicable to the diplopore mode.As mentioned above, the manufacture method of the semiconductor device that relates to of present embodiment 1 is applicable to double channel mode and diplopore mode.
Fig. 5 is the profile of the 5th operation of the manufacturing process of semiconductor device.As shown in Figure 5, on the pattern 55a of intermediate layer, form resist layer (the 2nd resist layer).
When forming this resist layer, as required, also can before forming resist layer, form anti-reflection layer 60.
This anti-reflection layer 60, for example can following film forming: can be coated with the ARC29 of daily output chemistry system second minimum organic ARC etc. as commercially available organic ARC, making thickness be about 80nm.
By forming above-mentioned anti-reflection layer 60, can make the jump planarization that on the pattern 55a of intermediate layer, forms, make this anti-reflection layer 60 above become the face of general planar.
Wherein, because center pattern 55a is formed by plasma silicon nitride film (P-SiN), thickness is about 20nm, so when forming anti-reflection layer 60, the end and the anti-reflection layer 60 that can be suppressed at intermediate layer pattern 55a produce significantly.In addition, can also be suppressed at and generate thin part in the anti-reflection layer 60 of formation.Then, form resist layer at this on above the anti-reflection layer 60.At this moment, in the end of intermediate layer pattern 55a and do not form very big inclination above the anti-reflection layer 60,, also can suppress the generation of the part that tilts to the resist layer that forms even therefore at this formation resist layer above anti-reflection layer 60.
This resist layer (the 2nd resist layer) can have photosensitive chemically amplified photo resist agent to ArF by coating, implements to bake processing (PAB) after about 100 ℃ the coating and forms.As mentioned above, after forming resist layer,, use mask (the 2nd mask) to carry out exposure-processed by projection aligner.
This mask is in the necessary circuitry pattern, as the 2. described mask of ☆ (the 2nd mask), divided mask (the 2nd mask) in the exposure of the double channel structure that is used for constituting by minimum elimination width (for example, 32nm Space) and its residual width (96nmLine) of 3 times.
When disposing this mask, intermediate layer pattern 55a that has formed and position be the position relation of the mask of side thereon, for example must be configured with the precision of counting about nm.
Herein, adopt and to shine broadband light, detect the method for mark position, confirm the position accurately, carry out illuminating exposure with CCD image devices such as (Charge CoupledDevice) to alignment mark.
Herein, the 1st intermediate layer 54 is the pecvd silicon oxide film, at this intermediate layer pattern 55a that forms the plasma silicon nitride film on above the 1st intermediate layer, is positioned at top situation with the plasma silicon layer and compares, be easy to obtain the optical contrast, be easy to detect the alignment mark position.Therefore, can make mask (the 2nd mask) contraposition with high accuracy.
The configuration mask is when carrying out exposure-processed, can be suppressed to form rake in the resist layer and grade, and becomes the general planar shape, therefore, and the generation that can suppress to defocus.In addition, can also suppress not cause the bad generation of exploring by the resist layer thickness is good.
After exposing as mentioned above, under about 100 ℃～140 ℃, carry out about 1 minute heat treatment.Then, carried out development treatment about 30 seconds～1 minute, after the development of carrying out under about 110 ℃ about 1 minute, bake, form corrosion-resisting pattern (the 2nd corrosion-resisting pattern) 61 with 2.38wt% tetrahydrochysene amine-oxides (TMAH) solution.Be positioned at the slit 161 of 61 of this corrosion-resisting patterns, be positioned at above-mentioned intermediate layer pattern 55a and go up (the formation operation of the 2nd corrosion-resisting pattern finishes).
Need to prove, when making above-mentioned resist layer form pattern, as required, on resist layer on, also can form and open 2006-267521 communique, spy as the spy and open external protection on the resist of 2006-227632 communique record.
Fig. 6 is the profile of the 6th operation of the manufacturing process of expression semiconductor device.As shown in Figure 6, be mask with the corrosion-resisting pattern 61 of above-mentioned formation, make above-mentioned intermediate layer pattern 55a form pattern, the pattern transfer that is formed at corrosion-resisting pattern 61 to the pattern 55a of intermediate layer, is formed intermediate layer pattern (the 2nd intermediate layer pattern) 55b.
Herein, the slit 161 of corrosion-resisting pattern 61 is positioned at center pattern 55a top as mentioned above, forms pattern as described above, and intermediate layer pattern 55b forms the pattern of miniaturization more than intermediate layer pattern 55a.
Herein, the 1st intermediate layer 54 has the function of protection bottom 53, when forming intermediate layer pattern 55b and intermediate layer pattern 55a, can suppress to be etched to bottom 53.Bottom 53 can be kept the state (the formation operation of the 2nd intermediate layer pattern finishes) that covers above the machined layer 52.
Fig. 7 is the profile of the 7th operation of the manufacturing process of expression semiconductor device, and Figure 29 is the plane graph of the 7th operation.So Fig. 7 and shown in Figure 29 passes through O
2Plasma treatment is removed corrosion-resisting pattern 61 and anti-reflection layer 60a.Then, also can and peel off as required with the wet type resist of sulfuric acid hydrogen peroxide etc.Thus, pattern 55b in intermediate layer is exposed to the outside.Need to prove the plane graph of the 7th operation when Figure 31 is applicable to ditrysian type for expression.As shown in figure 31, as diplopore, during the manufacture method of the semiconductor device that suitable present embodiment 1 relates to, can form a plurality of sectional hole patterns with fine interval.
Fig. 8 is the profile of the 8th operation of the manufacturing process of expression semiconductor device.As shown in Figure 8, pattern 55b is a mask with this intermediate layer, makes intermediate layer 54 and bottom 53 form pattern.Thus, form by being transferred the lamination pattern that figuratum intermediate layer pattern 54a and bottom pattern 53a constitute.As mentioned above, bottom 53 finally with these bottom 53 unified the 1st pattern and the 2nd patterns, makes machined layer 52 form pattern as the diaphragm performance function of machined layer 52 simultaneously.
And bottom 53 is made of carbon class films such as amorphous carbon, with the selection that is used for the machined layer (polysilicon, silicon oxide film, silicon nitride film, SiOC film etc.) that various semiconductors make than very big (content of claim 3), be at least more than 10.Thus, can adopt the high machined layer etchant of versatility.
Fig. 9 is the profile of the 9th operation of the manufacturing process of expression semiconductor device.As shown in Figure 9, must form pattern by intermediate layer pattern 54a and bottom pattern 53a by the last machined layer of processing 52.
Become bottom pattern 53a from the intermediate layer pattern 55b transfer printing that applies fine pattern herein.Therefore, can form the machined layer pattern 52a that process factor k1 for example is lower than the fine repetition interval of " 0.25 ".
Herein, be benchmark with bottom pattern 53a, machined layer 52 compares, reaches the 1st intermediate layer 54 with the 2nd intermediate layer 55 with respect to the selection in the 1st intermediate layer 54 and compare big with respect to the selection ratio in the 2nd intermediate layer 55 with respect to the selection ratio of bottom pattern 53a.Therefore, can make machined layer form pattern well.
Can followingly design: i.e. after the etching of machined layer 52 finished, cut down naturally in the 1st, the 2nd intermediate layer 54,55 herein, and the state remaining with carbon class layer finishes etching down.And different with inoranic membrane by the film formed bottom 53 of residual carbon class, the enough oxygen plasmas of energy optionally ashing are removed.On the other hand, for example, the bottom 53 of omission of carbon class film, hard mask with inorganic 2 tunics on machined layer 52 adds man-hour, must remove inoranic membrane at last, in order optionally to remove, must use CMP (chemico-mechanical polishing: the method for removing that is of little use of method and so on Chemical Mechanical Polishing).
And then, about with the machined layer 52 that is the bottom pattern 53a etching polysilicon, silicon oxide film, silicon nitride film, SiOC film etc. of carbon class layer, have a lot of technical resources, can easily use this technology flexibly.
For the bottom pattern 53a of carbon class layer is bigger than very with the selection of the machined layer 52 (polysilicon, silicon oxide film, silicon nitride film, SiOC film etc.) that is used for various semiconductors manufacturings, be at least more than 10, the etching machined layer 52 accurately.
As mentioned above, in the manufacture method of the semiconductor device that present embodiment 1 relates to, under the state on bottom 53 covers above the machined layer 52, make the multilayer intermediate layer that on this bottom 53, forms form pattern, can form the intermediate layer pattern that has formed final pattern.
Therefore,,, compare, can suppress less forming fine pattern operation before on the machined layer 52 with existing manufacturing process so can lower the number of times that is implemented as membrane process owing to protected machined layer 52 and implemented repeatedly photoetching process in upper layer side.And when forming the 1st intermediate layer 54 and the 2nd intermediate layer 55 by chemical vapour deposition technique, the material that can select is more, can take multiple combination.
The manufacture method of the semiconductor device that present embodiment 1 relates to preferably is applicable to diplopore mode and double channel mode, and the diplopore mode preferably is applicable to contact operation, via (via hole) operation.Need to prove that because preferential dual damascene (dual damocene) operation of via need be imbedded via, so the spin coating organic underlayer is imbedded via, 2 layers of intermediate layer imbedding well behaved application type are useful.In addition, the double channel mode preferably is applicable to the multilayer wired operation of the Cu that is undertaken by the mosaic procedure that forms the ditch distribution.
＜variation 1 〉
As described above, the situation that forms bottom 53 on machined layer 52 is described, described bottom 53 can adopt chemical vapour deposition technique to form, constitute by inorganic material such as amorphous carbon, but also can form following bottom 53, this bottom 53 can form by spin-coating method, is made of polymer that contains aromatic rings such as phenyl, naphthyl etc.
At this moment, in Fig. 1, on above machined layer 52, as the subsurface material that is rich in carbon that is used for multilayer resist method, promptly contain the polymer of aromatic rings such as phenyl, naphthyl, carry out about 200 ℃ to 250 ℃ hard roasting processing 1～2 minute with 100nm～300nm spin coating.
Thus, can form bottom 53, this bottom 53 is made of the macromolecular compound that contains aromatic compound such as phenyl ring, naphthalene nucleus or norborene (norboronene), adamantyl alicyclic compounds such as (adamantyl), is that the organic membrane that is rich in carbon more than the 75 weight % forms (bottom form operation end) by carbon content.Need to prove, be the organic membrane that is rich in carbon more than the 75 weight % by using carbon content, can guarantee the selection ratio with multiple machined layer 52.Thus, when etching machined layer 52, can form pattern well.
Then, on on bottom 53, thickness coating with 50～150nm is the intermediate layer material (the 1st intermediate layer material) of main component with bridging property silsesquioxane derivative and crosslinking agent, adopts about 200 ℃ to 250 ℃ 1～2 minute hard baking, and carries out hot curing and handles.Thus, form the 1st intermediate layer 54 (operation that forms in the 1st intermediate layer finishes) that forms by the polysilsesquioxane derivative.Need to prove that polysilsesquioxane (Polysilsesquioxane) is represented by following Chemical formula 1.In addition, R=H, C
2H
6, reactionlessness group etc.Also there is CH in phenyl moiety
3The situation that base or phenyl/methyl mixes.
[Chemical formula 1]
Then, on on the 1st intermediate layer 54, adopt poly-diphenyl silane of coating Osaka GasChemical (strain) system bridging property such as spin-coating method and epoxies cross-linked material propylene glycol monomethyl ether mixed solution as Thermocurable polysilane film (the 2nd intermediate layer material), making its thickness is 30～70nm, carries out the hot curing processing by 1～2 minute hard baking under about 200 ℃.Thus, form film formed the 2nd intermediate layer of representing by following Chemical formula 2 55 of polysilane.Need to prove,, also can use No. 3486123 communique of patent or the special material of putting down in writing in the 2001-93824 communique (the formation operation in the 2nd intermediate layer finishes) of opening as the Thermocurable polysilane film.
[Chemical formula 2]
In addition, can enumerate short-chain alkyls such as R=phenyl, methyl etc.Need to prove, when producing the pattern edge-curl phenomenon during inhibitory reflex rate or under chemical interaction fully, form anti-reflection layer 56 on as shown in Figure 2 also can be on the 2nd intermediate layer 55 by the 2nd intermediate layer 55.This anti-reflection layer 56 forms by the daily output chemistry system ARC83 that the thickness with about 40nm is coated with commercially available first minimum organic ARC.
Coating has photosensitive chemically amplified photo resist agent to ArF on anti-reflection layer 56, carries out baking processing (PAB) after the coating about 100 ℃, forms resist layer.
Then, above the resist layer that forms, the configuration mask.This mask (the 1st mask) is the mask that 2. waits record in the circuit pattern as ☆, and this mask is cut apart in the exposure of the double channel structure that is used for being made of minimum elimination width (for example 32nm Space) and its residual width of 3 times (96nm Line).
Next, use this mask, resist layer is carried out exposure-processed, under about 100 ℃ to 140 ℃, carry out the exposure after-baking (PEB) about 1 minute, carried out development treatment about 30 seconds～1 minute with 2.38% Tetramethylammonium hydroxide (TMAH) solution, after the development of carrying out under about 100 ℃ about 1 minute, bake, form corrosion-resisting pattern (the 1st corrosion-resisting pattern) 57.At this moment, as required, can use on the upper strata of resist and to open 2006-267521 communique, spy as the spy and open external protection (the formation operation of the 1st corrosion-resisting pattern finishes) on the resist of 2006-227632 communique record.
Then, as shown in Figure 3, be mask with corrosion-resisting pattern 57, make the 2nd intermediate layer 55 form pattern, on pattern transfer to the 2 intermediate layers 55 with corrosion-resisting pattern 57.At this moment, in the etching in the 2nd intermediate layer 55,, can use carbon fluoride gas (CF as halogen gas
4, CHF
3, CH
2F
2, CH
3F), chlorine (Cl
2), bromize hydrogen gas (HBr).Thus, form intermediate layer pattern 55a.
As mentioned above, when forming intermediate layer pattern 55a, pre-configured alignment mark.
In Fig. 4, adopt O
2Plasma treatment by ashing, is removed corrosion-resisting pattern 57 and anti-reflection layer 56.As required, also can and peel off with the wet type resist of sulfuric acid hydrogen peroxide etc.Thus, make intermediate layer pattern 55a to exposing outside.
As shown in Figure 5, for example as commercially available organic ARC, the ARC29 of coating daily output chemistry system second minimum organic ARC, make the about 80nm of thickness, form anti-reflection layer 60 thus, though described anti-reflection layer 60 is a film, can make the jump planarization that forms between the pattern 55a of intermediate layer, controls reflectivity simultaneously.
Then, this above anti-reflection layer 60 on, the coating ArF is had photosensitive chemically amplified photo resist agent, carry out baking processings (PAB) after the coating about 100 ℃, formation resist layer.
As mentioned above, above the resist layer that forms, the configuration mask is implemented exposure-processed.In this mask necessary circuitry pattern, 2. wait the mask of record, cut apart when eliminating the double channel exposure structure of width (for example 32nm Space) and its residual width of 3 times (96nm Line) formation being used for making by minimum by projection aligner as ☆.
As mentioned above, by resist layer is carried out exposure-processed, can form corrosion-resisting pattern 61.The slit 161 that forms in this corrosion-resisting pattern 61 is positioned on intermediate layer pattern 55a top.
Need to prove, when using mask to form corrosion-resisting pattern 61, as required, can be coated with the external protection of opening as the spy on 2006-267521 communique and the special resist of opening the record of 2006-227632 communique on the upper strata of resist layer.Herein, when disposing above-mentioned mask, intermediate layer pattern 55a that has formed and the position of mask relation must be configured with the precision of for example counting about nm.
Herein, on the 1st intermediate layer 54 that forms by the polysilsesquioxane derivative of silicon oxide film class on, form the above-mentioned intermediate layer pattern 55b that forms by polysilicon class polysilane film.Therefore, when forming intermediate layer pattern 55a shown in Figure 4, the aligned pattern irradiation broadband light to forming when detecting alignment mark with imaging devices such as CCD, can obtain the optical contrast of higher alignment mark.Thus, can make mask contraposition accurately, form pattern exactly.
Next, as shown in Figure 6, use this corrosion-resisting pattern 61, make intermediate layer pattern 55a form pattern, the pattern transfer of corrosion-resisting pattern 61 to the intermediate layer 55, is formed intermediate layer pattern 55b.Need to prove, can enumerate CF as fluorocarbons class gas
4, CHF
3, CH
2F
2, CH
3F also can use the mist of above-mentioned fluorocarbons class.
Herein, owing to slit 161 shown in Figure 5 is positioned on the pattern 55a of intermediate layer, so the intermediate layer pattern 55b that forms is than more miniaturization of intermediate layer pattern 55a.
Thus, can on the pattern 55b of intermediate layer, form the pattern of the fine repetition interval that is lower than " 0.25 ".
As shown in Figure 7, adopt O
2Plasma treatment by ashing, is removed corrosion-resisting pattern 61 and anti-reflection layer 60a.At this moment, as required, also can and peel off with the wet type resist of sulfuric acid hydrogen peroxide etc.As mentioned above, pattern 55b in intermediate layer is to exposing outside.
As shown in Figure 8, pattern 55b is a mask with the intermediate layer, makes the 1st intermediate layer 54 and bottom 53 form pattern, forms the 1st intermediate layer pattern 54a and bottom pattern 53a.At this moment, cut down naturally by film formed the 2nd intermediate layer pattern 55b of Thermocurable polysilane.
As shown in Figure 9, be mask with the 1st intermediate layer pattern 54a and the bottom pattern 53a that forms, make machined layer 52 form pattern, for example, can form the machined layer pattern 52a that process factor k1 is lower than the fine repetition interval of " 0.25 ".
The 1st intermediate layer pattern 54a that is formed by the polysilsesquioxane derivative cuts down when machined layer 52 forms pattern naturally, so do not need special operation.
Need to prove, also can on the amorphous carbon that CVD forms, form the subsurface material that is rich in carbon, (tetraethoxysilane: tetraethoxysilane) replacement bridging property silsesquioxane derivative, or silicon nitride film etc. are as multilayer film to use polysilicon to replace polysilane film, TEOS.
(execution mode 2)
Use Figure 10 to Figure 17, the manufacture method of the semiconductor device that present embodiment 2 relates to is described.Need to prove, for above-mentioned Fig. 1 to the identical or suitable structure of structure shown in Figure 9, give and identical symbol, omit its explanation.
Figure 10 is the profile of the 1st operation of the manufacture method of the semiconductor device that relates to of expression present embodiment 2.As shown in Figure 10, on the first type surface of Semiconductor substrate 1, form machined layer 22.
Next, this above machined layer 22 on, contain the polymer of aromatic rings such as phenyl, naphthyl as the subsurface material spin coating of being rich in carbon, making thickness is 100nm～300nm, carries out about 200 ℃ to 250 ℃ hard roasting processing 1～2 minute, forms bottom 23.
Then, this above bottom 23 on, AQUAMICA as polysilazane spin coating AZ ELECTRONICMATERIALS society, make in the heating plate of humidity about 35% through certain humidity control, hard roasting by about 250 ℃ to 300 ℃ 1～2 minute, the enforcement hot curing is handled, and burns till, and forms by hard SiO
2The 1st intermediate layer 24 that the 1st intermediate layer material constitutes, thickness is 50～10nm.
Need to prove that shown in (2), polysilazane and water reaction generate silica.
-(SiH
2NH)-+2H
2O→SiO
2+NH
3+2H
2 …(2)
By sending into air with humidity conditioner to heating plate, can realize humidity control from coating pan.
In addition, handle, make the hard SiO of polysilazane adopting hard baking about the hot curing of polysilazane
2Change when insufficient, in order to promote curing reaction, add the hot steam polysilazane is heated steam treatment 10sec～300sec is effective with about 200 ℃～450 ℃.
In addition, as the additive method that promotes curing reaction, washing processing with the aqueous solution of adding ultra-pure water or surfactant, afterwards, is effective to polysilazane heat treated 60sec～3600sec under about 150 ℃～350 ℃.
And then the additive method as promoting curing reaction washes processing with the insoluble water-containing organic solvent of separating polysilazane, afterwards, also is effective to polysilazane heat treated 60sec～3600sec under about 150 ℃～350 ℃.As used water-containing organic solvent, can select moisture content is 0.1～5% water-containing organic solvent, for example can select the long-chain alcohols, preferred isopropyl alcohol (Isopropyl alcohol), isobutanol (Iso Butanol) etc.
As mentioned above, be about the cured that 0.1～5% water-containing organic solvent carries out polysilazane, can make water distribution to the surface of polysilazane and the inside of polysilazane, promote the polysilazane curing reaction by using moisture content.
Herein, the moisture content of water-containing organic solvent is lower than at 0.1% o'clock, can not obtain being used for the necessary water of cured polysilazane.The moisture content of water-containing organic solvent is higher than at 5% o'clock, and remaining water increases after the polysilazane cured, is difficult in the dried after cured remove fully anhydrate, and may cause into the membrane stage variation.
Need to prove that undissolved water-containing organic solvent is meant, is benchmark with the surface area that impregnated in the polysilazane before the water-containing organic solvent, and the rate of change that impregnated in the surface area of the polysilazane behind the water-containing organic solvent is the state below 5%.
Then, poly-diphenyl silane of coating Osaka Gas Chemical (strain) system bridging property and epoxies cross-linked material propylene glycol monomethyl ether mixed solution are as the Thermocurable polysilane film, making thickness is 30～70nm, under about 200 ℃,, form the 2nd intermediate layer 25 by the hard roasting hot curing processing of carrying out in 1～2 minute.As the Thermocurable polysilane film, can use No. 3486123 communique of patent or the special material of putting down in writing in the 2001-93824 communique of opening.
Figure 11 is the profile of the 2nd operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment 2.In this Figure 11, in the time of can not controlling reflectivity fully by the 2nd intermediate layer 25, or when under the interaction of chemistry, producing the pattern edge-curl phenomenon, can be coated with the daily output chemistry system ARC83 of commercially available first minimum organic ARC in the above with the thickness of 40nm, form anti-reflection layer 26.
Thereon as resist, coating has photosensitive chemically amplified photo resist agent to ArF, after curing processing (PAB) after 100 ℃ the coating, use the 1st mask, carry out exposure-processed, described the 1st mask is in the necessary circuitry pattern, as the mask of records such as non-patent literature 2, when being used for the double structure that is made of the residual width of minimum (for example, 32nm Space) and its elimination width of 3 times (96nm Line) being exposed, cut apart by projection aligner.
About 1 minute of the after-baking (PEB) that exposes under about 100 ℃ to 140 ℃ was carried out development treatment about 30 seconds～1 minute with 2.38wt% tetrahydrochysene amine-oxides (TMAH) solution.After the development of carrying out under about 110 ℃ about 1 minute, bake, form corrosion-resisting pattern 57.At this moment, as required, can use on the upper strata of resist and to open 2006-267521 communique, spy as the spy and open external protection (formation of the 1st corrosion-resisting pattern finishes) on the resist of 2006-227632 communique record.
Figure 12 is the profile of the 3rd operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment 2.As shown in figure 12, as mask, etching is carried out in the 2nd intermediate layer 25, corrosion-resisting pattern is transferred on the 2nd intermediate layer 25 with corrosion-resisting pattern 27.Make fluorocarbons class gas, can enumerate CF
4, CHF
3, CH
2F
2, CH
3F also can use the mist class of above-mentioned fluorocarbons class.Thus, form the 2nd intermediate layer pattern 25a.
Figure 13 is the profile of the 4th operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment 2.Figure 32 is the plane graph of the 4th operation for this reason.As Figure 13 and shown in Figure 32, adopt O
2Plasma treatment by ashing, is removed corrosion-resisting pattern 27 and anti-reflection layer 26.In case of necessity, also can and peel off with the wet type resist of sulfuric acid hydrogen peroxide etc.Thus, make the 2nd intermediate layer pattern 25a to exposing outside.
Figure 14 is the profile of the 5th operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment 2.As shown in figure 14, as commercially available organic ARC, the ARC29 of coating daily output chemistry system second minimum organic ARC makes the about 110nm of thickness, forms anti-reflection layer 30 thus.By formation anti-reflection layer 30, though be film, but still can imbed the jump of the 2nd intermediate layer pattern 55a with anti-reflection layer 30, make its planarization, control reflectivity simultaneously.
Coating has photosensitive chemically amplified photo resist agent to ArF on this anti-reflection layer 30, carries out baking processing (PAB) after the coating about 100 ℃, forms resist layer.
Then, use following mask (the 3rd mask), resist layer is carried out exposure-processed, described mask is in the necessary circuitry pattern, as the mask of records such as non-patent literature 2, when the double structure exposure that is used for constituting, cut apart by the residual width of minimum (for example, 32nm Space) and its elimination width of 3 times (96nm Line).
Under about 100 ℃ to 140 ℃, expose after-baking (PEB) about 1 minute, carried out development treatment about 30 seconds～1 minute with 2.38wt% tetrahydrochysene amine-oxides (TMAH) solution.After the development of carrying out under about 110 ℃ about 1 minute, bake, form corrosion-resisting pattern 31.
At this moment, as required,, can use also that the spy opens the 2006-267521 communique, the spy opens the external protection on the resist of putting down in writing in the 2006-227632 communique on the upper strata of resist.
Herein, the corrosion-resisting pattern 31 of formation is positioned at the top in the slit 125 of the 2nd intermediate layer pattern 25a.In other words, on the intermediate layer 24 in the slit 125 that is positioned at the 2nd intermediate layer pattern 25a.
Figure 15 is the profile of the 6th operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment 2.Figure 33 is the plane graph of the 6th operation for this reason.As Figure 15 and shown in Figure 33, as mask,, form the 1st intermediate layer pattern 24a by forming pattern through burning till on film formed the 1st intermediate layer 24 of hard SiO2 that polysilazane obtains with corrosion-resisting pattern 31 and the 2nd intermediate layer pattern 25a.
As fluorocarbons class gas, can enumerate CF
4, CHF
3, CH
2F
2, CH
3F also can use the mist class that adds oxygen or nitrogen in the mist class of above-mentioned fluorocarbons class or the fluorocarbons class gas.
As mentioned above, by making the 1st intermediate layer 24 form pattern, can form the 1st intermediate layer pattern 24a, the pattern of fine repetition interval less, that for example be lower than " 0.25 " forms described the 1st intermediate layer pattern 24a by compare at interval with the 2nd intermediate layer pattern 25a.
Need to prove, form the 1st intermediate layer pattern 24a of anti-reflection layer 30a in the above and form the 1st intermediate layer pattern 24a alternate configurations of the 2nd intermediate layer pattern 25a in the above.
Figure 16 is the profile of the 7th operation of the manufacturing process of the semiconductor device that relates to of expression present embodiment 2.Among this Figure 16, under the residual state of the 2nd intermediate layer pattern 25a that on the 1st intermediate layer pattern 24a shown in Figure 15, forms and anti-reflection layer 30a, make bottom 23 form patterns, form bottom pattern 23a.
Thus, form the bottom pattern 23a of minuteness space as shown in figure 16.The situation that forms the situation of the 1st intermediate layer pattern 24a and the 2nd intermediate layer pattern 25a on this bottom pattern 23a and only form the 1st intermediate layer pattern 24a above it alternately occurs.
The machined layer 22 that must in the end process, apparatus structure is necessary is a mask with this bottom pattern 23a that is rich in carbon, can the multiple film of etching.In addition, can cut down naturally when machined layer 22 etchings, therefore do not need to remove especially operation by film formed the 1st intermediate layer pattern 24a of polysilazane with by film formed the 2nd intermediate layer pattern 25a of polysilane.Need to prove that the manufacture method of the semiconductor device that present embodiment 2 relates to (two-wire system) preferably is applicable to grid (Gate) operation that forms residual distribution.
＜variation 1 〉
Need to prove, in present embodiment 2, form the 1st intermediate layer 24, form the 2nd intermediate layer 25 by polysilazanes film, but be not limited thereto by polysilane film.
For example, also can form the 1st intermediate layer 24, form the 2nd intermediate layer 25 by polysilane film by polysilazanes film.
The hard SiO that polysilazanes film obtains is handled in hot curing
2, with respect to Si by polysilane or polysilsesquioxane etc. and so on
XO
YC
ZThe material that (X, Y, Z are arbitrary integer), protium and the element that comprises inevitably form has bigger selection ratio.Therefore, in the 1st intermediate layer 24 and the 2nd intermediate layer 25 handles the hard SiO that polysilazane obtains by hot curing
2Form.Another one is formed by following material, and described material contains the Si of polysilane or polysilsesquioxane etc. and so on
XO
YC
Z(X, Y, Z are arbitrary integer), protium and the element that comprises inevitably.For example, when using bromize hydrogen gas (HBr) class gas, be benchmark with the polysilsesquioxane as etching gas, the hard SiO that polysilazane obtains is handled in hot curing
2The selection ratio be about about 0.1231, the selection ratio of polysilane is about about 1.005.And then, use C as etching gas
4F
5During/argon gas, be benchmark with the polysilsesquioxane, the hard SiO that polysilazane obtains is handled in hot curing
2The selection ratio be 9.1532, the selection ratio of polysilane is about about 0.232.As mentioned above, the hard SiO that polysilazane obtains is handled in hot curing
2, with respect to Si by polysilane or polysilsesquioxane etc. and so on
XO
YC
ZThe material that (X, Y, Z are arbitrary integer), protium and the element that comprises inevitably form can guarantee to be at least the bigger selection ratio more than 3.
Figure 17 is the profile of operation after the manufacturing process of the above-mentioned semiconductor device shown in Figure 15 of expression.In Figure 17, bottom 23 is formed before the patterns, remove rare fluoric acid or fluorocarbons class gas by dry type, can optionally only remove anti-reflection layer 30a shown in Figure 15 or by film formed the 2nd intermediate layer pattern 25a of polysilazane.Then, make by film formed the 1st intermediate layer pattern 24a of polysilane and expose.
Figure 18 is the profile of the operation after the expression operation shown in Figure 17.As shown in figure 18, under the state of residual the 1st intermediate layer pattern 24a only, make bottom 23 form patterns, form bottom pattern 23a.Need to prove that bottom 23 is formed by organic membrane, therefore, when producing undesirable condition, adopt simple processing promptly can form bottom 23 once more by Regeneration Treatment.
＜variation 2 〉
Use Figure 19 to Figure 27, the 2nd variation of the semiconductor device that present embodiment 2 relates to is described.
Figure 19 is the profile of the 1st operation of the manufacturing process of the semiconductor device of expression the 2nd variation.As shown in figure 19, on the first type surface of Semiconductor substrate 1, form machined layer 82.Then, this above machined layer 22 on, be identically formed the bottom 83 that forms by the subsurface material that is rich in carbon with above-mentioned operation shown in Figure 10 and the 1st intermediate layer 84 that forms by polysilazane and by film formed the 2nd intermediate layer 85 of polysilane.
Then, on this 2nd intermediate layer 85, form the 3rd intermediate layer 86 that is identically formed with the 1st intermediate layer 84 again.
Particularly, on on the 2nd intermediate layer 85, AQUAMICA as polysilazane spin coating AZELECTRONIC MATERIALS society, make in the heating plate of humidity about 35% through certain humidity control, hard roasting by about 250 ℃ to 300 ℃ 1～2 minute, the enforcement hot curing is handled, and burns till, and forms by hard SiO
2The 3rd intermediate layer 86 that forms of the 1st intermediate layer material, thickness 50～100nm.
Figure 20 is the profile of the operation after the manufacturing process shown in Figure 19.As shown in figure 20, form anti-reflection layer 87, form resist layer on above the anti-reflection layer 87 at this.
Then, at this configuration mask above resist layer.This mask as ☆ 2. shown in, cut apart when the exposure of the double structure that is used for constituting by the residual width of minimum (for example, 32nm Space) and its elimination width of 3 times (96nm Line).
Then, use this mask, resist layer is implemented exposure-processed, form corrosion-resisting pattern 88.
Figure 21 is the profile of the operation after the manufacturing process shown in Figure 20.As shown in figure 21, use the corrosion-resisting pattern 88 that forms, make the 3rd intermediate layer 86 form pattern, form the 3rd intermediate layer pattern 86a as mask.
Figure 22 is the profile of the operation after the manufacturing process shown in Figure 21.As shown in figure 22, remove corrosion-resisting pattern 88 and anti-reflection layer 87a.Thus, make the 3rd intermediate layer pattern 86a of formation to exposing outside.
Figure 23 is the profile of the operation after the manufacturing process shown in Figure 22.As shown in figure 23, on the 3rd intermediate layer pattern 86a, form anti-reflection layer 90.Thus, imbed slit between the 3rd intermediate layer pattern 86a.Need to prove that the selection ratio of the 3rd intermediate layer 86 with respect to the 2nd intermediate layer 85 compared, reached in the 2nd intermediate layer 85 with respect to the selection in the 3rd intermediate layer 86, for example all more than 2.Therefore, the 3rd intermediate layer 86 can become film.So, when on the 3rd intermediate layer pattern 86a, forming anti-reflection layer 90, can suppress to produce and the very big part of anti-reflection layer 90 inclinations.Then, this above anti-reflection layer 90 with the planar formation resist layer of general planar.
Next, dispose mask above the resist layer that forms, the exposure resist layer forms corrosion-resisting pattern 91.This corrosion-resisting pattern 91 is positioned at the top in the slit of the 3rd intermediate layer pattern 86a.
Figure 24 is the profile of the operation after the manufacturing process shown in Figure 23.As shown in figure 24, be mask with corrosion-resisting pattern shown in Figure 23 91 and the 3rd intermediate layer pattern 86a, make the 2nd intermediate layer 85 form pattern.
As mentioned above, form pattern by making the 2nd intermediate layer 85, the pattern that forms can be transferred to respectively on the 3rd intermediate layer pattern 86a and the corrosion-resisting pattern 91, formation can form the 2nd intermediate layer pattern 85a of fine pattern.
This 2nd intermediate layer pattern 85a, the pattern that anti-reflection layer 90a forms above it and, the 3rd intermediate layer pattern 86a forms above it pattern alternate configurations.At this moment, the 1st intermediate layer 84 is as the protective layer performance function of bottom 83.
Figure 25 is the profile of the operation after the expression manufacturing process shown in Figure 24.As shown in figure 25, as mask, make the 1st intermediate layer 84 form pattern with the 2nd intermediate layer pattern 85a.Thus, form the 1st intermediate layer pattern 84a.At this moment, bottom 83 is as the diaphragm performance function of protection machined layer 82.
Figure 26 is the profile of the operation after the expression manufacturing process shown in Figure 25.As shown in figure 26, as mask, make bottom 83 form pattern, form bottom pattern 83 with the 1st intermediate layer pattern 84a.
Figure 27 is the profile of the operation after the expression operation shown in Figure 26.As shown in figure 27, be mask with the bottom pattern 83 that forms, make machined layer 82 form pattern, can obtain grid fine pattern 82a such as (gate).
As mentioned above, on bottom 83, make the lamination intermediate layer that constitutes by the multilayer intermediate layer form pattern, form this lamination intermediate layer pattern, use this lamination intermediate layer, make bottom form pattern, form the bottom pattern, make machined layer form pattern, can form fine pattern.Need to prove that the manufacture method by semiconductor device that present embodiment 1,2 is related to is used for separation circuit, grid operation, contact operation, distribution operation, via operation successively, can make the semiconductor device with fine pattern.
As mentioned above, embodiments of the present invention are illustrated, this disclosed execution mode has carried out illustration in all directions, but is not limited thereto.Scope of the present invention shown in claim, comprises the meaning that is equal to claim and all changes in the scope.And above-mentioned numerical value etc. are illustration just, is not limited to above-mentioned numerical value and scope.
Understood the present invention in detail, but above-mentioned just being used to illustrate, be not limited thereto, scope of invention should be expressly understood to be the content of being set forth by claim.
Claims (35)
1. the manufacture method of a semiconductor device, described manufacture method comprises following operation:
On the first type surface of Semiconductor substrate, form the operation of machined layer;
On described machined layer, form the operation of bottom;
On described bottom, form the operation in the 1st intermediate layer and the 2nd intermediate layer successively;
Under the state that covers described machined layer with described bottom, make described the 2nd intermediate layer form the operation of pattern;
On described the 2nd intermediate layer of described formation pattern, form the operation of the 1st mask pattern;
Use described the 1st mask pattern, make described the 2nd intermediate layer form the operation of pattern;
Use the 2nd intermediate layer of described formation pattern, make described the 1st intermediate layer and described bottom form pattern, form the operation of the 2nd mask pattern;
Use described the 2nd mask pattern, make described machined layer form the operation of pattern.
2. the manufacture method of semiconductor device as claimed in claim 1, wherein, be benchmark, described the 2nd intermediate layer with respect to the selection in described the 1st intermediate layer with described the 1st intermediate layer being benchmark, described the 1st intermediate layer selection ratio with respect to described the 2nd intermediate layer with described the 2nd intermediate layer when, and is that benchmark, described machined layer are more less than comparing with respect to the selection of described bottom with the bottom.
3. the manufacture method of semiconductor device as claimed in claim 1, wherein, described the 1st intermediate layer is a silicon oxide layer, described the 2nd intermediate layer is the polysilane layer.
4. the manufacture method of semiconductor device as claimed in claim 1, wherein, described the 1st intermediate layer is polysilsesquioxane derivative layer or polysilazane layer.
5. the manufacture method of semiconductor device as claimed in claim 1, wherein, described the 1st intermediate layer is the polysilane layer, described the 2nd intermediate layer is the polysilazane layer.
6. the manufacture method of semiconductor device as claimed in claim 1, wherein, described the 1st intermediate layer and described the 2nd intermediate layer are formed by the filmogen that can adopt chemical vapour deposition technique to form.
7. the manufacture method of semiconductor device as claimed in claim 1, wherein, described the 1st intermediate layer and described the 2nd intermediate layer are formed by the filmogen that can adopt spin-coating method to form.
8. the manufacture method of semiconductor device as claimed in claim 1, wherein, described bottom is an organic layer.
9. the manufacture method of semiconductor device as claimed in claim 8, wherein, the carbon content of described organic layer is more than the 75 weight %.
10. the manufacture method of semiconductor device as claimed in claim 1, wherein, described bottom is formed by the inorganic material that can adopt chemical vapour deposition technique to form.
11. the manufacture method of semiconductor device as claimed in claim 10, wherein, described bottom is an amorphous carbon.
12. the manufacture method of semiconductor device as claimed in claim 1 wherein, forms the operation in described the 1st intermediate layer and described the 2nd intermediate layer, comprises to form the operation of polysilazane layer as described the 1st intermediate layer or described the 2nd intermediate layer.
13. the manufacture method of semiconductor device as claimed in claim 1, wherein, one in described the 1st intermediate layer and described the 2nd intermediate layer is the polysilazane layer, another in described the 1st intermediate layer and described the 2nd intermediate layer for respect in described bottom and the described polysilazane layer any mutually mutual election then than be 3 or more layer.
14. the manufacture method of semiconductor device as claimed in claim 1, wherein, one in described the 1st intermediate layer and described the 2nd intermediate layer is the polysilazane layer, and another in described the 1st intermediate layer and described the 2nd intermediate layer is polysilane layer or polysilsesquioxane layer.
15. the manufacture method of semiconductor device as claimed in claim 12 wherein, also comprises to use and adds the hot steam and make described polysilazane layer be cured the operation of reaction.
16. the manufacture method of semiconductor device as claimed in claim 12, wherein, also comprise and use the aqueous solution, the flushing that add pure water or surfactant to handle the operation of described polysilazane layer and make described polysilazane layer be cured the operation of reaction by heat treated.
17. the manufacture method of semiconductor device as claimed in claim 12 wherein, also comprises water-containing organic solvent that use do not make the dissolving of described polysilazane layer and washes the operation of processing and make the polysilazane layer be cured the operation of reaction by heat treated,
The moisture content of described water-containing organic solvent is more than 0.1% below 5%.
18. the manufacture method of a semiconductor device, described manufacture method comprises following operation:
On the first type surface of Semiconductor substrate, form the operation of machined layer;
The operation of formation bottom on described machined layer;
The operation in the lamination intermediate layer that formation is formed by the multilayer intermediate layer on described bottom;
Pattern is implemented repeatedly in described lamination intermediate layer formed, form the operation of lamination patterned layer;
With described lamination pattern layer is mask, and described bottom and described machined layer are carried out etched operation.
19. the manufacture method of a semiconductor device, described manufacture method comprises following operation:
On the first type surface of Semiconductor substrate, form the operation of machined layer;
On described machined layer, form the operation of bottom;
On described bottom, form the operation in the 1st intermediate layer and the 2nd intermediate layer successively;
Covering under the state of described machined layer with described bottom, making described the 2nd intermediate layer form the operation of pattern;
On described the 1st intermediate layer that is positioned between described the 2nd intermediate layer of described formation pattern, form the operation of the 1st mask pattern;
Use described the 2nd intermediate layer of described the 1st mask pattern and described formation pattern, make described the 1st intermediate layer form the operation of pattern;
Use described the 1st intermediate layer of described formation pattern, make described bottom form pattern, form the operation of the 2nd mask pattern;
Use described the 2nd mask pattern, make described machined layer form the operation of pattern.
20. the manufacture method of semiconductor device as claimed in claim 19, wherein, with described the 1st intermediate layer is benchmark, described the 2nd intermediate layer selection ratio with respect to described the 1st intermediate layer, and be benchmark, described the 1st intermediate layer selection ratio with respect to described the 2nd intermediate layer with described the 2nd intermediate layer, and be that benchmark, described machined layer are more less than comparing with respect to the selection of described bottom with the bottom.
21. the manufacture method of semiconductor device as claimed in claim 19, wherein, described the 1st intermediate layer is a silicon oxide layer, and described the 2nd intermediate layer is the polysilane layer.
22. the manufacture method of semiconductor device as claimed in claim 19, wherein, described the 1st intermediate layer is polysilsesquioxane derivative layer or polysilazane layer.
23. the manufacture method of semiconductor device as claimed in claim 19, wherein, described the 1st intermediate layer is the polysilane layer, and described the 2nd intermediate layer is the polysilazane layer.
24. the manufacture method of semiconductor device as claimed in claim 19, wherein, described the 1st intermediate layer and described the 2nd intermediate layer are formed by the filmogen that can adopt chemical vapour deposition technique to form.
25. the manufacture method of semiconductor device as claimed in claim 19, wherein, described the 1st intermediate layer and described the 2nd intermediate layer are formed by the filmogen that can adopt spin-coating method to form.
26. the manufacture method of semiconductor device as claimed in claim 19, wherein, described bottom is an organic layer.
27. the manufacture method of semiconductor device as claimed in claim 26, wherein, the carbon content of described organic layer is more than the 75 weight %.
28. the manufacture method of semiconductor device as claimed in claim 19, wherein, described bottom is formed by the inorganic material that can adopt chemical vapour deposition technique to form.
29. the manufacture method of semiconductor device as claimed in claim 28, wherein, described bottom is an amorphous carbon.
30. the manufacture method of semiconductor device as claimed in claim 19 wherein, forms the operation in described the 1st intermediate layer and described the 2nd intermediate layer, comprises to form the operation of polysilazane layer as described the 1st intermediate layer or described the 2nd intermediate layer.
31. the manufacture method of semiconductor device as claimed in claim 19, wherein, one in described the 1st intermediate layer and described the 2nd intermediate layer is the polysilazane layer, another in described the 1st intermediate layer and described the 2nd intermediate layer for select mutually with respect in described bottom and the described polysilazane layer any than be 3 or more layer.
32. the manufacture method of semiconductor device as claimed in claim 19, wherein, one in described the 1st intermediate layer and described the 2nd intermediate layer is the polysilazane layer, and another in described the 1st intermediate layer and described the 2nd intermediate layer is polysilane layer or polysilsesquioxane layer.
33. the manufacture method of semiconductor device as claimed in claim 30 wherein, also comprises use and adds the hot steam, makes described polysilazane layer be cured the operation of reaction.
34. the manufacture method of semiconductor device as claimed in claim 30, wherein, also comprise and use the aqueous solution, the flushing that add pure water or surfactant to handle the operation of described polysilazane layer and make described polysilazane layer be cured the operation of reaction by heat treated.
35. the manufacture method of semiconductor device as claimed in claim 30 wherein, also comprises water-containing organic solvent that use do not make the dissolving of described polysilazane layer and washes the operation of processing and make the polysilazane layer be cured the operation of reaction by heat treated,
The moisture content of described water-containing organic solvent is more than 0.1% below 5%.
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| JP2007033779 | 2007-02-14 | ||
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| CN101246816A true CN101246816A (en) | 2008-08-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107168010A (en) * | 2016-03-08 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of lithography mask version |
| CN108155100A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
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| JP4927678B2 (en) * | 2007-03-13 | 2012-05-09 | パナソニック株式会社 | Pattern formation method |
| WO2009054413A1 (en) * | 2007-10-25 | 2009-04-30 | Nissan Chemical Industries, Ltd. | Semiconductor device manufacturing method |
| JP5390764B2 (en) * | 2007-12-28 | 2014-01-15 | 東京エレクトロン株式会社 | Resist pattern forming method, residual film removal processing system, and recording medium |
| JP5990367B2 (en) * | 2011-06-17 | 2016-09-14 | 富士フイルム株式会社 | Pattern forming method and electronic device manufacturing method using the same |
| JP6047039B2 (en) | 2012-04-20 | 2016-12-21 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing method, substrate processing apparatus, and program |
| CN103255416B (en) * | 2013-05-14 | 2015-08-12 | 广东工业大学 | A kind of engraving method and etch-polish liquid used thereof |
| KR102067082B1 (en) | 2017-01-19 | 2020-01-16 | 삼성에스디아이 주식회사 | Method of forming patterns, and semiconductor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2803999B2 (en) * | 1993-11-10 | 1998-09-24 | 現代電子産業株式会社 | Method for manufacturing fine pattern of semiconductor device |
| KR100223325B1 (en) * | 1995-12-15 | 1999-10-15 | 김영환 | Method for manufacturing fine pattern of semiconductor device |
| JP3978852B2 (en) * | 1998-02-27 | 2007-09-19 | ソニー株式会社 | Manufacturing method of semiconductor device |
| JP2002343767A (en) * | 2001-05-14 | 2002-11-29 | Toshiba Corp | Pattern forming method |
| US7064078B2 (en) * | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
| JP2006085029A (en) * | 2004-09-17 | 2006-03-30 | Az Electronic Materials Kk | Method for forming pattern using photosensitive polysilazane film |
| JP4662052B2 (en) * | 2005-03-11 | 2011-03-30 | 信越化学工業株式会社 | Photoresist underlayer film forming material and pattern forming method |
| US20070018286A1 (en) * | 2005-07-14 | 2007-01-25 | Asml Netherlands B.V. | Substrate, lithographic multiple exposure method, machine readable medium |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107168010A (en) * | 2016-03-08 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of lithography mask version |
| CN107168010B (en) * | 2016-03-08 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing photoetching mask |
| CN108155100A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN108155100B (en) * | 2016-12-02 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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