CN101241908A - A static discharging protection method and circuit - Google Patents
A static discharging protection method and circuit Download PDFInfo
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- CN101241908A CN101241908A CNA2007100075525A CN200710007552A CN101241908A CN 101241908 A CN101241908 A CN 101241908A CN A2007100075525 A CNA2007100075525 A CN A2007100075525A CN 200710007552 A CN200710007552 A CN 200710007552A CN 101241908 A CN101241908 A CN 101241908A
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Abstract
The invention relates to an electrostatic discharge (ESD) protection method and circuit, it utilizes the principle that the gate electrode of the n-channel metal-oxide-semiconductor field effect transistor (NMOS) of the field may open the electronics channel for channeling a large amount of the electrostatic current when it suffers high electrostatic pressure so as to effectively protect any ESD event out of the scope of the operation voltage. Improving the conventional p-channel metal-oxide-semiconductor field effect transistor (PMOS) only can protect the limit of the operation voltage of the input/output end (I/O) which is less than supply voltage VDD. Moreover, due to the scope of the operating voltage is very wide, it can be directly used between the output end of the open drain and the supply voltage VDD without two-phase electrostatic discharge protection of VSS so as to save much space and be safer; Simultaneously, also being different from that the punch through current is the floating-gate field NMOS of the electrostatic discharge protection, the invention can clearly set the trigger voltage of the electrostatic discharge protection (i.e. the threshold voltage produced by the electronics channel) so as to make the electrostatic discharge protection to be safer.
Description
Technical field
(electrostatic discharge, ESD) the relevant technology of protection is specially adapted to out drain output (open drain output) and supply voltage V to the present invention relates to static discharge in a kind of and the semiconductor industry
DDBetween ESD protection circuit.
Background technology
In the semiconductor industry, from integrated circuit (IC) and even manufacturing, encapsulation system assembling in addition after product is finished, integrated circuit all is difficult to be exposed in the environment of static discharge threat with avoiding, comprise artificial use (human body model in the middle of this, HBM), machine discharge (machine model, MM), assembly discharge (charge-devicemodel, CDM) with electromagnetic wave induction (field-induced model, FIM), all can produce the electrostatic pressure of wanting several thousand times of high hundreds ofs than the own operating voltage of integrated circuit (operation voltage).High electrostatic pressure like this can produce great electrostatic current in the moment of discharge and burn internal circuit; for this reason; shown in Figure 1A; between main internal circuit 110 external links, must to make electrostatic discharge (ESD) protection (ESD protection); to guarantee that when electrostatic discharge event (ESDevent) takes place this static discharge current can not cause damage through this main internal circuit.For instance, if an internal circuit 110 its three links are externally arranged: one for mainly providing the power voltage terminal V of power supply
DDTwo is low-voltage end V
SS(V
SSThe V that compares
DDBe relatively low pressure, be generally earthed voltage); And the 3rd be input/output terminal I/O.If no electrostatic discharge (ESD) protection, this static discharge current just can be flowed through this internal circuit extremely than cold end thereby cause this internal circuit to burn when electrostatic discharge event takes place.So-called electrostatic discharge (ESD) protection is to outer end and its low-voltage end V at each this internal circuit
SSMake a short circuit (short) circuit 120 between (being generally earth terminal), 130, the not conducting under normal working voltage (normal operation voltage) of this short circuit current and when taking place, static discharge is short-circuited with this static discharge current of rapid conducting keeping normal operation.
Traditionally, need the characteristic of conducting during high electrostatic pressure in order to keep not conducting under the normal working voltage, normally utilize diode or PNP to connect reverse bias (reverse bias) characteristic of face, only penetrate breakdown voltage (punch through voltage) Shi Caihui greater than it and penetrate collapse (punch through) shunting static discharge current at reverse bias; Or the operating voltage of utilizing this input/output terminal I/O is forever less than supply voltage V
DDCharacteristic, use p passage metal-oxide half field effect transistor (p-channel metal-oxide-semiconductor field effect transistor, PMOS) 241 bear the electric hole passages of opening under the gate voltage, shunting operating voltage and the supply voltage V of this input/output terminal I/O
DDBetween static discharge current (ginseng Figure 1B).
Yet; the mode that use penetrates collapse is for example: diode string (diode string) or float gate place metal-oxide half field effect transistor (floating-gate field n-channel metal-oxide-semiconductor field effecttransistor; floating-gate field NMOS) 242 does electrostatic discharge (ESD) protection 140 (ginseng Fig. 1 C); can not definitely grasp the magnitude of voltage that it penetrates when collapse; all can influence the magnitude of voltage that penetrates the collapse generation because impurity ratio and PN connect smooth rate of face or the like in the semiconductor production; can not ensure that so, just this electrostatic discharge (ESD) protection can normal operation in known operating voltage range.Though and the PMOS electrostatic discharge (ESD) protection 241 that adopts negative gate voltage to start can be grasped the operating voltage range of its protection, but can only protective ratio supply voltage V
DDThe electrostatic discharge event that little input/output terminal operating voltage is outer.
Summary of the invention
A purpose of the present invention provides a kind of electrostatic discharge protection method and circuit, to solve in the conventional electrostatic discharge protection circuit, and can only protective ratio supply voltage V
DDElectrostatic discharge event that little input/output terminal operating voltage is outer and the restriction that can not grasp the magnitude of voltage that penetrates the avalanche generation.
Another object of the present invention provides a kind of electrostatic discharge protection method and circuit; the electrostatic discharge (ESD) protection of opening drain output (open drain output) pin (pin) that often need in the semiconductor subassembly to be specially adapted to; make its pin can connect different lifting resistance (pull-up resister) changing different output voltages, and the operating voltage that makes this switch pole is unlike the supply voltage V of other input/output terminal I/O than this internal circuit
DDLittle.
For achieving the above object; electrostatic discharge protection method of the present invention; it is the voltage difference of utilizing when electrostatic discharge event takes place; make a place n passage metal-oxide half field effect transistor (field n-channel metal-oxide-semiconductorfield effect transistor; field NMOS) (inversion) reverses in gate (gate) place oxide layer (field oxide layer) below exhaustion region (depletion); electronics channel (n channel) the shunting static discharge current (ESD current) that sees through the counter-rotating generation reaches the purpose of electrostatic discharge (ESD) protection to avoid the path of internal circuit.
One embodiment of the present invention provides a kind of unidirectional (one-directional) ESD protection circuit; be provided with a place of conducting n passage metal-oxide half field effect transistor when static discharge takes place; make unidirectional static discharge current be shunted the path of avoiding internal circuit, reach the purpose (ginseng Fig. 3 A) of electrostatic discharge (ESD) protection.
Another embodiment of the present invention provides a kind of two-way (two-directional) ESD protection circuit; be provided with one of them place n passage metal-oxide half field effect transistor of conducting when static discharge takes place; make the bidirectional ESD electric current all be shunted the path of avoiding internal circuit, reach the purpose (ginseng Fig. 3 B) of electrostatic discharge (ESD) protection.
For the above-mentioned content of the present invention, purpose, advantage and further feature can be become apparent, below cooperate graphic and preferred embodiment detailed description the present invention.
Description of drawings
Figure 1A is a schematic diagram of commonly using ESD protection circuit and internal circuit correlation.
Figure 1B is for commonly using the schematic diagram of p passage metal-oxide half field effect transistor (PMOS) ESD protection circuit and internal circuit correlation.
Fig. 1 C is for commonly using the schematic diagram of float gate place n passage metal-oxide half field effect transistor (floating-gate field NMOS) ESD protection circuit and internal circuit correlation.
Fig. 2 A forms the schematic diagram of electronics channel for place n passage metal-oxide half field effect transistor (field NMOS) place oxide layer below among the present invention.
Fig. 2 B is the schematic diagram of compound crystal silicon gate place n passage metal-oxide half field effect transistor (poly-gate fieldNMOS) ESD protection circuit among the present invention and internal circuit correlation.
Fig. 3 A is the schematic diagram of unidirectional (one-directional) ESD protection circuit among the present invention and internal circuit correlation.
Fig. 3 B is the schematic diagram of two-way (two-directional) ESD protection circuit among the present invention and internal circuit correlation.
Fig. 4 A is layout (layout) embodiment one vertical view of unidirectional (one-directional) ESD protection circuit among the present invention.
Fig. 4 B is along the online sectional schematic diagram of a-a among Fig. 4 A.
Fig. 4 C is along the online sectional schematic diagram of b-b among Fig. 4 A.
Fig. 5 A is layout (layout) embodiment one vertical view of two-way (two-directional) ESD protection circuit among the present invention.
Fig. 5 B is along the online sectional schematic diagram of c-c among Fig. 5 A.
Primary clustering symbol description: 110-internal circuit; 120-V
DDTo V
SSESD protection circuit; 130-I/O is to V
SSESD protection circuit; 140-I/O is to V
DDESD protection circuit; V
DD-supply voltage; The I/O-input/output terminal; V
SS-low-voltage end (V
SSThe V of ratio
DDBe relatively low pressure, be generally earthed voltage); Static discharge current on the ESD shunting-ESD protection circuit; The source electrode (source) of 150-place n passage metal-oxide half field effect transistor (fieldNMOS); The gate (gate) of 151-place n passage metal-oxide half field effect transistor (field NMOS); The drain (drain) of 152-place n passage metal-oxide half field effect transistor (field NMOS); The electronics channel of 153-place n passage metal-oxide half field effect transistor (field NMOS); P
1-the first static discharge end; P
2-the second static discharge end; 241-p passage metal-oxide half field effect transistor (PMOS) ESD protection circuit; 242-float gate place n passage metal-oxide half field effect transistor (floating-gate field NMOS) ESD protection circuit; 243-compound crystal silicon gate place n passage metal-oxide half field effect transistor (poly-gate field NMOS) ESD protection circuit; The 310-first place n passage metal-oxide half field effect transistor (field NMOS); The 320-second place n passage metal-oxide half field effect transistor (field NMOS); 410-compound crystal silicon gate (poly-gate); 420-place oxide layer (field oxidelayer); 440-opens drain output (open drain output); A-a-layout sectional drawing is along the position of a-a tangent plane in vertical view; B-b-layout sectional drawing is along the position of b-b tangent plane in vertical view; C-c-layout sectional drawing is along the position of c-c tangent plane in vertical view.
Embodiment
The embodiment of electrostatic discharge protection method of the present invention such as Fig. 2 A, influence and infringement when being provided with protecting an internal circuit 110 not to be subjected to static discharge may further comprise the steps: (a) see through one first static discharge end P
1, the static discharge current during with this internal circuit generation electrostatic discharge event imports; (b) sees through one second static discharge end P again
2, the static discharge current during with this internal circuit generation electrostatic discharge event flows out; Simultaneously, when (c) utilizing this internal circuit generation electrostatic discharge event, this first static discharge end P
1With this second static discharge end P
2Between voltage difference, make one the one n passage metal-oxide half field effect transistor 1
StThe gate of NMOS (gate) 151 oxide layers (oxide layer) below exhaustion regions (depletion) reverse (inversion) to produce electronics channel (n channel) 153, are provided with this first static discharge end P
1The static discharge current that imports is able to rapidly by this second static discharge end P
2Flow out, reach the purpose of electrostatic discharge (ESD) protection.
Embodiment such as Fig. 3 A of unidirectional (one-directional) of the present invention ESD protection circuit are provided with protecting an internal circuit 110 not to be subjected to the influence and the infringement of unidirectional static discharge current, comprising: (a) one first static discharge end P
1, static discharge current and its voltage when being provided with importing this internal circuit generation electrostatic discharge event are V
1(b) one second static discharge end P
2, static discharge current and its voltage when being provided with flowing out this internal circuit generation electrostatic discharge event are V
2And (c) one the one n passage metal-oxide half field effect transistor 1st NMOS 310, its gate connects this first static discharge end P
1, and its drain (drain) is connected this first static discharge end P respectively with source electrode (source)
1With this second static discharge end P
2, be provided with this first static discharge end P when this internal circuit generation electrostatic discharge event
1To this second static discharge end P
2Static discharge potential difference (V during more than or equal to its gate critical voltage
1-V
2〉=V
Th, V
ThBe its gate critical voltage), draw at it and to form short circuit (short) between source electrode, make path shunting (shunt) that static discharge current avoids this internal circuit draw short circuit between source electrode to form electrostatic discharge (ESD) protection to it.Yet, under operate as normal (normal operation) voltage, this first static discharge end P
1With this second static discharge end P
2Between voltage difference (V
1-V
2) be less than gate critical voltage V
Th, make and to avoid drawing between source electrode of n passage metal-oxide half field effect transistor 1st NMOS to be short-circuited.Wherein, a n passage metal-oxide half field effect transistor 1stNMOS can be place (field) n passage metal-oxide half field effect transistor, and the place oxide layer (fieldoxide layer) the 420th of its gate below can make gate critical voltage V
ThBecome big, see through and select the place n passage metal-oxide half field effect transistor of different processing procedures just can adjust this critical voltage value, to meet different normal working voltage demand (V
1-V
2＜V
Th).For example: utilize its bigger critical voltage V
ThCharacteristic, make it can be directly used in the external input/output terminal (I/O) of opening drain (open drain) of this internal circuit 440 and power voltage terminal V
DDBetween electrostatic discharge (ESD) protection.Cooperate the design of compound crystal silicon gate (poly-gate) 410 again, just can obtain preferable electrostatic discharge (ESD) protection effect.
Fig. 4 A is that the layout (layout) of this unidirectional ESD protection circuit is implemented illustration, and it is online and along the online section of b-b (cross-section) schematic diagram along a-a that Fig. 4 B and Fig. 4 C are respectively Fig. 4 A.Layout as Fig. 4 A strengthens/dwindles into and is longer than compound crystal silicon thin-film width W (width) on the oxide layer of place, makes the static discharge current of this compound crystal silicon gate below electronics channel of circulation increase/diminish, to meet the demand of different electrostatic discharge (ESD) protections.
Embodiment such as Fig. 3 B of two-way (two-directional) of the present invention ESD protection circuit are provided with protecting an internal circuit not to be subjected to the influence and the infringement of bidirectional ESD electric current, comprising: (a) one first static discharge end P
1, static discharge current and its voltage when being provided with importing/flow out this internal circuit generation electrostatic discharge event are V
1(b) one second static discharge end P
2, static discharge current and its voltage when being provided with this internal circuit generation electrostatic discharge event (ESD event) of outflow/importing are V
2(c) one the one n passage metal-oxide half field effect transistor 1st NMOS310, its gate connects this first static discharge end P
1, and its drain is connected this first static discharge end P respectively with source electrode
1With this second static discharge end P
2, be provided with this first static discharge end P when this internal circuit generation electrostatic discharge event
1To this second static discharge end P
2Static discharge potential difference (V during more than or equal to its gate critical voltage
1-V
2〉=V
Th, V
ThBe its gate critical voltage), to draw at it and to form short circuit between source electrode, the path that makes static discharge current avoid this internal circuit branches to it and draws short circuit between source electrode to form electrostatic discharge (ESD) protection; And (d) one the 2nd n passage metal-oxide half field effect transistor 2nd NMOS 320, its gate connects this second static discharge end P
2, and its drain is connected this second static discharge end P respectively with source electrode
2With this first static discharge end P
1, be provided with this second static discharge end P when this internal circuit generation electrostatic discharge event
2To this first static discharge end P
1Static discharge potential difference (V during more than or equal to its gate critical voltage
2-V
1〉=V
Th, V
ThBe its gate critical voltage), to draw at it and to form short circuit between source electrode, the path that makes static discharge current avoid this internal circuit branches to it and draws short circuit between source electrode to form electrostatic discharge (ESD) protection.Yet, under operate as normal (normal operation) voltage, this first static discharge end P
1With this second static discharge end P
2Between voltage difference (| V
1-V
2|) less than gate critical voltage V
Th, make and can avoid drawing between source electrode of n passage metal-oxide half field effect transistor to be short-circuited, the 2nd drawing between source electrode of n passage metal-oxide half field effect transistor is short-circuited.Wherein, a n passage metal-oxide half field effect transistor can be place n passage metal-oxide half field effect transistor, and the place oxide layer of its gate below can make gate critical voltage V
ThBecome big, see through and select the place n passage metal-oxide half field effect transistor of different processing procedures just can adjust this critical voltage value, to meet different normal working voltage demand (V
1-V
2＜V
Th).For example: utilize its bigger critical voltage V
ThCharacteristic, make it can be directly used in the external input/output terminal (I/O) of opening drain (open drain) of this internal circuit and power voltage terminal V
DDBetween electrostatic discharge (ESD) protection, cooperate compound crystal silicon gate (poly-gate) again, just can obtain preferable electrostatic discharge (ESD) protection effect.Again, the 2nd n passage metal-oxide half field effect transistor also can be place n passage metal-oxide half field effect transistor, sees through to select the place n passage metal-oxide half field effect transistor of different processing procedures just can adjust this critical voltage value, to meet different normal working voltage demand (V
2-V
1＜V
Th).For example: utilize it to have bigger critical voltage V
Th, can make it be used for protection from power voltage terminal V
DDElectrostatic discharge event.Equally cooperate compound crystal silicon gate (poly-gate) again, just can obtain preferable electrostatic discharge (ESD) protection effect.
Fig. 5 A is that the layout of this bidirectional ESD protective circuit is implemented illustration, and Fig. 5 B is that Fig. 5 A is along the online section of c-c (cross-section) schematic diagram.Layout as Fig. 5 A strengthens/dwindles into and is longer than compound crystal silicon thin-film width W (width) on the oxide layer of place, makes the static discharge current of this compound crystal silicon gate below electronics channel of circulation increase/diminish, to meet the demand of different electrostatic discharge (ESD) protections.
For instance, if this operating voltage range of opening the drain output is supply voltage V
DDUp and down within the 15V, even and bidirectional ESD protective circuit of the present invention in operating voltage near supply voltage V
DD(+-) during 15V, still keep this internal circuit normal operation; When this opens the drain output more than or equal to supply voltage normal working voltage V
DD+ 15V or this power voltage terminal are smaller or equal to supply voltage normal working voltage V
DD-15V promptly can start electrostatic discharge (ESD) protection shunting static discharge current immediately, prevents any abnormal voltage discharge outside operating voltage range effectively.
To sum up, according to above-mentioned accompanying drawing that discloses and explanation, the present invention can reach its intended purposes, and a kind of electrostatic discharge protection method and circuit are provided, can be for the utilization on the industry.
Claims (17)
1. electrostatic discharge protection method, influence and infringement when being provided with protecting an internal circuit not to be subjected to static discharge is characterized in that, may further comprise the steps:
(a) see through one first static discharge end, the static discharge current during with this internal circuit generation electrostatic discharge event imports; Again
(b) see through one second static discharge end, the static discharge current during with this internal circuit generation electrostatic discharge event flows out; Simultaneously,
When (c) utilizing this internal circuit generation electrostatic discharge event; voltage difference between this first static discharge end and this second static discharge end; make the gate pole oxidation layer below exhaustion region of one the one n passage metal-oxide half field effect transistor counter-rotating take place to produce the electronics channel; the static discharge current that is provided with this first static discharge end importing is able to be flowed out by this second static discharge end rapidly, reaches the effect of electrostatic discharge (ESD) protection.
2. a unidirectional ESD protection circuit is provided with protecting an internal circuit not to be subjected to the influence and the infringement of unidirectional static discharge current, it is characterized in that, comprising:
(a) one first static discharge end, static discharge current and its voltage when being provided with importing this internal circuit generation electrostatic discharge event are;
(b) one second static discharge end, static discharge current and its voltage when being provided with flowing out this internal circuit generation electrostatic discharge event are; And
One the one n passage metal-oxide half field effect transistor; its gate connects this first static discharge end; and its drain is connected this first static discharge end and this second static discharge end respectively with source electrode; be provided with when this internal circuit generation electrostatic discharge event this first static discharge end to the static discharge potential difference of this second static discharge end during more than or equal to its gate critical voltage; draw at it and to form short circuit between source electrode, the path that makes static discharge current avoid this internal circuit branches to it and draws short circuit between source electrode to form electrostatic discharge (ESD) protection.
3. unidirectional ESD protection circuit as claimed in claim 2 is characterized in that, under normal working voltage, and this first static discharge end and this second static discharge end P
2Between voltage difference system less than the gate critical voltage, make and avoid drawing between source electrode of n passage metal-oxide half field effect transistor to be short-circuited.
4. unidirectional ESD protection circuit as claimed in claim 2 is characterized in that, a n passage metal-oxide half field effect transistor is a place n passage metal-oxide half field effect transistor, and the place oxidation series of strata of its gate below make the gate critical voltage become big.
5. unidirectional ESD protection circuit as claimed in claim 4 is characterized in that, this critical voltage value system is adjusted by the place n passage metal-oxide half field effect transistor of selecting different processing procedures, to meet different normal working voltage demands.
6. unidirectional ESD protection circuit as claimed in claim 4 is to have bigger critical voltage, makes to be directly used in the external input/output terminal of opening drain of this internal circuit and the electrostatic discharge (ESD) protection between power voltage terminal.
7. unidirectional ESD protection circuit as claimed in claim 2 is characterized in that, the gate of a n passage metal-oxide half field effect transistor is the compound crystal silicon gate, to obtain preferable electrostatic discharge (ESD) protection effect.
8. a bidirectional ESD protective circuit is provided with protecting an internal circuit not to be subjected to the influence and the infringement of bidirectional ESD electric current, it is characterized in that, comprising:
(a) one first static discharge end, static discharge current and its voltage when being provided with importing/flow out this internal circuit generation electrostatic discharge event are;
(b) one second static discharge end, static discharge current and its voltage when being provided with flowing out/import this internal circuit generation electrostatic discharge event are;
(c) one the one n passage metal-oxide half field effect transistor, its gate connects this first static discharge end, and its drain is connected this first static discharge end and this second static discharge end respectively with source electrode, be provided with when this internal circuit generation electrostatic discharge event this first static discharge end to the static discharge potential difference of this second static discharge end during more than or equal to its gate critical voltage, draw at it and to form short circuit between source electrode, the path that makes static discharge current avoid this internal circuit branches to it and draws short circuit between source electrode to form electrostatic discharge (ESD) protection; And
(d) one the 2nd n passage metal-oxide half field effect transistor, its gate connects this second static discharge end, and its drain is connected this second static discharge end and this first static discharge end respectively with source electrode, is provided with when this internal circuit generation electrostatic discharge event this second static discharge end to this first static discharge end P
1Static discharge potential difference during more than or equal to its gate critical voltage, draw at it and to form short circuit between source electrode, the path that makes static discharge current avoid this internal circuit branches to it and draws short circuit between source electrode to form electrostatic discharge (ESD) protection.
9. bidirectional ESD protective circuit as claimed in claim 8; it is characterized in that; under normal working voltage; voltage difference between this first static discharge end and this second static discharge end is less than the gate critical voltage; make and avoid drawing between source electrode of n passage metal-oxide half field effect transistor to be short-circuited, the 2nd drawing between source electrode of n passage metal-oxide half field effect transistor is short-circuited.
10. bidirectional ESD protective circuit as claimed in claim 8 is characterized in that, a n passage metal-oxide half field effect transistor is a place n passage metal-oxide half field effect transistor, and the place oxide layer of its gate below is to make the gate critical voltage become big.
11. as the 10th described bidirectional ESD protective circuit of claim; it is characterized in that; the critical voltage value of the one n passage metal-oxide half field effect transistor can be adjusted by the place n passage metal-oxide half field effect transistor of selecting different processing procedures, to meet different normal working voltage demands.
12. bidirectional ESD protective circuit as claimed in claim 8 is characterized in that, the 2nd n passage metal-oxide half field effect transistor is a place n passage metal-oxide half field effect transistor, and the place oxide layer of its gate below is to make the gate critical voltage become big.
13. bidirectional ESD protective circuit as claimed in claim 12; it is characterized in that; the critical voltage value of the 2nd n passage metal-oxide half field effect transistor can be adjusted by the place n passage metal-oxide half field effect transistor of selecting different processing procedures, to meet different normal working voltage demands.
14. bidirectional ESD protective circuit as claimed in claim 10; it is characterized in that; the one n passage metal-oxide half field effect transistor is to have bigger critical voltage, makes to be directly used in the external input/output terminal of opening drain of this internal circuit and the electrostatic discharge (ESD) protection between power voltage terminal.
15. bidirectional ESD protective circuit as claimed in claim 12 is characterized in that, the 2nd n passage metal-oxide half field effect transistor is to have bigger critical voltage, is used in the electrostatic discharge event of protection from power voltage terminal.
16. bidirectional ESD protective circuit as claimed in claim 8 is characterized in that, the gate of a n passage metal-oxide half field effect transistor is the compound crystal silicon gate, to obtain preferable electrostatic discharge (ESD) protection effect.
17. bidirectional ESD protective circuit as claimed in claim 8 is characterized in that, the gate of the 2nd n passage metal-oxide half field effect transistor is the compound crystal silicon gate, to obtain preferable electrostatic discharge (ESD) protection effect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100075525A CN101241908A (en) | 2007-02-06 | 2007-02-06 | A static discharging protection method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100075525A CN101241908A (en) | 2007-02-06 | 2007-02-06 | A static discharging protection method and circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101241908A true CN101241908A (en) | 2008-08-13 |
Family
ID=39933271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100075525A Pending CN101241908A (en) | 2007-02-06 | 2007-02-06 | A static discharging protection method and circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101241908A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102967973A (en) * | 2012-11-08 | 2013-03-13 | 京东方科技集团股份有限公司 | Electrostatic discharge protective circuit and driving method and display panel |
| CN105487317A (en) * | 2016-01-25 | 2016-04-13 | 京东方科技集团股份有限公司 | Substrate and display device |
-
2007
- 2007-02-06 CN CNA2007100075525A patent/CN101241908A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102967973A (en) * | 2012-11-08 | 2013-03-13 | 京东方科技集团股份有限公司 | Electrostatic discharge protective circuit and driving method and display panel |
| US9013846B2 (en) | 2012-11-08 | 2015-04-21 | Boe Technology Group Co., Ltd. | Electro-static discharge protection circuit and method for driving the same and display panel |
| CN102967973B (en) * | 2012-11-08 | 2015-10-14 | 京东方科技集团股份有限公司 | A kind of ESD protection circuit and driving method and display panel |
| CN105487317A (en) * | 2016-01-25 | 2016-04-13 | 京东方科技集团股份有限公司 | Substrate and display device |
| WO2017128738A1 (en) * | 2016-01-25 | 2017-08-03 | Boe Technology Group Co., Ltd. | Substrate and display device containing the same |
| CN105487317B (en) * | 2016-01-25 | 2019-04-02 | 京东方科技集团股份有限公司 | A kind of substrate and display device |
| US10546851B2 (en) | 2016-01-25 | 2020-01-28 | Boe Technology Group Co., Ltd | Substrate and display device containing the same |
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