CN101236982A - Image pick-up device - Google Patents
Image pick-up device Download PDFInfo
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- CN101236982A CN101236982A CNA2008100085146A CN200810008514A CN101236982A CN 101236982 A CN101236982 A CN 101236982A CN A2008100085146 A CNA2008100085146 A CN A2008100085146A CN 200810008514 A CN200810008514 A CN 200810008514A CN 101236982 A CN101236982 A CN 101236982A
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- 230000005684 electric field Effects 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 96
- 239000010410 layer Substances 0.000 description 77
- 238000009792 diffusion process Methods 0.000 description 35
- 238000007667 floating Methods 0.000 description 35
- 239000011229 interlayer Substances 0.000 description 16
- 238000005192 partition Methods 0.000 description 16
- 238000009825 accumulation Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005755 formation reaction Methods 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000000926 separation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001151 other effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005381 potential energy Methods 0.000 description 2
- 101001014671 Heterostelium pallidum Cell-cell adhesion glycoprotein 64 Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Abstract
A image sensor includes a charge increasing portion for increasing the quantity of charges, a first electrode for applying a voltage regulating a region adjacent to the charge increasing portion to a prescribed potential, a second electrode provided adjacently to the first electrode for applying another voltage increasing the quantity of charges in the charge increasing portion, a first wire formed on a prescribed layer for supplying a signal to the first electrode and a second wire formed on a layer different from the prescribed layer for supplying another signal to the second electrode.
Description
Technical field
The present invention relates to camera head.
Background technology
As the known a kind of CCD of prior art (Charge Coupled Device) imageing sensor, it possesses times portion (electric charge increase portion) that increases that electronics (electric charge) increases doubly (increase) that is used for.
In this ccd image sensor that increases times type in the past, as shown in figure 25, on the surface of silicon substrate 501, be formed with gate oxide 502.In addition, the regulation zone on the upper surface of gate oxide 502, the interval that separates regulation is formed with 4 gate electrodes 503～506.Supply with the clock signal φ 11～φ 14 of 4 phases respectively to this gate electrode 503～506.
In addition, be formed with respectively in the transmission raceway groove 507 under gate electrode 503～506 the pixel separation partition wall, accumulate well, electric charge temporarily and transmit partition wall and electric charge accumulation well.This pixel separation partition wall has the electric charge accumulation well that well and adjacent pixels are accumulated in division temporarily, and adjacent electric charge is accumulated the function of temporarily accumulating well that is transmitted electronically to of well.In addition, accumulate the function that well has interim accumulated electrons when transmitting electronics temporarily.In addition, electric charge transmits partition wall and has division and accumulate well and electric charge accumulation well temporarily and will be accumulated in the function of temporarily accumulating in the well in the electric charge accumulation well of being transmitted electronically to.
In addition, electric charge accumulation well has to be accumulated from accumulating the function of the electronics that well sends temporarily, and also has as the function that increases times portion, and this increases times portion and is used for by the ionization by collision of electric field electronics being increased doubly.That is, the interface between electric charge transmission partition wall and electric charge accumulation well is formed with the high electric field region 508 that is adjusted to high potential, and the electronics that is sent to high electric field region 508 thus obtains energy from high electric field region 508.
Then, in the process that the electronics that obtains this energy moves in high electric field region 508 by with the atomic collision of silicon substrate 501, thereby generate electronics and hole.Then, in the electronics and hole of this generation, only electronics is pooled to electric charge accumulation well by the electric field in the high electric field region 508.Thus, carry out increasing doubly of electronics.In addition, increasing of this electronics doubly is to carry out in the process of transmission by the electronics of the photodiode generation of light area.
Then, with reference to Figure 25 in the past the action that increases doubly that increases times type ccd image sensor is described.
At first, after gate electrode 503 is supplied with the clock signal φ 11 of H level, made gate electrode 503 become conducting state, make the gate electrode 506 of adjacent pixels become cut-off state.Thus, the electronics of accumulating in the electric charge of the adjacent pixels accumulation well is sent to the pixel separation partition wall.
Then, after gate electrode 504 is supplied with the clock signal φ 12 of H level, made gate electrode 504 become conducting state, supply with the clock signal φ 11 of L level, make gate electrode 503 become cut-off state to gate electrode 503.Thus, the electronics that is sent to the pixel separation partition wall is sent to and accumulates well temporarily.
Then, the clock signal φ 14 to gate electrode 506 supply H level makes gate electrode 506 become conducting state.Thus, apply high voltage to gate electrode 506, the interface of transmitting between partition wall and the electric charge accumulation well at electric charge forms high electric field region 508.Afterwards, gate electrode 506 is kept under the state of conducting state, clock signal φ 12 to gate electrode 504 supply L level makes gate electrode 504 become cut-off state, crosses electric charge transmission partition wall and is sent to electric charge accumulation well thereby be accumulated in the electronics of accumulating in the well temporarily.Thus, the electronics that sends increases doubly under the ionization by collision effect of high electric field, and the electronics after increasing doubly is accumulated in the electric charge accumulation well.In addition, to the clock signal φ 13 of gate electrode 505 supply certain voltage, electric charge transmits partition wall and is adjusted to the regulation current potential and keeps constant.
But, consider to have used increasing in times cmos image sensor of the structure of type ccd image sensor in the past in hypothesis, be used for supplying with respectively connecting up of clock signal and be formed on same one deck to each gate electrode, and be adjacent to configuration, so there is following unfavorable condition: because the wiring capacitance between each wiring, and in the voltage of the gate electrode that supplies to each pixel respectively, produce discrete discrepancy.And, when the voltage of the gate electrode that supplies to each pixel and the voltage that supplies to gate electrode have produced under the situation of discrete discrepancy, have the problem that multiplying power produces discrete discrepancy that increases of electronics in each pixel.
Summary of the invention
The camera head of the present invention's first mode, it comprises: electric charge increase portion, it is used to make electric charge to increase; First electrode, it is used to apply and will be adjusted into the voltage of regulation current potential with electric charge increase portion adjacent areas; Second electrode, it is configured to adjacent with first electrode, is used to be applied to the voltage that electric charge increase portion increases electric charge; First wiring, it is formed on the layer of regulation, and is used for supplying with signal to first electrode; With second wiring, it is formed on the layer different with the layer of stipulating, and is used for supplying with signal to second electrode.
The camera head of second mode of the present invention, it comprises: electric charge increases mechanism, and it is used to make electric charge to increase; First electrode, it is used to apply will increase the voltage that mechanism's adjacent areas is adjusted into the regulation current potential with electric charge; Second electrode, it is configured to adjacent with first electrode, and being used to be applied to electric charge increases the voltage that mechanism increases electric charge; First wiring, it is formed on the layer of regulation, and is used for supplying with signal to first electrode; With second wiring, it is formed on the layer different with the layer of stipulating, and is used for supplying with signal to second electrode.
Description of drawings
Fig. 1 is the vertical view that the integral body of the COMS imageing sensor in expression first execution mode of the present invention constitutes.
Fig. 2 is the vertical view of the structure of the COMS imageing sensor in expression first execution mode.
Fig. 3 is the profile along the 700-700 line of Fig. 2.
Fig. 4 is the profile along the 710-710 line of Fig. 2.
Fig. 5 is the vertical view of the ground floor wiring of the COMS imageing sensor in expression first execution mode.
Fig. 6 is the vertical view of first and the second layer wiring of the COMS imageing sensor in expression first execution mode shown in Figure 1.
Fig. 7 is the vertical view of first, second and three-layer routing of the COMS imageing sensor of expression in first execution mode.
Fig. 8 is the circuit diagram of the formation of the COMS imageing sensor in expression first execution mode.
Fig. 9 be used for illustrating first execution mode the COMS imageing sensor electronics increase the doubly signal waveforms of action.
Figure 10 be used for illustrating first execution mode the COMS imageing sensor electronics increase the doubly potential energy diagram of action.
Figure 11 is the signal waveforms of reading action of electronics that is used for illustrating the COMS imageing sensor of first execution mode.
Figure 12 is the potential energy diagram of reading action of electronics that is used for illustrating the COMS imageing sensor of first execution mode.
Figure 13 is the vertical view of the structure of the COMS imageing sensor in expression second execution mode.
Figure 14 is the vertical view of the ground floor wiring of the COMS imageing sensor in expression second execution mode.
Figure 15 is the vertical view of first and the second layer wiring of the COMS imageing sensor in expression second execution mode.
Figure 16 is the vertical view of first, second and three-layer routing of the COMS imageing sensor of expression in second execution mode.
Figure 17 is the vertical view of the structure of the COMS imageing sensor in expression the 3rd execution mode.
Figure 18 is the vertical view of the ground floor wiring of the COMS imageing sensor in expression the 3rd execution mode.
Figure 19 is the vertical view of first and the second layer wiring of the COMS imageing sensor in expression the 3rd execution mode.
Figure 20 is the vertical view of first, second and three-layer routing of the COMS imageing sensor of expression in the 3rd execution mode.
Figure 21 is the vertical view of the structure of the COMS imageing sensor in expression the 4th execution mode.
Figure 22 is the vertical view of the ground floor wiring of the COMS imageing sensor in expression the 4th execution mode.
Figure 23 is the vertical view of first and the second layer wiring of the COMS imageing sensor in expression the 4th execution mode.
Figure 24 is the vertical view of first, second and three-layer routing of the COMS imageing sensor of expression in the 4th execution mode.
Figure 25 is times profile of representing in the past of the structure of type ccd image sensor that increases.
Embodiment
Below, with reference to the accompanying drawings embodiments of the present invention are described.In addition, in the following embodiments, be to have used situation of the present invention in the COMS imageing sensor to describe to a example at camera head.
(first execution mode)
At first, the structure with reference to the COMS imageing sensor 100 of Fig. 1～8 pair first execution mode describes.
As shown in Figure 1, the COMS imageing sensor 100 of first execution mode comprises: image pickup part 51, and it comprises a plurality of pixels 50 with rectangular (ranks shape) configuration; Row mask register 52; With column selection register 53.
As Fig. 2 and shown in Figure 3, the structure as the pixel 50 of the COMS imageing sensor 100 of first execution mode is formed with the element separated region 2 that is used for separating respectively each pixel 50 on the surface of p type silicon substrate 1.In addition, on the surface of the p type silicon substrate 1 of each pixel 50 of surrounding, according to clipping by n by element separated region 2
-The mode of the transmission raceway groove 3 (with reference to Fig. 3) that the type extrinsic region constitutes separates the interval of regulation, forms photodiode portion (PD) 4 and by n
+The floating diffusion zone (FD) 5 that the type extrinsic region constitutes.Transmission raceway groove 3 is formed on the directions X and extends.In addition, photodiode portion 4 and floating diffusion zone (floating diffusion) 5 is respectively an example of " photoelectric conversion part " of the present invention and " maintaining part ".
In addition, the surface at the p type silicon substrate 1 of each pixel 50 of being surrounded by element separated region 2 as Fig. 2 and shown in Figure 4, according to clipping the mode that transmits raceway groove 6 (with reference to Fig. 4), separates predetermined distance and forms reset drain (RD) 7 of portion and efferent 8.In addition, be formed with transmission raceway groove 9 (with reference to Fig. 4) between floating diffusion zone 5 and the reset drain portion 7.
On the upper surface that transmits raceway groove 3, as shown in Figure 3, be formed with gate insulating film 10a.In addition, the regulation zone on the upper surface of gate insulating film 10a separates predetermined distance, forms transmission gate electrode 11～13 in order, increases times gate electrode 14, reads gate electrode 15 towards floating diffusion zone 5 sides from photodiode portion 4 sides.That is, transmitting gate electrode 11 is formed adjacent with photodiode portion 4.In addition, reading gate electrode 15 is formed adjacent with floating diffusion zone 5.In addition, transmitting gate electrode 11,12 and 13 is respectively an example of " the 5th electrode " of the present invention, " third electrode " and " first electrode ".In addition, increasing times gate electrode 14 is examples of " second electrode " of the present invention, and reading gate electrode 15 is examples of " the 4th electrode " of the present invention.
As shown in Figure 4, on the upper surface that transmits raceway groove 6, be formed with gate insulating film 10b.In addition, the regulation zone on the upper surface of gate insulating film 10b is formed with amplifying gate electrode 16 and row is selected gate electrode 17.It is adjacent with reset drain portion 7 that amplifying gate electrode 16 is formed, and row selects gate electrode 17 to be formed adjacent with efferent 8.In addition, on the upper surface that transmits raceway groove 9, be formed with gate insulating film 10c.In addition, on the upper surface of gate insulating film 10c, be formed with reset gate electrode 18.It is adjacent with floating diffusion zone 5 that reset gate electrode 18 is formed, and adjacent with reset drain portion 7.
Here, in the first embodiment, on the upper surface of p type silicon substrate 1, be formed with the ground floor wiring across interlayer dielectric.As Fig. 3～shown in Figure 5, wiring 19a, 19b and 19c are made of the ground floor wiring.In addition, wiring 19a and 19b are respectively examples of " the 5th wiring " of the present invention and " first wiring ".As shown in Figure 5, wiring 19a is formed: via contact site 11a with transmit gate electrode 11 and be connected, and when the zone corresponding with photodiode portion 4 makes a circulation, extend along the Y direction.In addition, wiring 19b is formed: via contact site 13a with transmit gate electrode 13 and be connected, and when the zone corresponding with photodiode portion 4 makes a circulation, extend along the Y direction.In addition, wiring 19c is formed: be connected with floating diffusion zone 5 via contact site 5a, and be connected with amplifying gate electrode 16 via contact site 16a.In addition, by each row wiring 19a and 19b are set.That is, on each wiring 19a, connect the transmission gate electrode 11 that column direction (Y direction) is gone up adjacent a plurality of pixels 50, and on each wiring 19b, connect the transmission gate electrode 13 that column direction (Y direction) is gone up adjacent a plurality of pixels 50.In addition, according to each pixel 50 wiring 19c is set.
In addition, in the first embodiment, on the upper surface of ground floor wiring, be formed with second layer wiring across not shown interlayer dielectric.As Fig. 3, Fig. 4 and shown in Figure 6, read gate line 20a, resetting gate polar curve 20b and row selection wire 20c is made of second layer wiring.In addition, read the example that gate line 20a is " the 3rd wiring " of the present invention.As shown in Figure 6, reading gate line 20a, resetting gate polar curve 20b and row selection wire 20c is formed on the directions X and extends.In addition, read gate line 20a via contact site 15a with read gate electrode 15 and be connected.In addition, resetting gate polar curve 20b is formed: be connected with reset gate electrode 18 via contact site 18a, and circuitous in the zone corresponding with contact site 15a.Have, row selection wire 21c selects gate electrode 17 to be connected via contact site 1 7a with row again.In addition, read gate line 20a, resetting gate polar curve 20b and row selection wire 20c according to each row setting.That is, respectively read connect on the gate line 20a that line direction (directions X) goes up adjacent a plurality of pixels 50 read gate electrode 15, and on each resetting gate polar curve 20b, connect the reset gate electrode 18 that line direction (directions X) is gone up adjacent a plurality of pixels 50.In addition, on each row selection wire 20c, connect the row selection gate electrode 17 that line direction (directions X) is gone up adjacent a plurality of pixels 50.
In addition, in the first embodiment, on the upper surface of second layer wiring, form three-layer routing across not shown interlayer dielectric.As Fig. 4 and shown in Figure 7, vdd line 21a and holding wire 21b are made of three-layer routing.As shown in Figure 7, vdd line 21a and holding wire 21b are formed on the Y direction and extend.Vdd line 21a is connected with reset drain portion 7 via contact site 7a.In addition, holding wire 21b is connected with efferent 8 via contact site 8a.In addition, by each row vdd line 21a and holding wire 21b are set.That is, on each vdd line 21a, connect the reset drain portion 5 that column direction (Y direction) is gone up adjacent a plurality of pixels 50, and on each holding wire 21b, connect the efferent 8 that column direction (Y direction) is gone up adjacent a plurality of pixels 50.
In addition, in the first embodiment, on the upper surface of three-layer routing, form the 4th layer of wiring across not shown interlayer dielectric.As shown in Figures 2 and 3, wiring 22a and 22b are made of the 4th layer of wiring.In addition, wiring 22a and wiring 22b are respectively examples of " second wiring " of the present invention and " the 4th wiring ".As shown in Figure 2, wiring 22a and wiring 22b are formed on the directions X and extend.In addition, wiring 22a via contact site 14a with increase times gate electrode 14 and be connected.In addition, the wiring 22a that is made of the 4th layer of wiring is formed under the situation of overlooking with the wiring 19b that is made of the ground floor wiring and intersects.In addition, the wiring 22b that is made of the 4th layer of wiring is connected with transmission gate electrode 12 via contact site 12a when the zone corresponding with photodiode portion 4 is circuitous.In addition, wiring 22a and the 22b that is made of the 4th layer of wiring is provided with according to each row.That is, increase times gate electrode 14 what each wiring connected a plurality of pixels 50 adjacent on line direction (X) direction on 22a, and on each wiring 22b, connect the transmission gate electrode 12 of a plurality of pixels 50 adjacent on line direction (X) direction.
In addition, as shown in Figure 8, wiring 19a, 22b, 19b and 22a be for respectively via contact site 11a, 12a, 13a and 14a, supply with and be used for voltage-controlled clock signal φ 1, φ 2, φ 3 and φ 4 and be provided with to transmitting gate electrode 11,12,13 and increasing times gate electrode 14.
In addition, as shown in Figure 3, passing through wiring 19a, 22a and 19b respectively under the situation of the Continuity signal (signal of H level) that transmits gate electrode 11,12 and 13 supply clock signal φ 1, φ 2 and φ 3, to transmitting the voltage that gate electrode 11,12 and 13 applies about 2.9V.Thus, under the situation of the Continuity signal (signal of H level) that transmits gate electrode 11,12 and 13 supply clock signal φ 1, φ 2 and φ 3, the transmission raceway groove 3 under the transmission gate electrode 11,12 and 13 is adjusted to the current potential of about 4V.In addition, under the situation of the pick-off signal (signal of L level) that transmits gate electrode 11,12 and 13 supply clock signal φ 1, φ 2 and φ 3, the transmission raceway groove 3 under the transmission gate electrode 11,12 and 13 is adjusted to the current potential of about 1V.
In addition, at wiring 22a, under the situation of the Continuity signal (signal of H level) that increases times gate electrode 14 supply clock signal φ 4, to increasing the voltage that times gate electrode 14 applies about 24V by constituting by the 4th layer of wiring.Thus, supplying with under the situation of Continuity signal (signal of H level) of clock signal φ 4, increasing the state that transmission raceway groove 3 under times gate electrode 14 becomes the high potential that is adjusted to about 25V to increasing times gate electrode 14.In addition, supplying with under the situation of pick-off signal (signal of L level) of clock signal φ 4, increasing the state that transmission raceway groove 3 under times gate electrode 14 becomes the current potential that is adjusted to about 1V to increasing times gate electrode 14.
In addition, reading gate line 20a, supply with under the situation of Continuity signals (signal of H level), to reading the voltage that gate electrode 15 applies about 2.9V to reading gate electrode 15 by what constitute by second layer wiring.Thus, supplying with under the situation of Continuity signal (signal of H level) to reading gate electrode 15, the transmission raceway groove of reading under the gate electrode 15 3 becomes the state that is adjusted to about 4V current potential.In addition, supplying with under the situation of pick-off signal (signal of L level) to reading gate electrode 15, the transmission raceway groove of reading under the gate electrode 15 3 becomes the state that is adjusted to about 1V current potential.In addition, photodiode portion 4 and floating diffusion zone 5 become the state of the current potential that is adjusted to about 3V and 5V respectively.
Thus, the transmission raceway groove 3 (electronics is accumulated the 3a of portion) that transmits under the gate electrode 12 is constituted as: supplying with under the situation of Continuity signal (signal of H level) to transmitting gate electrode 12, at the electric field that transmits the interim accumulated electrons of transmission raceway groove 3 (electronics is accumulated the 3a of portion's (accumulating well)) formation under the gate electrode 12 temporarily.In addition, electronics is accumulated the example that the 3a of portion is " accumulating portion " of the present invention.
In addition, the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14 is constituted as: supplying with under the situation of Continuity signal (signal of H level) to increasing times gate electrode 14, by being adjusted into the current potential of about 2.5V, make thus electronics with the transmission raceway groove 3 (electronics increases the 3b of a times portion (electric charge accumulation well)) that increases under times gate electrode 14 in ionization by collision, form the high electric field that electronics increases doubly (increase).In addition, the ionization by collision of electronics is to produce with the interface that transmits the transmission raceway groove 3 under the gate electrode 9 at the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14.In addition, electronics increases the example that times 3b of portion is " an electric charge increase portion " of the present invention.
In addition, the transmission raceway groove 3 that transmits under the gate electrode 11 has in the function that electronics is accumulated the 3a of portion that is transmitted electronically to that will be accumulated under the situation that transmits gate electrode 11 supply Continuity signals (signal of H level) in the photodiode portion 4, and, separate partition wall performance function with the photodiode that electronics is accumulated the 3a of portion as divided light electric diode portion 4 supplying with under the situation of pick-off signal (signal of L level) to transmitting gate electrode 11.
In addition, transmitting transmission raceway groove 3 under the gate electrode 13 has and is supplying with and will be accumulated in the electronics that is transmitted electronically to that electronics accumulates among the 3a of portion under the situation of Continuity signals (signal of H level) and increase times 3b of portion and will be accumulated in electronics and increase the function that electronics is accumulated the 3a of portion that is transmitted electronically among times 3b of portion to transmitting gate electrode 13.In addition, transmit the transmission raceway groove 3 under the gate electrode 13, supplying with under the situation of pick-off signals (signal of L level), accumulate the electric charge that the 3a of portion and electronics increase times 3b of portion and transmit partition wall performance function as dividing electronics to transmitting gate electrode 13.That is, transmit gate electrode 13, can increase times 3b of portion with being accumulated in the electronics that is transmitted electronically to that electronics accumulates among the 3a of portion thus, and will be accumulated in electronics and increase and be transmitted electronically to electronics among times 3b of portion and accumulate among the 3a of portion by being supplied to Continuity signal (signal of H level).
In addition, read transmission raceway groove 3 under the gate electrode 15 and have and supplying with and to be accumulated in electronics under the situation of Continuity signals (signal of H level) and to increase the function that is transmitted electronically to floating diffusion zone 5 among times 3b of portion, and have and supplying with under the situation of pick-off signals (signal of L level) and divide the function that electronics increases times 3b of portion and floating diffusion zone 5 to reading gate electrode 15 to reading gate electrode 15.That is, read gate electrode 15, can increase being transmitted electronically in the floating diffusion zone 5 among times 3b of portion with being accumulated in electronics thus by being supplied to Continuity signal (signal of H level).
In addition, as shown in Figure 8, supply with reset signal, and row selection wire 20c is connected with row mask register 52 (with reference to Fig. 1) to the resetting gate polar curve 20b that constitutes by second layer wiring.In addition, the holding wire 21b that is made of three-layer routing is connected with column selection register 53 (with reference to Fig. 1), and to vdd line 21a supply line voltage VDD (for example about 5V).
Then, with reference to Fig. 9 and Figure 10, the action that increases doubly of the electronics in the cmos image sensor in first execution mode 100 is described.
At first, during Fig. 9, among the A, as shown in figure 10, be conducting state by making transmission gate electrode 11, thereby the transmission raceway groove 3 under the transmission gate electrode 11 becomes the state of the current potential that is adjusted to about 4V.At this moment, because photodiode portion 4 is adjusted to the current potential of about 3V, so generate and the electronics accumulated is transferred into transmission raceway groove 3 under the transmission gate electrode 11 from photodiode portion 4 by photodiode portion 4.Afterwards, become conducting state by making transmission gate electrode 12, thereby the transmission raceway groove 3 that transmits under the gate electrode 12 becomes the state that is adjusted to about 4V current potential.
Then, during Fig. 9, among the B, as shown in figure 10, become cut-off state by making transmission gate electrode 11, thereby the transmission raceway groove 3 under the transmission gate electrode 11 becomes the state of the current potential that is adjusted to about 1V.At this moment, because the transmission raceway groove 3 that transmits under the gate electrode 12 is adjusted to the current potential of about 4V, be sent to the transmission raceway groove 3 (electronics is accumulated the 3a of portion) that transmits under the gate electrode 12 so be positioned at the electronics that transmits the transmission raceway groove 3 under the gate electrode 11.Afterwards, increase times gate electrode 14 and become conducting state by making, thereby the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14 becomes the state that is adjusted to about 25V current potential.
Then, C during Fig. 9 as shown in figure 10, become conducting state by making transmission gate electrode 13, thereby the transmission raceway groove 3 under the transmission gate electrode 13 becomes the state of the current potential that is adjusted to about 4V.At this moment, electronics in accumulating the transmission raceway groove 3 (electronics is accumulated the 3a of portion) that transmits under the gate electrode 12 is sent to the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14, and this transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14 is adjusted to than the also high current potential (about 25V) of current potential (about 4V) that transmits the transmission raceway groove 3 under the gate electrode 12 and 13.Then, the electronics that is sent to the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14 under increasing times gate electrode 14 transmission raceway groove 3 and transmit in the process that the interface between the transmission raceway groove 3 under the gate electrode 13 moves and obtain energy by high electric field.Then, have the collision of high-octane electronics and silicon atom and generate electronics and hole.Afterwards, the electronics that generates by ionization by collision is being accumulated in the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14 under the effect of electric field.
Then, D during Fig. 9 as shown in figure 10, increases times gate electrode 14 and becomes cut-off state by making, thereby increases the state that transmission raceway groove 3 under times gate electrode 14 becomes the current potential that is adjusted to about 1V.At this moment, the electronics of accumulating in the transmission raceway groove 3 under increasing times gate electrode 14 is sent to the transmission raceway groove 3 that transmits under the gate electrode 12 and 13, and the transmission raceway groove 3 under this transmission gate electrode 12 and 13 is adjusted to the current potential (about 4V) higher than the current potential that increases the transmission raceway groove 3 under times gate electrode 14 (about 1V).Then, become cut-off state by making transmission gate electrode 13, thereby the transmission raceway groove 3 under the transmission gate electrode 13 becomes the state of the current potential that is adjusted to about 1V.At this moment, be positioned at the electronics that transmits transmission raceway groove 3 places under the gate electrode 13 and be sent to the transmission raceway groove 3 (electronics is accumulated the 3a of portion) that transmits under the gate electrode 12, the transmission raceway groove 3 under this transmission gate electrode 12 (electronics is accumulated the 3a of portion) is adjusted to than the high current potential (about 4V) of current potential (about 1V) that transmits the transmission raceway groove under the gate electrode 13.
Afterwards, by repeated multiple times (for example about 400 times) carry out above-mentioned during B～D increase doubly action, the electronics that transmits from photodiode portion 4 increases doubly to about 200 times thus.
Then, with reference to Fig. 8 and Figure 10～Figure 12, to the electronics in the cmos image sensor in first execution mode 100 read the action describe.
At first, electronics read action the increasing doubly after the action of C during Figure 10, during Figure 11 among the E, as shown in figure 12, under electronics is accumulated in state in the transmission raceway groove 3 (electronics increases times 3b of portion) that increases under times gate electrode 14, transmit gate electrode 12 and 13 and become cut-off state by making, thereby transmit the state that transmission raceway groove 3 under the gate electrode 12 and 13 becomes the current potential that is adjusted to about 1V.Afterwards, read gate electrode 15 and become conducting state, thereby read the state that transmission raceway groove 3 under the gate electrode 15 becomes the current potential that is adjusted to about 4V by making.
Then, F during Figure 11 as shown in figure 12, increases times gate electrode 14 and becomes cut-off state by making, thereby increases the state that transmission raceway groove 3 under times gate electrode 14 becomes the current potential that is adjusted to about 1V.At this moment, the electronics of accumulating in the transmission raceway groove 3 under increasing times gate electrode 14 (electronics increases times 3b of portion), by being adjusted to the transmission raceway groove 3 under the gate electrode 15 read of 4V current potential, be sent to floating diffusion zone 5, this floating diffusion zone 5 is adjusted to the current potential (about 5V) higher than the current potential that increases the transmission raceway groove 3 under times gate electrode 14 (about 1V).
At this moment, as shown in Figure 8, the amplifying gate electrode 16 of each pixel 50 is connected with floating diffusion zone 5 by wiring 9c, and becomes the conducting state of answering with the duplet of floating diffusion zone 5 maintenances.Under this state be cut-off state because row is selected gate electrode 17, so in holding wire 21b streaming current not.
Then, by supplying with the signal of H level to row selection wire 20c in turn, select gate electrode 17 to become conducting state in turn thereby go.Thus, the conducting state of corresponding amplifying gate electrode 16 and streaming current in turn in holding wire 21b.Thus, the charge signal that is fed into the electronics in floating diffusion zone 5 is exported as voltage signal.Then, behind whole end of outputs,, make reset gate electrode 18 become conducting state, thereby the current potential in the floating diffusion zone 5 of whole pixels 50 is reset to 5V by supply with the reset signal of H level to resetting gate polar curve 20b.
In the first embodiment, as mentioned above, be formed for supplying with the wiring 19b of clock signal φ 3 by the ground floor wiring to transmitting gate electrode 13, and be formed for supplying with the wiring 22a of clock signal φ 4 to increasing times gate electrode 14 by the 4th layer of wiring different with the ground floor wiring, thereby with by comparing with the situation of the adjacent formation of one deck wiring 19a and wiring 22a, because big by the distance between ground floor wiring wiring 19b that constitutes and the wiring 22a that constitutes by the 4th layer of wiring, thus can dwindle by ground floor connect up the wiring 19b that constitutes and the wiring 22a that constitutes by the 4th layer of wiring between electric capacity.Thus, can suppress to produce discrete discrepancy to the voltage of the clock signal φ 3 that the transmission gate electrode 13 of each pixel 50 is supplied with and in the voltage that increases the clock signal φ 4 that times gate electrode 14 supplies with.Its result, in each pixel 50 since can suppress transmission under the gate electrode 13 transmission raceway groove 3 and increase in the potential difference between the transmission raceway groove 3 under times gate electrode 14 and produce discrete discrepancy, so can suppress in each pixel 50 electronics increase multiplying power generation discrete discrepancy.
In addition, in the first embodiment, intersect by forming with the wiring 22a that constitutes by the 4th layer of wiring by the wiring 19b that the ground floor wiring constitutes, thereby the area of the mutual opposed part of wiring 22a that can dwindle the wiring 19b that constitutes by ground floor wiring and constitute by the 4th layer of wiring, thus can further dwindle the wiring 19b that constitutes by the ground floor wiring and the wiring 22a that constitutes by the 4th layer of wiring between electric capacity.Thus, can further suppress to produce discrete discrepancy to the voltage of the clock signal φ 3 that the transmission gate electrode 13 of each pixel 50 is supplied with and in the voltage that increases the clock signal φ 4 that times gate electrode 14 supplies with.
In addition, in the first embodiment, by forming wiring 22a by the 4th layer of wiring different with the ground floor wiring, thereby with by comparing with the situation of the adjacent formation of one deck wiring 19b and 22a, can make the 19b that constitutes by ground floor wiring circuitous, so can improve the numerical aperture of cmos image sensor 100 in the zone corresponding with photodiode portion 4.
In addition, in the first embodiment, accumulate the 3a of portion by the electronics that is formed for accumulated electrons and transmit, alternately carry out accumulating the 3a of portion repeatedly and increase that times 3b of portion transmits electronics and increasing doubly and increasing times 3b of portion from electronics of realizing accumulated the 3a of portion transmission electronics to electronics, thereby can improve the multiplying power that increases of electronics to electronics from electronics.
In addition, in the first embodiment, by be formed for supplying with the wiring 22a of clock signal φ 4 by the 4th layer of wiring to increasing times gate electrode 14, and by being formed for reading gate electrode 20a to what read that gate electrode 15 supplies with signals with the wiring of the 4th layer of different second layer of wiring, with compare by the situation that is adjacent to form wiring 22a with one deck and reads gate line 20a, wiring 22a and how long the distance between the 20a increase, so can dwindle wiring 22a and read electric capacity between the gate line 20a.Thus, in the time of suppressing sense data, because of being changed to pick-off signal to the Continuity signal that times gate electrode 14 supplies with that increases of the electric field that is used to produce electron impact ionization, supply to the signal change of reading gate electrode 15 and make via reading gate line 20a via wiring 22a.Its result can correctly carry out reading of data.
In addition, in the first embodiment, by supplying with the wiring 22b of clock signal φ 2 to transmitting gate electrode 12 the 4th layer of formation, forming to the wiring 19b that transmits gate electrode 13 supply clock signal φ 3 with the 4th layer of different ground floor that connects up, and wiring 22b and wiring 19b are intersected mutually, thereby with compare by the situation that is adjacent to form wiring 22b and wiring 19b with one deck, can dwindle connect up 22b and the electric capacity between 1 9b of connecting up.Thus, can stably produce the electric field that is used for accumulating the interim accumulated electrons of the 3a of portion by transmitting gate electrode 12 at electronics.
In addition, in the first embodiment, by holding wire 21b being formed on and being formed with different the 3rd layer of the second layer of reading gate line 20a, and make it and read gate line 20a and intersect, thereby with comparing with the situation of reading gate line 20a forming holding wire 21b with one deck, can reduce holding wire 21b and read electric capacity between gate line 20a.Thus, can read the electronics that keeps in the floating diffusion zone 5 reliably by reading gate line 20a.
In addition, in the first embodiment, under the situation of overlooking, make wiring 19a not with the overlapping state of photodiode portion 4 The corresponding area under, and the outer rim along photodiode portion 4 forms wiring 19a, thereby under the long-pending situation in the plane that has increased photodiode portion 4, because wiring 19a is configured to not overlapping with photodiode portion 4, even so under the low situation of illumination, can light be transformed to electronics with the long-pending amount in plane that has increased photodiode portion 4.
In addition, in the first embodiment, formed the zone of wiring 19a in outer edge along photodiode portion 4, under the situation of overlooking, make wiring 22b not overlapping with wiring 19a, thereby can be with overlay configuration the amount of wiring 22b and wiring 19a, the plane that increases 1 photodiode portion 4 in the pixel 50 is long-pending.
In addition, in the first embodiment, by separating second layer wiring with wiring 22a and three-layer routing comes laying-out and wiring 19b, thus can be to separate a plurality of layers electric capacity between the amount of configuration further reduces to connect up.
(second execution mode)
Illustrate with reference to Figure 13～Figure 16: different with above-mentioned first execution mode in this second execution mode, the structure of the cmos image sensor 200 in adjacent 2 pixel 150a and the total floating diffusion zone 105 of 150b on directions X.
As shown in figure 13, the floating diffusion zone 105 of this second execution mode be configured to pixel 150a read gate electrode 15, pixel 150b read gate electrode 15, reset gate electrode 118 is adjacent.In addition, floating diffusion zone 105 is examples of " maintaining part " of the present invention.
In addition, in second execution mode,, be provided with the total reset gate electrode 118 of pixel 150a and 150b, reset drain portion 107, amplifying gate electrode 116, row selection gate electrode 117 and efferent 108 at the juncture area of pixel 150a and 150b.
In addition, floating diffusion zone 5, reset gate electrode 18, reset drain portion 7, amplifying gate electrode 16, row selection gate electrode 17 and the efferent 8 with above-mentioned first execution mode is identical respectively for other formations of floating diffusion zone 105, reset gate electrode 118, reset drain portion 107, amplifying gate electrode 116, row selection gate electrode 117 and efferent 108.
In addition, in second execution mode, on the upper surface of p type silicon substrate 101, form the ground floor wiring across not shown interlayer dielectric.As shown in figure 14, wiring 19a, 19b, 19c and read gate line 119d and constitute by ground floor wiring.In addition, read the example that gate line 119d is " the 3rd wiring " of the present invention.The total wiring of pixel 150a and 150b 119c.In addition, wiring 119c is connected with amplifying gate electrode 116 via contact site 116a, and is connected with floating diffusion zone 105 via contact site 105a.In addition, reading gate line 119d is formed on the Y direction according to each row and extends.In addition, read connect on the gate line 119d that column direction (Y direction) goes up adjacent a plurality of pixel 150a (150b) read gate electrode 15.In addition, wiring 119c and read gate line 119d other constitute respectively with the wiring 19c of above-mentioned first execution mode and to read gate line 20a identical.
In addition, in second execution mode, on the upper surface of ground floor wiring, form second layer wiring across not shown interlayer dielectric.As shown in figure 15, resetting gate polar curve 120b and row selection wire 120c are made of second layer wiring.Resetting gate polar curve 120b is connected with reset gate electrode 118 via contact site 118a.In addition, going selection wire 120c selects gate electrode 117 to be connected via contact site 117a with row.In addition, other of resetting gate polar curve 120b and row selection wire 120c constitute identical with the resetting gate polar curve 20b of above-mentioned first execution mode and the selection wire 20c that goes respectively.
In addition, in second execution mode, on the upper surface of second layer wiring, form three-layer routing across not shown interlayer dielectric.As shown in figure 16, vdd line 121a and holding wire 121b are made of three-layer routing.Vdd line 121a is connected with reset drain portion 107 via contact site 107a.In addition, holding wire 121b is connected with efferent 108 via contact site 108a.In addition, vdd line 21a and the holding wire 21b with above-mentioned first execution mode is identical respectively for other formations of vdd line 121a and holding wire 121b.
In addition, in second execution mode, on the upper surface of three-layer routing, form the 4th layer of wiring across not shown interlayer dielectric.As shown in figure 13, wiring 22a and 22b are made of the 4th layer of wiring.
In addition, other formations of second execution mode are identical with above-mentioned first execution mode.
In second execution mode, as mentioned above, the total floating diffusion zone 105 of adjacent 2 pixel 150a and 150b on directions X, thus compare with the situation that the floating diffusion zone is set in each pixel, can increase the light-receiving area of the photodiode portion 4 in the cmos image sensor 200.Thus, can improve the sensitivity of cmos image sensor 200.
In addition, in second execution mode, by forming with the wiring 22a that constitutes by the 4th layer of wiring and intersect by the gate line 119d that reads that ground floor wiring constitutes, thereby can dwindle the area of the mutual opposed part of wiring 22a of reading gate line 119d and constituting by the 4th layer of wiring that constitutes by ground floor wiring, so the electric capacity between the wiring 22a that reads gate line 119d and constitute by the 4th layer of wiring that can further reduce to constitute by the ground floor wiring.Thus, in the time of suppressing sense data, because of being changed to pick-off signal to the Continuity signal that times gate electrode 14 supplies with that increases of the electric field that is used to produce electron impact ionization, supply to the signal change of reading gate electrode 15 and make via reading gate line 119d via wiring 22a.
In addition, other effects of second execution mode are identical with above-mentioned first execution mode.
(the 3rd execution mode)
Illustrate with reference to Figure 17～Figure 20: in the 3rd execution mode, different with above-mentioned second execution mode, adjacent 2 pixel 250a and 250b on directions X are except the also total structure that increases times gate electrode 214 and read the cmos image sensor 300 of gate electrode 215 in floating diffusion zone 105.
As shown in figure 17, the 3rd execution mode increases that times gate electrode 214 is configured to the transmission gate electrode 13 of the transmission gate electrode 13 of pixel 250a, pixel 250b, to read gate electrode 215 adjacent.In addition, reading gate electrode 215 is configured to adjacent with floating diffusion zone 105.In addition, increase times gate electrode 214 and read gate electrode 215 other constitute respectively with above-mentioned first execution mode increase times gate electrode 14 and read gate electrode 15 identical.In addition, increase times gate electrode 214 and read the example that gate electrode 215 is respectively " second electrode " of the present invention and " the 4th electrode ".
In addition, in the 3rd execution mode, on the upper surface of p type silicon substrate 201, form the ground floor wiring across not shown interlayer dielectric.As shown in figure 18, wiring 19a, 19b and 19c are made of the ground floor wiring.
In addition, in the 3rd execution mode, on the upper surface of ground floor wiring, form second layer wiring across not shown interlayer dielectric.As shown in figure 19, read gate line 220a, resetting gate polar curve 120b and row selection wire 120c is made of second layer wiring.In addition, read the example that gate line 220a is " the 3rd wiring " of the present invention.Read gate line 220a via contact site 215a with read gate electrode 215 and be connected.In addition, other that read gate line 220a constitute with above-mentioned first execution mode to read gate line 20a identical.
In addition, in the 3rd execution mode, on the upper surface of second layer wiring, form three-layer routing across not shown interlayer dielectric.As shown in figure 20, vdd line 221a and holding wire 121b are made of three-layer routing.
In addition, in the 3rd execution mode, above the three-layer routing on, form the 4th layer of wiring across not shown interlayer dielectric.As shown in figure 17, wiring 222a and 22b are made of the 4th layer of wiring.In addition, wiring 222a is an example of " second wiring " of the present invention.Wiring 222a via contact site 214a with increase times gate electrode 214 and be connected.In addition, other formations of wiring 222a and 22b are identical with the wiring 22a and the 22b of above-mentioned first execution mode.
In addition, other formations of the 3rd execution mode are identical with above-mentioned second execution mode.
In the 3rd execution mode, as mentioned above, adjacent 2 pixel 250a and 250b be except floating diffusion zone 105 on directions X, also totally increases times gate electrode 214 and read gate electrode 215, thereby can increase the light-receiving area of the photodiode portion 4 in the cmos image sensor 300.
In addition, other effects of the 3rd execution mode are identical with above-mentioned second execution mode.
(the 4th execution mode)
Illustrate with reference to Figure 21～Figure 24: in the 4th execution mode, different with above-mentioned first execution mode, be included in photodiode portion 4 and increase the structure of the cmos image sensor 400 that only forms a pixel 350 that transmits gate electrode 313 between times gate electrode 14.In addition, transmitting gate electrode 313 is examples of " first electrode " of the present invention.
The photodiode portion 4 of the 4th execution mode also has the function of temporarily accumulating well.
In addition, in the 4th execution mode, on the upper surface of p type silicon substrate 301, form the ground floor wiring across not shown interlayer dielectric.As shown in figure 22, reading gate line 319d, wiring 19c and 319e is made of the ground floor wiring.In addition, read the example that gate line 319d and wiring 319e are respectively " the 3rd wiring " of the present invention and " first wiring ".In addition, reading gate line 319d is formed on the Y direction according to each row and extends.In addition, wiring 319e is connected with transmission gate electrode 313 via contact site 313a.In addition, other that read gate line 319d and wiring 319e constitute respectively with above-mentioned first execution mode read gate line 20a and wiring 19d is identical.
In addition, in the 4th execution mode, on the upper surface of ground floor wiring, form second layer wiring across not shown interlayer dielectric.As shown in figure 23, resetting gate polar curve 20b and row selection wire 20c are made of second layer wiring.In addition, on the upper surface of second layer wiring, form three-layer routing across not shown interlayer dielectric.As shown in figure 24, vdd line 21a and holding wire 21b are made of three-layer routing.In addition, on the upper surface of three-layer routing, form the 4th layer of wiring across not shown interlayer dielectric.As shown in figure 21, wiring 22a is made of the 4th layer of wiring.
In addition, other formations of the 4th execution mode are identical with above-mentioned first execution mode.
In the 4th execution mode, as mentioned above, by in photodiode portion 4 with increase and only form 1 between times gate electrode 14 and transmit gate electrode 313, thereby the miniaturization of cmos image sensor 400 can be realized, and the area of the photodiode portion 4 in the cmos image sensor 400 can be increased.
In addition, other effects of the 4th execution mode are identical with above-mentioned first and second execution mode.
In addition, this disclosed execution mode, all points all are illustration, and should think to be used for limiting of the present invention.Scope of the present invention is not by the explanation of above-mentioned execution mode but represents by claim, and further comprise with claim equivalent and scope in all changes.
For example, in above-mentioned first～the 4th execution mode, illustration form the example of photodiode portion 4, but the present invention is defined in this, also can on the upper surface of photodiode portion, form the transmission gate electrode that is used for transmitting the electronics of accumulating in the photodiode portion.
In addition, in above-mentioned first and second execution mode, illustration by form transmitting gate electrode 11 in order, 12,13 and increase times gate electrode 14, thereby dispose photodiode portion 4 in order, photodiode separates partition wall, accumulate well temporarily, electric charge transmits the example of partition wall and electric charge accumulation well, but the present invention is defined in this, also can form in order and transmit gate electrode 11, increase times gate electrode 14, transmit gate electrode 13 and 12, dispose photodiode portion thus in order, photodiode separates partition wall, electric charge accumulation well, electric charge transmits partition wall and accumulates well temporarily.
In addition, in above-mentioned first～the 3rd execution mode, illustration by supplying with the clock signal φ 3 of H level or L level to transmitting gate electrode 13, thereby will transmit the example that transmission raceway groove 3 under the gate electrode 13 is adjusted into the current potential of about 4V or about 1V, but the present invention is defined in this, also can pass through to supply with the voltage signal of regulation, thereby the transmission raceway groove 3 that will transmit under the gate electrode 13 is adjusted into certain current potential (for example about 2V) to transmitting gate electrode 13.
In addition, in above-mentioned first～the 3rd execution mode, illustration by the 4th layer of wiring form the wiring 22b that is connected with transmission gate electrode 12, with increase the wiring 22a (222a) that times gate electrode 14 (214) is connected, but the present invention is defined in this, for example also can form the wiring 22b that be connected, thereby only form and increase the wiring 22a (222a) that times gate electrode 14 (214) is connected by the 4th layer of wiring by the wiring of the specified layer beyond the 4th layer of wiring with transmission gate electrode 12.
In addition, in above-mentioned first～the 4th execution mode, illustration form the example of 1 reset gate electrode according to each pixel, but the present invention is defined in this, also can be according to not having row or not every row to form reset gate electrode.
In addition, in above-mentioned first and second execution mode, illustration transmitting gate electrode 11,12,13 and reading under the situation of gate electrode 15 conducting states, transmit gate electrode 11,12,13 and read the example that transmission raceway groove 3 under the gate electrode 15 becomes the state of the current potential that is adjusted to about 4V, but the present invention is defined in this, also can transmit gate electrode 11,12,13 and read under the situation of gate electrode 15 conducting states, transmission gate electrode 11,12,13 and the transmission raceway groove of reading under the gate electrode 15 3 become the state that is adjusted to different respectively current potentials.
In addition, in above-mentioned first～the 4th execution mode, illustration form the example that transmits raceway groove, photodiode portion, floating diffusion zone, reset drain portion and efferent on the surface of p type silicon substrate, but the present invention is defined in this, also p type well area be can form, and transmission raceway groove, photodiode portion, floating diffusion zone, reset drain portion and efferent formed on the surface of this p type well area on the surface of n type silicon substrate.
In addition, in above-mentioned first～the 4th execution mode, illustration adopt the example of electronics as electric charge, but the present invention is defined in this, the polarity of conductivity type that also can be by making substrate impurity and the voltage that applies is all opposite, thereby adopts the hole to be used as electric charge.
Claims (20)
1. camera head comprises:
Electric charge increase portion, it is used to make electric charge to increase;
First electrode, it is used to apply and will be adjusted into the voltage of regulation current potential with described electric charge increase portion adjacent areas;
Second electrode, it is configured to adjacent with described first electrode, is used to be applied to the voltage that described electric charge increase portion increases electric charge;
First wiring, it is formed on the layer of regulation, and is used for supplying with signal to described first electrode; With
Second wiring, it is formed on the layer different with the layer of described regulation, and is used for supplying with signal to described second electrode.
2. camera head according to claim 1 is characterized in that,
Described first wiring is formed with described second wiring and intersects.
3. camera head according to claim 1 is characterized in that, also comprises:
Accumulate portion, it is used for accumulating the electric charge that transmits to described electric charge increase portion temporarily, and transmits the described electric charge of accumulating; With
Third electrode, it is arranged on and forms described top of accumulating the zone of portion, is used for applying being created in the voltage that the required electric field of electric charge is accumulated by the described portion of accumulating.
4. camera head according to claim 1 is characterized in that, also comprises:
Maintaining part, it is in order to keep electric charge with electric charge as signal output; With
The 4th electrode, it is used to apply generation electric charge is sent to the voltage of the electric field of described maintaining part,
Total at least described maintaining part in a plurality of pixels.
5. camera head according to claim 4 is characterized in that,
In a plurality of described pixels, except the also total described electric charge increase of described maintaining part portion, described second electrode and described the 4th electrode.
6. camera head according to claim 1 is characterized in that, also comprises:
Maintaining part, it is in order to keep electric charge with electric charge as signal output;
The 4th electrode, it is used to apply make electric charge is sent to the voltage that the electric field of described maintaining part produces; With
The 3rd wiring, it is formed on the layer different with the layer that forms described second wiring, and is used for supplying with signal to described the 4th electrode.
7. camera head according to claim 6 is characterized in that,
Described the 3rd wiring is formed with described second wiring and intersects.
8. camera head according to claim 6 is characterized in that,
Described the 3rd wiring be formed between layer that forms described first wiring and the layer that forms described second wiring layer on.
9. camera head according to claim 3 is characterized in that,
Also comprise the 4th wiring, it is formed by the layer identical with the layer that forms described second wiring, and is used for supplying with signal to described third electrode.
10. camera head according to claim 9 is characterized in that,
Described the 4th wiring is formed with described first wiring and intersects.
11. camera head according to claim 9 is characterized in that, also comprises:
Maintaining part, it is in order to keep electric charge with electric charge as signal output;
The 4th electrode, it is used to apply make electric charge is sent to the voltage that the electric field of described maintaining part produces; With
The 3rd wiring, it is used for supplying with signal to described the 4th electrode; With
Holding wire, it is exported the electric charge that keeps in the described maintaining part as signal,
Described holding wire be formed between layer that forms described second wiring and described the 4th wiring and the layer that forms described the 3rd wiring layer on.
12. camera head according to claim 11 is characterized in that,
Described holding wire is formed respectively and intersects with described second wiring, described the 3rd wiring and described the 4th wiring.
13. camera head according to claim 3 is characterized in that, also comprises:
Photoelectric conversion part, it generates electric charge; With
The 5th electrode, it is located between described photoelectric conversion part and the described third electrode, and the electric charge that is used for generating is sent to the described portion of accumulating.
14. camera head according to claim 13 is characterized in that,
Also comprise the 5th wiring, it is formed by the layer identical with the layer that forms described first wiring, and is used for supplying with signal to described the 5th electrode.
15. camera head according to claim 14 is characterized in that,
Described the 5th wiring is formed with described second wiring and intersects.
16. camera head according to claim 14 is characterized in that,
Under the situation of overlooking, the described the 5th be routed in the nonoverlapping state of described photoelectric conversion part The corresponding area under form along the outer edge of described photoelectric conversion part.
17. camera head according to claim 1 is characterized in that,
Also comprise a plurality of pixels,
According to each described pixel described electric charge increase portion, described first electrode and described second electrode are set.
18. camera head according to claim 1 is characterized in that,
Described first wiring constitutes as the ground floor wiring layer,
Described second wiring constitutes as the 4th layer of wiring layer.
19. camera head according to claim 18 is characterized in that,
First wiring that is made of described ground floor wiring layer and be formed across a plurality of layer by second wiring that described the 4th wiring layer constitutes intersects mutually.
20. a camera head, it comprises:
Electric charge increases mechanism, and it is used to make electric charge to increase;
First electrode, it is used to apply will increase the voltage that mechanism's adjacent areas is adjusted into the regulation current potential with described electric charge;
Second electrode, it is configured to adjacent with described first electrode, and being used to be applied to described electric charge increases the voltage that mechanism increases electric charge;
First wiring, it is formed on the layer of regulation, and is used for supplying with signal to described first electrode; With
Second wiring, it is formed on the layer different with the layer of described regulation, and is used for supplying with signal to described second electrode.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007022371 | 2007-01-31 | ||
| JP2007022371A JP2008192648A (en) | 2007-01-31 | 2007-01-31 | Imaging device |
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| CN101236982A true CN101236982A (en) | 2008-08-06 |
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| CNA2008100085146A Pending CN101236982A (en) | 2007-01-31 | 2008-01-23 | Image pick-up device |
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| US (1) | US7642499B2 (en) |
| JP (1) | JP2008192648A (en) |
| CN (1) | CN101236982A (en) |
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| CN104115271A (en) * | 2012-02-09 | 2014-10-22 | 株式会社电装 | Solid-state imaging device and method for driving same |
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| CN111405210A (en) * | 2020-03-20 | 2020-07-10 | 中国电子科技集团公司第四十四研究所 | Pixel-level multiplication internal line frame transfer CCD pixel structure |
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| JP2008060550A (en) * | 2006-07-31 | 2008-03-13 | Sanyo Electric Co Ltd | Imaging apparatus |
| US7969492B2 (en) * | 2007-08-28 | 2011-06-28 | Sanyo Electric Co., Ltd. | Image pickup apparatus |
| JP2009130669A (en) * | 2007-11-26 | 2009-06-11 | Sanyo Electric Co Ltd | Imaging apparatus |
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| JP3483261B2 (en) | 1992-07-10 | 2004-01-06 | テキサス インスツルメンツ インコーポレイテツド | Image sensor |
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| US20060128149A1 (en) * | 2004-12-15 | 2006-06-15 | Dongbuanam Semiconductor Inc. | Method for forming a metal wiring in a semiconductor device |
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2007
- 2007-01-31 JP JP2007022371A patent/JP2008192648A/en not_active Withdrawn
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2008
- 2008-01-23 CN CNA2008100085146A patent/CN101236982A/en active Pending
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| CN111405210B (en) * | 2020-03-20 | 2022-01-28 | 中国电子科技集团公司第四十四研究所 | Pixel-level multiplication internal line frame transfer CCD pixel structure |
Also Published As
| Publication number | Publication date |
|---|---|
| US7642499B2 (en) | 2010-01-05 |
| JP2008192648A (en) | 2008-08-21 |
| US20080179495A1 (en) | 2008-07-31 |
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