CN113488494B - Pixel multiplication and signal transfer control method of internal line frame transfer CCD - Google Patents
Pixel multiplication and signal transfer control method of internal line frame transfer CCD Download PDFInfo
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Abstract
The invention discloses a pixel multiplication and signal transfer control method of an internal line frame transfer CCD, which comprises a photosensitive area receiving photon irradiation and generating photoelectron signals, photoelectron signal integration and multiplication, photoelectron signal transfer, photoelectron signal fast state transfer and photoelectron signal reading.
Description
Technical Field
The invention relates to the technical field of CCD pixel multiplication and signal transfer modes, in particular to a pixel multiplication and signal transfer control method for an internal line frame transfer CCD.
Background
The conventional CCDs are generally classified into Linear array type CCDs (Linear CCDs), full Frame Transfer type CCDs (Full Frame Transfer CCDs), frame Transfer type CCDs (Frame Transfer CCDs), internal line Transfer type CCDs (Interline Transfer CCDs), time Delay integration CCDs (Time Delay integration CCDs), electron multiplication CCDs (electron multiplication CCDs), and the like, and each type of CCD has performance characteristics and spectrum detection advantages, and is applied to different scenes and fields.
An inline Frame transfer CCD (IFT CCD) is a newly proposed CCD structure. Based on the pixel-level multiplication IFT CCD principle, when the IFT CCD detects a target object with weak signals in the light integration stage, the detected signals are amplified by the pixel multiplication function, and the detection sensitivity of the IFT CCD is improved. When the pixel of the IFT CCD is multiplied, the pixel multiplication grid needs to apply higher voltage, the high and low level switching of the driving of the pixel transfer grid and the vertical transfer grid below the pixel multiplication grid can be influenced, and larger crosstalk is introduced, so that the overall function of the IFT CCD is influenced.
Disclosure of Invention
The invention provides a pixel multiplication and signal transfer control method of an internal line frame transfer CCD (charge coupled device), which aims to solve the problem that the integral function of an IFT (integrated circuit transfer) CCD is influenced by introducing large crosstalk when a higher voltage is applied to a pixel multiplication grid in the prior art.
In order to solve the above problems, the present invention provides a pixel multiplication and signal transfer control method for an internal line frame transfer CCD, comprising the following steps:
s1: controlling a photosensitive area of the inner line frame transfer CCD to receive photon irradiation and generate a photoelectron signal;
s2: applying high level to the pixel multiplication grid and keeping, transferring the photoelectron signal to a potential well under the pixel multiplication grid from the photosensitive region under the drive of an electric field generated by the high level of the pixel multiplication grid, realizing the multiplication of the photoelectron signal in the transfer process, applying low level to the pixel transfer grid and keeping, and blocking the photoelectron signal at one side of the pixel multiplication grid;
s3: after the photoelectron signal multiplication is finished, switching the pixel multiplication grid from a high level to a low level and switching the pixel transfer grid from the low level to the high level and keeping, simultaneously applying the high level to the driving phase of the first vertical transfer grid V2 and keeping, and transferring the multiplied photoelectron signal from the pixel multiplication grid to the potential well of the driving phase of the first vertical transfer grid V2 along the signal transfer channel;
s4: simultaneously applying the same fast state transfer pulse to the first vertical transfer gate V1 driving phase, the first vertical transfer gate V2 driving phase and the storage gate, and sequentially transferring the photoelectron signals in the first vertical transfer gate of each pixel structure downwards to the storage gate at the same fast state transfer frequency;
s5: and controlling the horizontal shift register to read out the photoelectronic signals temporarily stored in the storage grid line by line.
Further, in step S1, the internal line frame transfer CCD includes an internal line transfer structure pixel array, a frame transfer storage structure array, and a second vertical transfer gate, which are sequentially arranged from top to bottom, a horizontal shift register is connected below the second vertical transfer gate to control the reading of the photoelectron signals in the frame transfer storage structure array line by line, the end of the horizontal shift register is connected to a multiplication shift register through an overscan bit, the end of the multiplication shift register is connected to a horizontal output gate through an overscan bit, and the horizontal output gate is connected to a read-out amplifier through an output node.
Furthermore, the pixel array of the internal line transfer structure comprises a plurality of pixel structures, and each pixel structure comprises a photosensitive area, a trench resistor arranged on the outer edge of the photosensitive area in a surrounding manner, and a first vertical transfer gate arranged on one side of the photosensitive area; the first vertical transfer gate is provided with a first vertical transfer gate V1 driving phase and a first vertical transfer gate V2 driving phase which are sequentially arranged from top to bottom, and a transfer barrier and a pixel transfer gate are sequentially connected in a stacked mode from bottom to top on one side, close to the photosensitive area, of the first vertical transfer gate V1 driving phase or the first vertical transfer gate V2 driving phase; and a pixel multiplication structure is also arranged in the photosensitive area, and a pixel multiplication grid is connected between the pixel multiplication structure and the pixel transfer grid.
Furthermore, the frame transfer storage structure array comprises a plurality of storage grids distributed in an array, the storage grids are correspondingly arranged below each row of pixel structures, and each storage grid is provided with a storage grid SG1 driving phase and a storage grid SG2 driving phase which are sequentially arranged from top to bottom.
Further, in step S2, the high value applied to the cell multiplication gate is 30V, and the low value applied to the cell transfer gate is-10V.
Further, in step S3, when the pixel multiplication grid is switched from the high level to the low level, the low level value is 0V; when the pixel transfer gate is switched from a low level to a high level, the high level value is 5V; and the high level value applied to the first vertical transfer gate V2 driving phase is-10V.
Further, in step S4, the fast transition frequency is 5mhz to 10mhz.
The invention completes the processes of photoelectron signal collection, multiplication, transfer, fast state transfer, reading and the like of the internal line frame transfer CCD by controlling the mutual matching of the driving time sequences of the pixel multiplication grid, the pixel transfer grid, the V1 driving phase and the V2 driving phase of the first vertical transfer grid and the SG1 driving phase and the SG2 driving phase of the storage grid; under the drive of the fast state transfer pulse, the integration of the photosensitive area and the line-by-line transfer of signals are isolated from the aspect of time, and the problem that the performance of a device is reduced due to the fact that high level of a pixel element multiplication grid influences the high-low level switching of the pixel element transfer grid and a first vertical transfer grid in the process of light integration of the photosensitive area and large crosstalk is introduced is solved.
Drawings
Fig. 1 is a flowchart of a pixel multiplication and signal transfer control method of an internal line frame transfer CCD according to the present invention.
Fig. 2 is a schematic structural view of an inline frame transfer CCD.
FIG. 3 is a schematic structural diagram of the pixel array and the frame transfer memory structure array of the internal line transfer structure in FIG. 2.
Fig. 4 is a schematic diagram of the multiplication and transfer process of photoelectron signals in an inline frame transfer CCD.
The reference numbers of the specification are as follows:
the pixel structure comprises an internal line transfer structure pixel array 101, a frame transfer storage structure array 102, a second vertical transfer gate 105, a horizontal shift register 106, an overscan bit 107, a multiplication shift register 108, a horizontal output gate 109, an output node 110, a sense amplifier 111, a photosensitive region 201, a channel resistor 202, a first vertical transfer gate V1 driving phase 203, a first vertical transfer gate V2 driving phase 204, a pixel multiplication structure 205, a pixel multiplication gate 206, a pixel transfer gate 207, a storage gate SG1 driving phase 208, a storage gate SG2 driving phase 209, a first pixel structure 401, a second pixel structure 402, a third pixel structure 403 and a fourth pixel structure 404.
Detailed Description
The invention will be further explained with reference to the drawings.
In the description of the present invention, unless otherwise specified and limited, it should be noted that the term "connected" should be interpreted broadly, for example, as being mechanically or electrically connected, or as being interconnected between two elements, directly or indirectly through an intermediate medium, and the specific meaning of the term is understood by those skilled in the art according to the specific situation.
Fig. 1 is a flow chart of a pixel multiplication and signal transfer control method of an internal line frame transfer CCD according to the present invention. The pixel multiplication and signal transfer control method of the internal line frame transfer CCD of the embodiment divides the working process of the internal line frame transfer CCD into the processes of collection, integration (multiplication), transfer, fast state transfer, reading and the like of photoelectronic signals in the driving time sequence, thereby ensuring the weak target detection performance of the internal line frame transfer CCD and effectively improving the detection sensitivity of the internal line frame transfer CCD. Specifically, the present embodiment includes the following steps:
s1: and detecting photoelectron signals.
The photosensitive area 201 of the inline frame transfer CCD is controlled to receive photon illumination and generate photoelectron signals.
Fig. 2 is a schematic structural diagram of an internal line frame transfer CCD. The internal line frame transfer CCD comprises an internal line transfer structure pixel array 101, a frame transfer storage structure array 102 and a second vertical transfer grid 105 which are sequentially arranged from top to bottom, wherein the internal line transfer structure pixel array 101 is used for detecting, integrating (multiplying) and transferring photoelectron signals, and the internal line transfer structure pixel array 101 and the frame transfer storage structure array 102 jointly realize the fast state transfer of the photoelectron signals and temporarily store the photoelectron signals in the frame transfer storage structure array 102. A horizontal shift register 106 is connected below the second vertical transfer gate 105, and the horizontal shift register 106 is used for controlling the photoelectronic signals temporarily stored in the frame transfer storage structure array 102 to be read out row by row. The tail end of the horizontal shift register 106 is connected with a multiplication shift register 108 through an overscan bit 107, the tail end of the multiplication shift register 108 is connected with a horizontal output grid 109 through the overscan bit 107, the horizontal output grid 109 is connected with a read-out amplifier 111 through an output node 110, and photoelectron signals are read out row by the horizontal shift register 106 and then input into a post-stage circuit after being processed by the multiplication shift register 108 and the read-out amplifier 111.
FIG. 3 is a schematic structural diagram of an internal line transfer structure pixel array 101 and a frame transfer memory structure array 102. The internal line transfer structure pixel array 101 comprises a plurality of pixel structures, the pixel structures are distributed in a rectangular array, each pixel structure comprises a photosensitive area 201, a channel resistor 202 arranged on the outer edge of the photosensitive area 201 in a surrounding mode, and a first vertical transfer gate arranged on one side of the photosensitive area 201. The first vertical transfer gate has at least two driving phases sequentially arranged from top to bottom, and in this embodiment, the first vertical transfer gate has two driving phases, namely a first vertical transfer gate V1 driving phase 203 and a first vertical transfer gate V2 driving phase 204. A transfer barrier (not shown) and a pixel transfer gate 207 are sequentially stacked and connected from bottom to top on the side of the first vertical transfer gate V1 driving phase 203 or the first vertical transfer gate V2 driving phase 204 close to the photosensitive region 201, and in this embodiment, the pixel transfer gate 207 is disposed on the side of the first vertical transfer gate V2 driving phase 204. A pixel multiplication structure 205 is further arranged in the photosensitive region 201, and a pixel multiplication grid 206 is connected between the pixel multiplication structure 205 and the pixel transfer grid 207.
The frame transfer memory structure array 102 includes a plurality of memory gates distributed in an array, the memory gates are correspondingly disposed below each row of pixel structures, and each memory gate has at least two driving phases sequentially disposed from top to bottom. In this embodiment, the memory gate has two driving phases, namely a memory gate SG1 driving phase 208 and a memory gate SG2 driving phase 209.
Fig. 4 is a schematic diagram showing the multiplication and transfer process of the photoelectron signal in the in-line frame transfer CCD. In this embodiment, four pixel structures are taken as an example for explanation, in fig. 4, the transfer paths of photoelectron signals in the first pixel structure 401 and the second pixel structure 402 are (1), (2), (3), (4), (5) and (6), and the transfer paths of photoelectron signals in the third pixel structure 403 and the fourth pixel structure 404 are (7), (8) and (9).
S2: and integrating the photoelectrons to realize photoelectron signal multiplication.
Specifically, in the light integration process, a high level is applied to the pixel multiplication gate 206 and maintained, and a low level is applied to the pixel transfer gate 207 and maintained, and in the present embodiment, the high level value applied to the pixel multiplication gate 206 is preferably 30V, and the low level value applied to the pixel transfer gate 207 is preferably-10V.
With continued reference to fig. 4, the portion (1) in fig. 4 is the light integration process. The photoelectron signal is driven by an electric field generated by a high level of the pixel multiplication gate 206 and transferred to a potential well under the pixel multiplication gate 206 from the photosensitive region 201, and in the photoelectron signal transfer process, the photoelectron signal generates an avalanche multiplication effect due to a strong electric field generated by the pixel multiplication gate 206, so that the photoelectron signal is increased, and meanwhile, due to a low level applied on the pixel transfer gate 207, the photoelectron signal in the pixel multiplication gate 206 is blocked at one side of the pixel multiplication gate 206 by a transfer potential barrier under the pixel transfer gate 207 and is not transferred to an adjacent first vertical transfer gate V2 driving phase 204, so that the photoelectron signal multiplication is realized.
S3: photoelectron signal transfer.
Specifically, after the photoelectron signal multiplication is completed, the pixel multiplication gate 206 is switched from a high level to a low level and the pixel transfer gate 207 is switched from a low level to a high level and held, and simultaneously, a high level is applied to the first vertical transfer gate V2 driving phase 204 and held; in the present embodiment, when the pixel multiplication gate 206 is switched from a high level to a low level, the low level value is preferably 0V; when the pixel transfer gate 207 is switched from a low level to a high level, the high level value is preferably 5V; and the high level value applied to the first vertical transfer gate V2 driving phase 204 is preferably-10V. Through the mutual matching of the driving time sequences of the pixel multiplication gate 206, the pixel transfer gate 207 and the first vertical transfer gate V2 driving phase 204 (that is, the switching of high and low levels among the pixel multiplication gate 206, the pixel transfer gate 207 and the first vertical transfer gate V2 driving phase 204 is controlled according to the driving time sequences), the multiplied photoelectron signal enters the potential well of the first vertical transfer gate V2 driving phase 204 through the transfer potential barrier of the pixel transfer gate 207, and the photoelectron signal transfer is completed.
Continuing with fig. 4, part (2) of fig. 4 is the optoelectronic signal transferring process. Because the pixel transfer gate 207 is switched from low level to high level, a signal transmission channel for transferring a photoelectron signal from the pixel multiplication gate 206 to the first vertical transfer gate is opened, and because the pixel multiplication gate 206 is switched from high level to low level, a transfer potential barrier of the pixel multiplication structure 205 is raised, so that the multiplied photoelectron signal is transferred from the pixel multiplication gate 206 to a potential well of the first vertical transfer gate V2 driving phase 204 along the signal transmission channel; meanwhile, due to the high level applied to the first vertical transfer gate V2 driving phase 204, the potential well under the first vertical transfer gate V2 driving phase 204 can receive the photoelectron signal transferred by the pixel multiplication gate 206, and the transfer of the photoelectron signal is realized.
S4: the photoelectron signal is transferred fast.
Specifically, the same fast state transfer pulse is simultaneously applied to the first vertical transfer gate and the storage gate, and the photoelectron signals in the first vertical transfer gate of each pixel structure are sequentially transferred downwards into the storage gate at the same fast state transfer frequency.
Continuing with fig. 4, in fig. 4 (3) (4) (5) (6) are the fast state transfer processes for the photoelectron signal in first pixel structure 401 and second pixel structure 402, and (9) in r is the fast state transfer processes for third pixel structure 403 and fourth pixel structure 404. The fast-state transfer process of the photoelectron signal, i.e., the process of transferring the photoelectron signal generated by the photosensitive region 201 to the corresponding storage gate at a relatively fast-state transfer frequency. In the embodiment, the fast state transition frequency is 5MHz to 10MHz.
In the fast-state transfer of the photoelectron signal, the photoelectron signal in the first vertical transfer gate V2 driving phase 204 of the first row of pixel structures (i.e., the first pixel structure 401 and the second pixel structure 402 in this embodiment) is transferred to the first storage gate SG1 driving phase 208, which is the beginning of the fast-state transfer; the photoelectron signal under the first vertical transfer gate V1 driving phase 203 in the last row (i.e., the third pixel structure 403 and the fourth pixel structure 404 in this embodiment) is transferred to the structure under the last storage gate SG2 driving phase 209 for fast state transfer.
Specifically, when photoelectron signals in the first and second pixel element structures 401 and 402 are fast-transferred along the paths of (3), (4), (5), (6), the fast-state transfer pulse applies a high level to the first vertical transfer gate V2 drive phase 204 of the first and second pixel element structures 401 and 402, while applying a low level to the first vertical transfer gate V1 drive phase 203 of the corresponding next pixel element structure (i.e., the fourth pixel element structure 404 and the third pixel element structure 403), so that the potential barrier under the first vertical transfer gate V1 drive phase 203 is in an off state, and the photoelectron signals are blocked in the potential barrier of the first vertical transfer gate V2 drive phase 204 of the first and second pixel element structures 401 and 402; then, the fast state transfer pulse controls the first vertical transfer gate V1 driving phase 203 of the next pixel (the fourth pixel structure 404 and the third pixel structure 403) to be switched from a low level to a high level, and a potential barrier under the first vertical transfer gate V1 driving phase 203 is in an open state, so that the photoelectron signals in the potential wells of the first vertical transfer gate V2 driving phase 204 of the first pixel structure 401 and the second pixel structure 402 are transferred to the potential well of the first vertical transfer gate V1 driving phase 203 of the next pixel structure; the control process is then repeated until the photo-electric signal is transferred to the storage gate.
When the photoelectron signals in third pixel element structure 403 and fourth pixel element structure 404 are fast-state transferred along the path in (9) r, the fast-state transfer pulse applies a high level to first vertical transfer gate V2 driving phase 204 of third pixel element structure 403 and fourth pixel element structure 404, and simultaneously applies a low level to corresponding storage gate SG1 driving phase 208 of the pixel element structure, blocking the photoelectron signals in the potential wells of first vertical transfer gate V2 driving phase 204 of third pixel element structure 403 and fourth pixel element structure 404; the control fast pulse then applies a high level to the corresponding storage gate SG1 drive phase 208, causing the photoelectron signal to be transferred into the storage gate.
S5: the optoelectronic signals are read out row by row.
After the photoelectron signal is transferred in a fast state, the photoelectron signal is temporarily stored in the storage gate, and then the horizontal shift register 106 is controlled to read the photoelectron signal temporarily stored in the storage gate line by line, and in the process that the photoelectron signal is read line by line, the photosensitive area 201 can simultaneously perform the photoelectron signal detection and integration process of the next frame.
According to the pixel multiplication and signal transfer control method of the internal line frame transfer CCD, when a target object with weak detection signals needs a pixel multiplication function to amplify the detected signals so as to improve the detection sensitivity, the problem that the performance of the device is reduced due to the fact that high voltage is applied to the pixel multiplication grid 206 to influence other functional modules such as the pixel transfer grid 207 under the pixel multiplication grid 206 and the like to introduce large crosstalk is solved, the detection sensitivity of the internal line frame transfer CCD can be effectively improved, and the adaptability of the complex environment of the pixel level multiplication internal line frame transfer CCD to object detection and higher imaging detection performance are improved.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The above description is only an embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures made by using the contents of the present specification and the drawings can be directly or indirectly applied to other related technical fields, and are also within the scope of the present invention.
Claims (4)
1. A pixel multiplication and signal transfer control method of an internal line frame transfer CCD is characterized by being used for controlling the internal line frame transfer CCD to carry out pixel multiplication and signal transfer, wherein the internal line frame transfer CCD comprises an internal line transfer structure pixel array, a frame transfer storage structure array and a second vertical transfer gate which are sequentially arranged from top to bottom;
the pixel array of the internal line transfer structure comprises a plurality of pixel structures, and each pixel structure comprises a photosensitive area, a trench resistor arranged on the outer edge of the photosensitive area in a surrounding mode and a first vertical transfer gate arranged on one side of the photosensitive area; the first vertical transfer gate is provided with a first vertical transfer gate V1 driving phase and a first vertical transfer gate V2 driving phase which are sequentially arranged from top to bottom, and a transfer potential barrier and a pixel transfer gate are sequentially connected in a stacked manner from bottom to top on one side, close to the photosensitive area, of the first vertical transfer gate V1 driving phase or the first vertical transfer gate V2 driving phase; a pixel multiplication structure is further arranged in the photosensitive area, and a pixel multiplication grid is connected between the pixel multiplication structure and the pixel transfer grid;
the frame transfer storage structure array comprises a plurality of storage grids which are distributed in an array manner, the storage grids are correspondingly arranged below each row of pixel structures, and each storage grid is provided with a storage grid SG1 driving phase and a storage grid SG2 driving phase which are sequentially arranged from top to bottom;
a horizontal shift register for controlling photoelectron signals in the frame transfer storage structure array to be read line by line is connected below the second vertical transfer gate, the tail end of the horizontal shift register is connected with a multiplication shift register through an overscan bit, the tail end of the multiplication shift register is connected with a horizontal output gate through an overscan bit, and the horizontal output gate is connected with a read-out amplifier through an output node;
the pixel multiplication and signal transfer control method of the internal line frame transfer CCD comprises the following steps:
s1: controlling a photosensitive area of the inner line frame transfer CCD to receive photon irradiation and generate a photoelectron signal;
s2: applying high level to the pixel multiplication grid and keeping, transferring the photoelectron signal to a potential well under the pixel multiplication grid from the photosensitive region under the drive of an electric field generated by the high level of the pixel multiplication grid, realizing the multiplication of the photoelectron signal in the transfer process, applying low level to the pixel transfer grid and keeping, and blocking the photoelectron signal at one side of the pixel multiplication grid;
s3: after the photoelectron signal is multiplied, switching the pixel multiplication grid from a high level to a low level and switching the pixel transfer grid from the low level to the high level and keeping the pixel transfer grid, applying the high level to the first vertical transfer grid V2 driving phase and keeping the high level, and transferring the multiplied photoelectron signal from the pixel multiplication grid to a potential well of the first vertical transfer grid V2 driving phase along a signal transfer channel;
s4: simultaneously applying the same fast state transfer pulse to the first vertical transfer gate V1 driving phase, the first vertical transfer gate V2 driving phase and the storage gate, and sequentially transferring the photoelectron signals in the first vertical transfer gate of each pixel structure downwards to the storage gate at the same fast state transfer frequency; the fast state transfer pulse is used for isolating multiplication of photoelectron signals of the photosensitive area from photoelectron signal transfer along the signal transmission channel in time;
s5: and controlling the horizontal shift register to read out the photoelectronic signals temporarily stored in the storage grid line by line.
2. The method of claim 1, wherein in step S2, the high level value applied to the pixel multiplication gate is 30V, and the low level value applied to the pixel transfer gate is-10V.
3. The method for pixel multiplication and signal transfer control of an internal line frame transfer CCD as claimed in claim 1, wherein in step S3, when the pixel multiplication grid is switched from high level to low level, the low level value is 0V; when the pixel transfer grid is switched from a low level to a high level, the high level value is 5V; and a high level value applied to the first vertical transfer gate V2 driving phase is-10V.
4. The method for pixel multiplication and signal transfer control of an internal line frame transfer CCD (charge coupled device) according to claim 1, wherein in the step S4, the fast state transfer frequency is 5MHz to 10MHz.
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| JP2008192648A (en) * | 2007-01-31 | 2008-08-21 | Sanyo Electric Co Ltd | Imaging device |
| US9100600B2 (en) * | 2013-07-10 | 2015-08-04 | Samsung Electronics Co., Ltd. | Anti-blooming shutter control in image sensors |
| CN106791499B (en) * | 2016-11-22 | 2019-06-18 | 北京空间机电研究所 | A method of realizing that improving electron multiplication CCD camera exports signal noise ratio (snr) of image |
| CN111372017B (en) * | 2020-03-20 | 2022-03-15 | 中国电子科技集团公司第四十四研究所 | Pixel multiplication internal line frame transfer CCD with anti-halo structure |
| CN111405210B (en) * | 2020-03-20 | 2022-01-28 | 中国电子科技集团公司第四十四研究所 | Pixel-level multiplication internal line frame transfer CCD pixel structure |
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| EP2613171A1 (en) * | 2008-01-09 | 2013-07-10 | Surf Technology AS | Nonlinear elastic imaging with two-frequency elastic pulse complexes |
| CN103424198A (en) * | 2013-07-29 | 2013-12-04 | 西北核技术研究所 | Interline-transfer charge coupled device (IT-CCD) pulse laser repetition frequency measuring method based on main facula blanking technology |
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