CN111405210B - Pixel-level multiplication internal line frame transfer CCD pixel structure - Google Patents
Pixel-level multiplication internal line frame transfer CCD pixel structure Download PDFInfo
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- CN111405210B CN111405210B CN202010199462.6A CN202010199462A CN111405210B CN 111405210 B CN111405210 B CN 111405210B CN 202010199462 A CN202010199462 A CN 202010199462A CN 111405210 B CN111405210 B CN 111405210B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/711—Time delay and integration [TDI] registers; TDI shift registers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The invention relates to an IFT CCD pixel structure with pixel level multiplication, in particular to a pixel level multiplication internal line frame transfer CCD pixel structure, which comprises a substrate, a pixel multiplication structure and a pixel vertical transfer area, wherein the pixel multiplication structure is surrounded by a channel resistor and is provided with an opening at one side, and a pixel multiplication grid is arranged above the pixel multiplication structure and the channel resistor opening; the pixel vertical transfer region is arranged on one side of the pixel photosensitive region and consists of a pixel vertical transfer channel and a pixel vertical transfer gate above the channel, a pixel vertical transfer gate lower potential barrier is arranged below the pixel vertical transfer gate, the pixel vertical transfer channel is divided into a plurality of independent parts by the pixel vertical transfer gate lower potential barrier, and the vertical transfer of photoelectric signals in the pixel is controlled by the pixel vertical transfer gate and the pixel lower potential barrier; the invention can realize the improvement of the detection sensitivity at the front-end pixel level and can detect dim light and even single photon signals.
Description
Technical Field
The present invention relates to a Charge Coupled Device (CCD) structure, and more particularly, to an internal Frame Transfer CCD (IFT CCD) pixel structure with pixel level multiplication.
Background
The charge coupled device is a miniature image sensor, has both photoelectric conversion function and signal storage, transfer, conversion and other functions, and can convert images distributed in a spatial domain into electric signals distributed discretely in a time domain. The method has the advantages of high sensitivity, wide spectral response, large dynamic range, small pixel size, high geometric precision, good imaging quality, vibration resistance, radiation resistance and the like.
The conventional CCDs are generally classified into linear array type CCDs (linear CCDs), Full Frame Transfer type CCDs (Full Frame Transfer CCDs), Frame Transfer type CCDs (Frame Transfer CCDs), Interline Transfer type CCDs (Interline Transfer CCDs), Time Delay Integration CCDs (Time Delay Integration CCDs), Electron multiplication CCDs (Electron multiplication CCDs), and the like, each type of CCD has its own performance characteristics and spectrum detection advantages, and is applied to different scenes and fields.
An internal Frame Transfer Charged Coupled Device (IFT CCD) is a newly proposed CCD structure, based on the IFT CCD principle, the pixel level multiplication function is more easily realized, and the pixel level multiplied IFT CCD pixel structure is different from that of the conventional internal Frame Transfer CCD. In order to better realize the pixel multiplication function of the IFT CCD, the invention creatively provides an IFT CCD pixel structure with pixel level multiplication.
Disclosure of Invention
In order to better realize the Pixel multiplication function of the IFT CCD, the invention creatively provides a Pixel level multiplication inner line frame transfer CCD Pixel structure, which comprises a substrate, a Pixel Multiplication (PMD) structure and a Pixel vertical transfer area, wherein the Pixel multiplication structure is surrounded by a channel resistor and is provided with an opening on one side, and a Pixel Multiplication Gate (PMG) is arranged above the Pixel multiplication structure and the opening of the channel resistor; the Pixel Vertical Transfer region is arranged on one side of the Pixel photosensitive region and consists of a Pixel Vertical Transfer channel and a Pixel Vertical Transfer Gate (VTG) above the channel, a Pixel Vertical Transfer Gate lower potential Barrier (PTB) is arranged below the Pixel Vertical Transfer Gate, the Pixel Vertical Transfer channel is divided into a plurality of independent parts by the Pixel Vertical Transfer Gate lower potential Barrier, and the Vertical Transfer of a photoelectric signal in the Pixel is controlled by the Pixel Vertical Transfer Gate and the Pixel lower potential Barrier; a pixel transfer gate is arranged at the junction of one side of the pixel vertical transfer gate and a pixel photosensitive area (PS), the pixel transfer gate covers one side of the pixel vertical transfer gate, a pixel transfer gate lower potential barrier is arranged below the pixel transfer gate, the pixel transfer gate lower potential barrier is connected with a pixel multiplication structure and a channel resistance opening, the pixel transfer gate and the pixel transfer gate lower potential barrier realize the switching function of the photosensitive area, and whether a photoelectric signal in the photosensitive area is transferred out of the pixel photosensitive area or not is controlled.
Furthermore, pixels are arranged above the substrate, a pixel photosensitive area and a vertical transfer area are arranged on the pixels, surface dielectric layers of the pixel photosensitive area are arranged at the upper ends of the photosensitive area and the vertical transfer area, and a pixel multiplication structure is arranged inside the pixel photosensitive area.
Furthermore, the pixel multiplication structure is formed by ion implantation, and the edge distance of the pixel multiplication structure is at least more than 1 μm away from the channel resistance.
Furthermore, the pixel vertical transfer grid is at least of a 2-phase structure and comprises a first-phase vertical transfer grid and a second-phase vertical transfer grid, the first-phase vertical transfer grid and the second-phase vertical transfer grid are partially overlapped, and the overlapped parts of the pixel multiplication grid, the pixel transfer grid and the pixel vertical transfer grid are all one side of the second-phase vertical transfer grid.
Further, the pixel multiplication grid is formed by growing polycrystalline silicon, the pixel multiplication grid is overlapped with the second phase vertical transfer grid by at least more than 2 micrometers, and the pixel multiplication grid is overlapped with the pixel transfer grid by at least 1 micrometer.
Further, the pixel transfer gate is formed by growing polysilicon, and the pixel transfer gate overlaps with the second phase vertical transfer gate by more than 1 μm.
Further, a lower potential barrier of the pixel transfer gate is formed in an ion implantation mode, the width of the lower potential barrier of the pixel transfer gate is more than 1 μm, and the pixel transfer gate covers the upper part of the lower potential barrier of the pixel transfer gate.
Further, when the pixel does not need the multiplication function, the driving time sequence of the pixel multiplication grid is at a low level, the pixel multiplication region covered under the pixel multiplication grid is in a natural depletion state at the moment, the highest potential position is 4-5V, the potential required by charge multiplication cannot be reached, and the pixel is in a normal working state; when the pixel needs a multiplication function, the level of a driving time sequence of the pixel multiplication grid is changed from low to high, the high level is 20-30V, when the pixel multiplication grid is at the high level, the pixel multiplication area is deeply depleted towards the substrate direction through a high-voltage strong electric field, the maximum potential is 24-35V, and the high potential of the pixel multiplication area generates a strong electric field to enable the photoelectric charge to generate an avalanche multiplication effect; when the pixel is in a multiplication state, the driving time sequence of the pixel transfer gate is in a low level, and the pixel transfer gate controls a potential barrier under the pixel transfer gate to separate a photosensitive region of the pixel from a vertical transfer region of the pixel, so that the functions of signal multiplication and vertical transfer isolation in the pixel during light integration are realized.
The pixel-level multiplied IFT CCD pixel structure can realize the functions of photoelectric conversion in the pixel, charge multiplication in the pixel, photoelectric charge storage, photoelectric charge transfer and the like. The IFT CCD can realize the detection sensitivity improvement at the front-end pixel level, so that the IFT CCD has the capability of realizing the detection of dim light and even single photon signals.
Drawings
FIG. 1 is a schematic diagram of a conventional interline transfer CCD pixel structure;
FIG. 2 is a schematic diagram of an IFT CCD pixel structure with pixel level multiplication according to the present invention;
FIG. 3 is a cross-sectional view taken along line X of FIG. 2 in accordance with the present invention;
FIG. 4 is a cross-sectional view taken along line Y of FIG. 2 in accordance with the present invention;
101, a photosensitive area; 102. blocking a ditch; 103. a first phase vertical transfer gate; 104. a second phase vertical transfer gate;
205. a pixel multiplication structure; 206. pixel multiplication grid; 207. a pixel transfer gate; 208. a surface dielectric layer of the photosensitive area; 209. a pixel transfer gate lower barrier; 210. a substrate; 211. a pixel vertical transfer channel; 212. the pixel vertically transfers the barrier under the gate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention discloses a pixel level multiplication internal line frame transfer CCD pixel structure, which comprises a substrate, a pixel multiplication structure and a pixel vertical transfer area, wherein the pixel multiplication structure is surrounded by a channel resistor and is provided with an opening at one side, and a pixel multiplication grid is arranged above the pixel multiplication structure and the opening of the channel resistor; the pixel vertical transfer region is arranged on one side of the pixel photosensitive region and consists of a pixel vertical transfer channel and a pixel vertical transfer gate above the channel, a pixel vertical transfer gate lower potential barrier is arranged below the pixel vertical transfer gate, the pixel vertical transfer channel is divided into a plurality of independent parts by the pixel vertical transfer gate lower potential barrier, and the vertical transfer of photoelectric signals in the pixel is controlled by the pixel vertical transfer gate and the pixel lower potential barrier; the pixel transfer gate is arranged at the junction of one side of the pixel vertical transfer gate and the pixel photosensitive area, the pixel transfer gate covers one side of the pixel vertical transfer gate, a potential barrier under the pixel transfer gate is arranged below the pixel transfer gate, the potential barrier under the pixel transfer gate is connected with the pixel multiplication structure and the opening of the channel resistor, the pixel transfer gate covers one side of the pixel vertical transfer gate, and the pixel transfer gate and the potential barrier under the pixel transfer gate realize the switching function of the photosensitive area and control whether a photoelectric signal in the photosensitive area is transferred out of the pixel photosensitive area or not.
In order to further explain the structure of the present invention, this embodiment proposes a schematic structural diagram as shown in fig. 2, and the present invention is an IFT CCD pixel structure with multiplied pixel levels, and this embodiment prepares 4 adjacent IFT CCD pixel structures with multiplied pixel levels on a substrate, of course, the present invention may not be limited to the IFT CCD pixel structure with multiplied pixel levels of 4 pixel levels in practical application.
Fig. 1 is a schematic diagram of a conventional internal line transfer CCD pixel structure, and as can be seen from fig. 1, the conventional internal line transfer CCD pixel structure includes a trench resistance 102, a photosensitive region 101, and a vertical transfer region, and the vertical transfer region of the conventional internal line transfer CCD pixel structure includes a first vertical transfer phase 103 and a second vertical transfer phase 104.
On the basis of the traditional internal line transfer CCD pixel structure, the pixel level multiplied IFT CCD pixel structure provided by the invention is shown in figure 2, and each pixel level multiplied IFT CCD pixel structure comprises a photosensitive area 201, a pixel multiplication structure 205, a pixel multiplication grid 206, a pixel transfer grid 207, a channel resistor 202 and a pixel vertical transfer area.
In this embodiment, a device formed by an IFT CCD pixel structure multiplied by 4 pixel levels is taken as an example, and of course, the practical application of the present invention is not limited to the IFT CCD pixel structure multiplied by 4 pixel levels. Fig. 3 and 4 are cross-sectional views of the cross-section line X in fig. 2 at the cross-section line Y, respectively, and compared with the conventional internal line transfer CCD pixel structure, the present invention is further provided with a pixel multiplication structure 205, a pixel multiplication gate 206, and a pixel transfer gate 207; the pixel multiplication structure 205 is surrounded by the channel resistor 101 and is provided with an opening on one side, and a pixel multiplication grid 206 is arranged above the pixel multiplication structure 205 and the opening of the channel resistor 101; the pixel vertical transfer region is arranged on one side of the pixel photosensitive region 101 and consists of a pixel vertical transfer channel and a pixel vertical transfer gate above the channel, a pixel vertical transfer gate lower potential barrier is arranged below the vertical transfer region, the pixel vertical transfer channel 211 is divided into a plurality of independent parts by the pixel vertical transfer gate lower potential barrier, and the vertical transfer of photoelectric signals in the pixel is controlled by the pixel vertical transfer gate and the pixel vertical transfer gate lower potential barrier; a pixel transfer gate 207 is arranged at the junction of one side of the vertical transfer region and the pixel photosensitive region 101, the pixel transfer gate 207 covers one side of the pixel vertical transfer gate, a lower potential barrier 209 of the pixel transfer gate is arranged below the pixel transfer gate 207, the lower potential barrier 209 of the pixel transfer gate is connected with the pixel multiplication structure 205 and the opening of the channel resistor 101, the pixel transfer gate and the lower potential barrier 209 of the pixel transfer gate realize the switching function of the photosensitive region 101, and whether a photoelectric signal in the photosensitive region 101 is transferred out of the pixel photosensitive region is controlled.
As shown in fig. 3, pixels are arranged above a substrate 210, a pixel photosensitive area 101 and a pixel vertical transfer area of the pixels are both arranged on the pixels, a pixel photosensitive area surface dielectric layer 208 is arranged at the upper ends of the pixel photosensitive area 101 and the pixel vertical transfer area, and a pixel multiplication structure 205 is arranged inside the pixel photosensitive area.
As shown in fig. 3, in the direction of the sectional line X, the pixel vertical transfer channel 211 is divided into several independent parts by the potential barrier under the pixel vertical transfer gate; as shown in fig. 4, in the direction of the sectional line Y, the pixel vertical transfer channels 211 and the pixel vertical transfer gate lower barriers 212 are alternately arranged.
Further, the pixel multiplication structure 205 is formed by ion implantation, and the distance between the edge of the pixel multiplication structure and the channel resistance is at least 1 μm.
Further, the pixel vertical transfer gate has at least a 2-phase structure, in this embodiment, the 2-phase structure is taken as an example, as shown in fig. 2 and fig. 4, and includes a first-phase vertical transfer gate 103 and a second-phase vertical transfer gate 104, as shown in fig. 4, a part of the overlap exists between the first-phase vertical transfer gate 103 and the second-phase vertical transfer gate 104, and the overlapping parts of the pixel multiplication 206, the pixel transfer gate 207 and the pixel vertical transfer gate are both one side of the second-phase vertical transfer gate 104.
Further, the pixel multiplication gate 206 is formed by growing polysilicon, and the pixel multiplication gate 206 overlaps the second phase vertical transfer gate 104 by at least 2 μm or more, and the pixel multiplication gate 206 overlaps the pixel transfer gate 207 by at least 1 μm.
Further, the pixel transfer gate 207 is formed by growing polysilicon, and the pixel transfer gate 207 overlaps with the second-phase vertical transfer gate 104 by 1 μm or more.
Further, the pixel transfer gate lower potential barrier 209 is formed by ion implantation, and the width of the pixel transfer gate lower potential barrier 209 is more than 1 μm, and the pixel transfer gate covers the pixel transfer gate lower potential barrier 209.
The detection of photoelectric signals, the multiplication of photoelectric sum and the storage of the photoelectric in a photosensitive area are realized by driving a time sequence control pixel multiplication grid and a pixel transfer grid, and the specific working principle comprises the following steps:
when the pixel does not need the multiplication function, the pixel multiplication grid driving time sequence is at a low level, a pixel multiplication region covered under the pixel multiplication grid is in a natural depletion state at the moment, the highest potential is about 4-5V, the potential required by charge multiplication cannot be reached, and the pixel is in a normal working state;
when the pixel needs a multiplication function, the level of a driving time sequence of the pixel multiplication grid is changed from low to high, the high level is about 20-30V, when the pixel multiplication grid is at the high level, the pixel multiplication area is deeply depleted towards the substrate direction through a high-voltage strong electric field, the maximum electric potential is about 24-35V, and the high electric potential of the pixel multiplication area generates a strong electric field to enable photoelectric charges to generate an avalanche multiplication effect, so that the pixel multiplication function is realized;
when the pixel is in a multiplication state, the driving time sequence of the pixel transfer gate is in a low level, the pixel transfer gate controls a potential barrier under the pixel transfer gate to separate a pixel photosensitive area from a pixel vertical transfer area, and the functions of signal multiplication and vertical transfer isolation in the pixel during light integration are realized, so that multiplied photocharge is stored in the photosensitive area;
therefore, under the matching of the driving time sequence of the pixel multiplication grid and the pixel transfer grid, the detection of photoelectric signals, the multiplication of the photoelectric sum and the storage of the photoelectric in the photosensitive area are realized.
By adopting the pixel-level multiplied IFT CCD pixel structure, the functions of photoelectric conversion in the pixel, charge multiplication in the pixel, photoelectric charge storage, photoelectric charge transfer and the like can be realized. The IFT CCD can realize the improvement of the detection sensitivity at the front-end pixel level, so that the IFT CCD can achieve the aim of detecting glimmer and even single photon signals.
In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "both ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The pixel level multiplication internal line frame transfer CCD pixel structure comprises a substrate, a pixel multiplication structure and a pixel vertical transfer area, and is characterized in that the pixel multiplication structure is surrounded by a channel resistor and is provided with an opening on one side, and a pixel multiplication grid is arranged above the pixel multiplication structure and the channel resistor opening; the pixel vertical transfer region is arranged on one side of the pixel photosensitive region and consists of a pixel vertical transfer channel and a pixel vertical transfer gate above the channel, a pixel vertical transfer gate lower potential barrier is arranged below the pixel vertical transfer gate, the pixel vertical transfer channel is divided into a plurality of independent parts by the pixel vertical transfer gate lower potential barrier, and the vertical transfer of photoelectric signals in the pixel is controlled by the pixel vertical transfer gate and the pixel lower potential barrier; the pixel transfer gate is arranged at the junction of one side of the pixel vertical transfer gate and the pixel photosensitive area, the pixel transfer gate covers one side of the pixel vertical transfer gate, a lower potential barrier of the pixel transfer gate is arranged below the pixel transfer gate, the lower potential barrier of the pixel transfer gate is connected with the pixel multiplication structure and the opening of the channel resistor, the pixel transfer gate and the lower potential barrier of the pixel transfer gate realize the switching function of the photosensitive area, and whether a photoelectric signal in the photosensitive area is transferred out of the pixel photosensitive area or not is controlled.
2. The pixel-level multiplication inline frame transfer CCD pixel structure of claim 1, wherein the pixel is disposed above the substrate, the photosensitive region and the vertical transfer region are both disposed on the pixel, a pixel photosensitive region surface dielectric layer is disposed at the upper end of the pixel photosensitive region and the pixel vertical transfer region, and the pixel multiplication structure is disposed inside the pixel photosensitive region.
3. The pixel-level multiplication inline frame transfer CCD pixel structure of claim 1, wherein the pixel multiplication structure is formed by means of ion implantation and the edge of the pixel multiplication structure is at least 1 μm away from the channel resistance.
4. The pixel-level multiplication inline frame transfer CCD pixel structure of claim 1, wherein the pixel vertical transfer gate is at least a 2-phase structure comprising a first-phase vertical transfer gate and a second-phase vertical transfer gate, the first-phase vertical transfer gate and the second-phase vertical transfer gate have a partial overlap therebetween, and the overlapping portions of the pixel multiplication gate, the pixel transfer gate and the pixel vertical transfer gate are all one side of the second-phase vertical transfer gate.
5. The pixel-level multiplication inline frame transfer CCD pixel structure of claim 3, wherein the pixel multiplication gate is formed by growing polysilicon and overlaps at least 2 μm with the second phase vertical transfer gate and at least 1 μm with the pixel transfer gate.
6. The pixel-level multiplication inline frame transfer CCD pixel structure of claim 4, wherein the pixel transfer gate is formed by growing polysilicon and the pixel transfer gate overlaps the second phase vertical transfer gate by more than 1 μm.
7. The pixel-level multiplication inline frame transfer CCD pixel structure of claim 1, wherein the barrier under the pixel transfer gate is formed by ion implantation and has a width of more than 1 μm, and the pixel transfer gate covers over the barrier under the pixel transfer gate.
8. The pixel-level multiplication internal line frame transfer CCD pixel structure of claim 1, wherein when the pixel does not need the multiplication function, the driving time sequence of the pixel multiplication grid is low level, at this time, the pixel multiplication region covered under the pixel multiplication grid is in a natural depletion state, the highest potential is 4-5V, the potential required by charge multiplication cannot be reached, and the pixel is in a normal working state; when the pixel needs a multiplication function, the level of a driving time sequence of the pixel multiplication grid is changed from low to high, the high level is 20-30V, when the pixel multiplication grid is at the high level, the pixel multiplication area is deeply depleted towards the substrate direction through a high-voltage strong electric field, the maximum potential is 24-35V, and the high potential of the pixel multiplication area generates a strong electric field to enable the photoelectric charge to generate an avalanche multiplication effect; when the pixel is in a multiplication state, the driving time sequence of the pixel transfer gate is in a low level, and the pixel transfer gate controls a potential barrier under the pixel transfer gate to separate a photosensitive region of the pixel from a vertical transfer region of the pixel, so that the functions of signal multiplication and vertical transfer isolation in the pixel during light integration are realized.
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| CN113488494B (en) * | 2021-07-12 | 2023-04-14 | 中国电子科技集团公司第四十四研究所 | Pixel multiplication and signal transfer control method of internal line frame transfer CCD |
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