CN101236958B - 半导体封装体 - Google Patents

半导体封装体 Download PDF

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CN101236958B
CN101236958B CN2008100834243A CN200810083424A CN101236958B CN 101236958 B CN101236958 B CN 101236958B CN 2008100834243 A CN2008100834243 A CN 2008100834243A CN 200810083424 A CN200810083424 A CN 200810083424A CN 101236958 B CN101236958 B CN 101236958B
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semiconductor package
package body
support plate
pattern
conductive film
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CN101236958A (zh
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吴家福
李政颖
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开了一种半导体封装体。该半导体封装体包含一载板、至少一芯片、一封装材料以及一图案化导电薄膜。载板具有第一表面及第二表面，第一表面与第二表面相对设置。芯片设置于载板的第一表面，并与载板电性连接。封装材料包覆芯片及载板的至少部分第一表面。图案化导电薄膜设置于封装材料上，以电性连接至载板。本发明的图案化导电薄膜能够有效减少堆叠的垂直高度并缩小尺寸。

Description

半导体封装体
技术领域
本发明涉及一种关于封装体，特别涉及一种半导体封装体。
背景技术
随着电子产品以小型化及高效率为导向，在半导体的技术发展中，通过提高半导体封装装置的容量及性能，以符合使用者的需求。因此，多芯片模块化(multi-chip module)成为近年来研究焦点之一，其将两个或多个芯片以堆叠方式形成一半导体封装体。然而，随着堆叠的半导体封装体体积增大，小型化亦成为重要课题，此外，如何避免半导体封装体的电磁干扰(electromagnetic interference，EMI)亦是研究方向之一。
请参照图1所示，一种已知的半导体封装体1包含一载板11、一芯片12以及一封装材料13。芯片12打线接合于载板11上，封装材料13包覆芯片12及载板11的一侧。为防护电磁干扰，半导体封装体1还具有一遮蔽体14，其设置于封装材料13的外围并接地。然而，遮蔽体14不仅增加生产的成本，且遮蔽体14与载板11之间的结合力，也会因为时间而慢慢减弱，甚至造成遮蔽体14的脱离。此外，遮蔽体14也会增加半导体封装体1的体积，而不利于小型化。
另外，其他的电子元件亦可设置于半导体封装体1上而成为一堆叠架构。堆叠方式例如可先在封装材料13上设置一导线架或基板，然后设置一个或多个芯片或封装体于导线架上。然而，导线架由于结构限制(线宽及厚度)且无法紧靠封装材料13，故此种通过导线架来堆叠的方式并不利于缩小半导体封装体的尺寸。
因此，如何提供一种半导体封装体及其制造方法，能够减少堆叠的垂直高度并缩小半导体封装体的尺寸，且能够防护电磁干扰，已成为重要课题之一。
发明内容
有鉴于上述课题，本发明的目的为提供一种能够有效减少堆叠的垂直高度并缩小尺寸，且能防护电磁干扰的半导体封装体及其制造方法。
因此，为达上述目的，依本发明的一种半导体封装体包含一载板、至少一芯片、一封装材料以及一图案化导电薄膜。载板具有第一表面及第二表面，第一表面与第二表面相对设置。芯片设置于载板的第一表面，并与载板电性连接。封装材料包覆芯片及载板的至少部分第一表面。图案化导电薄膜设置于封装材料上，以电性连接至该载板。
为达上述目的，依本发明的一种半导体封装体的制造方法包含以下步骤：提供一封装体，封装体包含一载板、至少一芯片及一封装材料，载板具有第一表面及第二表面，第一表面与第二表面相对设置，芯片设置于载板的第一表面，并与载板电性连接，封装材料包覆芯片及载板的至少部分第一表面；以及形成一图案化导电薄膜于封装材料上，以电性连接至该载板。
承上所述，因依本发明的一种半导体封装体及其制造方法将一图案化导电薄膜直接形成于封装材料上，图案化导电薄膜可与其他电子元件相堆叠及电性连接而形成堆叠的半导体封装体。此外，部分图案化导电薄膜亦可接地而具有防护电磁干扰的功效。与已知技术相较，本发明的图案化导电薄膜并无已知导线架于结构上的限制，而能够有效减少堆叠的垂直高度并缩小尺寸。
附图说明
图1为一种已知的半导体封装体的示意图；
图2A为依据本发明优选实施例的一种半导体封装体的示意图；
图2B为图2A的半导体封装体及其图案化导电薄膜的示意图；
图3为依据本发明优选实施例的一种半导体封装体的制造方法的流程图；
图4A及图4B为图3的制造方法的示意图；
图5至图8为依据本发明的半导体封装体外接电子元件具有不同变化态样的示意图；以及
图9A及图9B为本发明的半导体封装体使用导线架作为载板的示意图。
附图标记说明
1、2、2a、3、4：半导体封装体
11、21：载板
12、22、22a、26、27、28、29、32、42：芯片
13、23、23a、23b、33、43：封装材料
14：遮蔽体
211：第一表面
212：第二表面
213、253：焊球
24、24b、34、44：图案化导电薄膜
241：线路图样
242：电磁防护图样
25：封装体
263：导电凸块
31、41：导线架
S01～S03：半导体封装体的制造方法的流程步骤
具体实施方式
以下将参照相关图示，说明依本发明优选实施例的一种半导体封装体及其制造方法，其中相同的元件将以相同的参照符号加以说明。
请参照图2A所示，本发明优选实施例的一种半导体封装体2包含一载板21、至少一芯片22、一封装材料23以及一图案化导电薄膜24。
载板21具有第一表面211及第二表面212，第一表面211与第二表面212相对设置。芯片22设置于载板21的第一表面211，并可以导电凸块(flip-chip bonding)或焊线(wire bonding)与载板21电性连接，在此以焊线接合为例。载板21的第二表面212具有多个焊球(solder ball)213，用以与其他电子元件电性连接，例如与一电路板(图未显示)连接。封装材料23包覆芯片22及载板21的至少部分第一表面211。封装材料23可为环氧树脂(epoxy)或硅胶(silicone)。图案化导电薄膜24设置于封装材料23上，并可延设至第一表面211，再经由载板21的导电孔(conductive via)，而与焊球213的至少其中之一电性连接。
请同时参照图2A及图2B所示，图案化导电薄膜24包含一线路图样241及一电磁防护图样242。线路图样241与第二表面212的未接地的焊球213的至少其中的一电性连接。电磁防护图样242可经由第二表面212的接地的焊球213电性连接而接地，以提供电磁遮蔽的效用。电磁防护图样242设置于线路图样241以外的位置。当然，电磁防护图样242亦可直接接地而不经由焊球213。此外，载板21可具有一线路重分布层(图未显示)，线路图样241及电磁防护图样242可通过线路重分布层，而与对应的焊球213电性连接。
在本实施例中，并不限制线路图样241及电磁防护图样242的尺寸及形状。图案化导电薄膜24可形成于封装材料23上的任意位置，并延设至载板21的第一表面211。
请参照图3所示，本发明优选实施例的一种半导体封装体的制造方法包含步骤S01至步骤S03。请同时参照图3、图4A及图4B所示，以进一步说明半导体封装体2的制造方法。
请参照图3及图4A所示，步骤S01为提供一封装体。封装体包含一载板21、至少一芯片22以及一封装材料23。由于载板21、芯片22及封装材料23的实施态样已详述于上，故不再赘述。
请参照图3及图4B所示，步骤S02为形成一图案化导电薄膜24于封装材料23上。图案化导电薄膜24可通过沉积、涂布、印刷或电镀方式形成于封装材料23上。其中，沉积可为物理沉积，例如溅镀(sputtering)。本实施例的制造方法在形成图案化导电薄膜24之前，可还包含形成一非平坦结构或一粗化结构于封装材料23的外表面，以加强图案化导电薄膜24与封装材料23之间的结合力。非平坦结构例如为沟槽及/或凸部的组合，粗化结构例如为粗糙面。
然后，步骤S03为将图案化导电薄膜24与焊球213至少其中之一电性连接，图案化导电薄膜24与焊球213经由载板21的导电孔而电性连接。
本实施例的制造方法还包含一步骤：将图案化导电薄膜24与至少一电子元件相堆叠及电性连接。在此并不限定电子元件的类别，例如电子元件可选自芯片、封装体、多芯片模块(multi-chip module，MCM)、多封装体模块(multi-package module，MPM)及其组合所构成的组。以下说明图案化导电薄膜24外接电子元件的不同变化态样。
如图5所示，一封装体25设置于半导体封装体2上，而与图案化导电薄膜24相堆叠及电性连接。封装体25的部分焊球253可与图案化导电薄膜24的线路图样241电性连接，另一部分焊球253可与图案化导电薄膜24的电磁防护图样242电性连接。另外，可通过另一封装材料包覆半导体封装体2及封装体25，以提供保护作用。
如图6所示，一芯片26例如以导电凸块设置于半导体封装体2上，而与图案化导电薄膜24相堆叠及电性连接。芯片26的部分导电凸块263可与图案化导电薄膜24的线路图样241电性连接，另一部分导电凸块263可与图案化导电薄膜24的电磁防护图样242电性连接。制造方法可还包含一步骤：通过另一封装材料包覆芯片26及半导体封装体2，以提供保护作用。
如图7所示，一芯片27例如以导电凸块设置于半导体封装体2上，而与图案化导电薄膜24电性连接。制造方法还包含一步骤：通过另一封装材料23a包覆半导体封装体2的一部分并形成一凹穴，用以放置芯片27。封装材料23a为裸露部分的图案化导电薄膜24，并形成一凹穴，由此裸露的图案化导电薄膜24可用以选择性相堆叠及电性连接各种电子元件，例如芯片27。
如图8所示，一半导体封装体2a的芯片22a以导电凸块设置于载板21上。一芯片28以导电凸块设置于半导体封装体2a，并与其图案化导电薄膜24电性连接。一封装材料23b包覆芯片28及半导体封装体2a。一图案化导电薄膜24b设置于封装材料23b上，并延设至载板21的第一表面211并与焊球213电性连接。
上述实施例的载板以电路基板为例，另外，本发明的载板亦可为导线架。请参照图9A所示，一种半导体封装体3包含一导线架31、一芯片32、一封装材料33及一图案化导电薄膜34。芯片32以焊线电性连接于导线架31。封装材料33包覆芯片32及部分导线架31。图案化导电薄膜34设置在封装材料33上并与导线架31电性连接。在此，导线架31为一四方扁平无引脚封装体(Quad Flat Non-leaded package，QFN)的导线架。
另外，请参照图9B所示，一种半导体封装体4包含一导线架41、一芯片42、一封装材料43及一图案化导电薄膜44。芯片42以焊线电性连接于导线架41。封装材料43包覆芯片32及部分导线架41。图案化导电薄膜44设置在封装材料43上并与导线架41电性连接。在此，导线架41为一四方扁平封装体(Quad Flat Package，QFP)的导线架。
综上所述，因依本发明的一种半导体封装体及其制造方法将一图案化导电薄膜直接形成于封装材料上，图案化导电薄膜可与其他电子元件相堆叠及电性连接而形成堆叠的半导体封装体。此外，部分图案化导电薄膜亦可接地而具有防护电磁干扰的功效。与已知技术相较，本发明的图案化导电薄膜并无已知导线架于结构上的限制，而能够有效减少堆叠的垂直高度并缩小尺寸。
以上所述仅为举例性，而非为限制性者。任何未脱离本发明的精神与范畴，而对其进行的等效修改或变更，均应包含于后附的权利要求中。

Claims (12)

1.一种半导体封装体，包含：
一载板，具有第一表面及第二表面，该第一表面与该第二表面相对设置；
至少一芯片，设置于该载板的该第一表面，并与该载板电性连接；
一封装材料，包覆该芯片及该载板的至少部分该第一表面；以及
一图案化导电薄膜，设置于该封装材料上，以电性连接至该载板，该图案化导电薄膜包含一线路图样和一电磁防护图样，所述线路图样和所述电磁防护图样彼此分离。
2.如权利要求1所述的半导体封装体，其中该第二表面具有多个焊球。
3.如权利要求2所述的半导体封装体，其中该线路图样与所述焊球至少其中之一电性连接。
4.如权利要求2所述的半导体封装体，其中该电磁防护图样与这些焊球至少其中之一电性连接。
5.如权利要求1所述的半导体封装体，其中该芯片以导电凸块或焊线与该载板电性连接。
6.如权利要求1所述的半导体封装体，其中该图案化导电薄膜与至少一电子元件相堆叠及电性连接。
7.如权利要求6所述的半导体封装体，其中该电子元件选自芯片、封装体、多芯片模块、多封装体模块及其组合所构成的组。
8.如权利要求6所述的半导体封装体，其中该半导体封装体及该电子元件为另一封装材料所包覆。
9.如权利要求6所述的半导体封装体，其中另一封装材料包覆该半导体封装体的一部分并形成一凹穴，用以放置该电子元件。
10.如权利要求1所述的半导体封装体，其中该封装材料的外表面具有一非平坦结构或一粗化结构，以结合该图案化导电薄膜。
11.如权利要求1所述的半导体封装体，其中该载板为电路基板或导线架。
12.如权利要求11所述的半导体封装体，其中该导线架为四方扁平封装体的导线架或四方扁平无引脚封装体的导线架。
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