CN101232456B - Distributed type testing on-chip network router - Google Patents
Distributed type testing on-chip network router Download PDFInfo
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Abstract
The invention discloses a distributing type testable chip network router, which comprises a plurality of physical transmission channels with configurable channel quantity for providing the transmission of physical data; a router configuration channel which is independent of a data transmission network and supports the connection test of the router; a plurality of channel link controllers used for finishing the response to an input request and the allocation to a virtual channel; a cross switch used for providing a full connection between an inputting virtual channel and an outputting channel; a plurality of distributing type route controllers which are distributed at the inputting virtual channel and determine the direction of microchips forwarding according to microchip head information in the channel; and a plurality of distributing type arbitration devices which are distributed in the outputting channel and determine the property ownership of the outputting channel when a plurality of inputting virtual channels request occupying the outputting channel. The router is applicable to chip network systems in the multiprocessor system chip, and has the advantages that the router is reliable, highly-efficient, testable and expandable.
Description
Technical field
The present invention relates to multiprocessor system chip (Multiprocessor Systems-on-Chip, MPSoC) on-chip interconnect network (the On-Chip InterconnectionNetworks that uses in, OCINs) system, in particular, the invention provides a kind of distributed type testing router that is applicable to the on-chip interconnect network system.
Background technology
Along with the continuous development of integrated circuit technique and the driving of application demand, chip design enters into multiprocessor karyonide system chip stage from uniprocessor karyonide system chip.In traditional design, the mode of shared bus is used in the functional unit interconnection usually in the chip.The unit that needs to interconnect in chip gets more and more, and bus bandwidth is limited, and length increases sharply, and the time-delay that consumes on the bus, power consumption etc. also increase thereupon, and these all become the key factor that limits its development.For solving the many disadvantages of bus architecture, designers use the basic thought in traditional multiprocessor internet and the general communication network, and (Networks-on-Chip is NoC) as new chip-on communication solution to propose network-on-chip.
Router is finished the reception and the forwarding of packet as a critical component of network.Traditional router is used to connect Large Scale Computer System, distance between the router is little of several centimetres, big to hundreds of rice, connecting medium has twisted-pair feeder, coaxial cable, optical fiber etc., router as one independently parts have plenty hardware resources to utilize.Under these conditions, asynchronous transmission, large capacity cache, less transmission width, complicated fault-tolerant mechanism for correcting errors, perfect polymerization communication support have all been used in the design of router.In network-on-chip, router is integrated in the single chip with other IP (Intellectual Property), and the distance between the router is reduced to a millimeter rank, and what connect router is the metal level of chip internal, interconnection resources is very abundant, but available hardware resource is relatively limited.The network-on-chip structure is generally used local synchronization Global Asynchronous technology, and (Globally Asynchronous Locally Synchronous, GALS), the design of router need be satisfied it to the clock zone requirement.In the time of in router is integrated in chip, the connectedness of how simple, quick test router and network is with extremely important.The topological structure of network-on-chip will change with application demand, and router will be easy to be expanded and adapt to various topological structures.The characteristics of network-on-chip determine its need reliable, efficient, can test, extendible router.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of be applicable to network-on-a-chip in the multiprocessor system chip reliable, efficient, can test, extendible router.
Router of the present invention is used for network-on-a-chip, and as the resource node in the communication node connection network, the resource node in the network can be processor, digital signal processor, high-speed memory, high-speed peripheral or other special circuits in network.
Minimum transmission units on the network-on-chip at router of the present invention place is that microplate (Flow Control Unit, Flit), be made up of header (Head) and load information (Payload) two parts by microplate.Comprise microplate type, microplate source address, destination address three partial contents in the header; In the load information the entrained data of microplate.Router can extract header after receiving microplate, and transmits this microplate according to the content in the header.Router is only transmitted load information and is not resolved its particular content.
In order to solve the problems of the technologies described above, the invention provides a kind of distributed type testing on-chip network router, comprising:
A plurality of physical transmission channels that number of channels can be prepared are used to provide the transmission of physical data, and width of channel is a microplate width; Input channel can provide a plurality of Virtual Channels, and for each Virtual Channel add microplate buffer memory (First-In-First-Out, FIFO), the buffer memory width is a microplate width, the degree of depth can suitably be selected according to hardware resource.Output channel does not provide Virtual Channel and buffer memory; Simultaneously, each I/O channel provides control logic to transmit with the reception of finishing data;
(Configure Channel CR), is independent of data transmission network to a configuration of routers passage, supports the connectivity test of router;
(Link Controller LC), finishes the distribution to input request responding and Virtual Channel to a plurality of channel link controllers, and its quantity is consistent with input channel quantity;
(Crossbar Switch SW), provides the input Virtual Channel to the full connection between the output channel to a cross bar switch;
(Distributed Router DRT), is distributed in each input Virtual Channel place to a plurality of distributed path control deivces, and according to the routing direction of microplate header decision microplate in the passage, its quantity is consistent with Virtual Channel quantity;
A plurality of distributed arbiters (Distributed Arbiter DARB), is distributed in each output channel, the ownership ownership of decision output channel when having the request of a plurality of input Virtual Channel to take output channel, and its quantity is consistent with output channel quantity.
Router of the present invention is applicable to two-dimensional grid (Mesh) topological structure, the control unit that router provides 5 I/O channels and adapts therewith in this topological structure.Router I/O channel and control unit all adopt modularized design, change number of channels and control corresponding unit and can make router be applicable to other network topology structure.
Router of the present invention is operated in a plurality of clock zones, to adapt to the clock request of network-on-chip.Each input channel of router all is operated in clock zone separately, and clock signal is transmitted by upper level router or resource node, and promptly input channel and upper level router or resource node are operated in same clock zone.Data are transformed into the local clock territory from the input clock territory after entering the Virtual Channel buffer unit, parts such as the cross bar switch in the router, distributed path control deivce, distributed arbiter all are operated in the local clock territory.Data in the router, transmit signal such as request and local clock and be transferred in the network after synchronous.The local clock signal of router is also followed data-signal and is transferred to next stage router or resource node together as its input clock.This way is divided into the fritter of local synchronization one by one with network-on-chip, has reduced the length and wiring difficulty of clock trees in the chip, has reduced the load on the clock trees, has reduced power consumption.
Router provides a configuration of routers passage, is used to provide the support to the router testability.Collocation channel separates with data transmission network on the sheet, is not subjected to the influence of data transmission network.By configuration the special modality of router is coupled together and be not subjected to that microplate influences in the passage, thereby provide the internuncial test of router.The router preparation is undertaken by the resource node in the network, and it can be processor, digital signal processor or special-purpose preparation module.
Router is used for the data of network are carried out flow control for each input channel provides a link controller, and Virtual Channel distributes, and supports the worm channel route.For each Virtual Channel provides a register, store source, the destination address of the whether occupied and active channel of passage in the link controller, be used to characterize this Virtual Channel current state.Comprise the type of this microplate and source thereof, destination address in the header of microplate.Provide one type microplate to be used to open up and take the Virtual Channel of a free time, be called the data head microplate.When not having available Virtual Channel, the data head microplate will get clogged, up to available Virtual Channel occurring.Article one, passage occupied after, the Virtual Channel register can be modified to characterize passage occupied, source, the destination address with this microplate writes register simultaneously.One type microplate is provided, when consistent in the channel register of the source in its header, destination address and an occupied passage, advances, be called the data microplate along passage.One type microplate is provided, when consistent in the channel register of the source in its header, destination address and an occupied passage, advances, and revise channel register the passage that takies is discharged, be called data tail microplate along passage.Provide two types microplate to be used for controlling links, they transmit forward when idle channel is arranged, but do not change channel status, are called request microplate and feedback microplate respectively.
Router provides a full cross bar switch that connects, and it provides the connection of any input Virtual Channel to any output channel.
Router provides a plurality of distributed path control deivces and distributed arbiter.Distributed path control deivce is positioned at each input Virtual Channel place, receives the microplate header, carries out route according to certain routing algorithm, selects an output channel.Path control deivce is supported the worm channel exchange, when the data head microplate is carried out route route results is deposited, and does not carry out route and directly use the route results of depositing as its route results when data microplate and data tail microplate arrive.Can carry out route again to request microplate and feedback microplate path control deivce.It is order that this way makes transfer of data, has avoided the problem of out of order propagation.Path control deivce is subjected to the control of dispensing unit, will not be subjected to the influence of routing algorithm by the result and the routing channel selecting to dispose is transmitted microplate at the effective time channel of configuration.Each output channel provides a distributed arbiter, and it receives the request of Virtual Channel, and selects the highest input Virtual Channel of priority to link to each other with this output channel according to certain priority rule.
The present invention adopts modularized design, and the collocation channel of router, transmission channel, distributed path control deivce, distributed arbiter all are designed to multiplexing extensibility module.
Compared with prior art, the beneficial effect of distributed type testing on-chip network router of the present invention is: be applicable to the interconnection of network-on-a-chip, finish forwarding of data.Adopt unique clock communications, less buffer memory is used in the exchange of hardware supports worm channel.The test channel of router is provided, supports connectivity test router and network.Use collocation channel, transmission channel, distributed path control deivce and the distributed arbiter of modularized design router, hardware configuration is very simple, has the extensibility of height.
Description of drawings
Below in conjunction with figure the specific embodiment of the present invention is described in further detail.
Fig. 1 is a system construction drawing of the present invention;
Fig. 2 is the collocation channel circuit diagram among the present invention;
Fig. 3 is the controlling links circuit diagram among the present invention;
Fig. 4 is the input Virtual Channel control circuit figure among the present invention;
Fig. 5 is the route control circuit figure among the present invention;
Fig. 6 is a kind of arbitration control circuit figure among the present invention;
Fig. 7 is the another kind of arbitration control circuit figure among the present invention;
Fig. 8 is another the arbitration control circuit figure among the present invention;
Fig. 9 is the cross-bar switch circuit figure among the present invention;
Figure 10 is the output channel control circuit figure among the present invention.
Embodiment
The minimum unit of router transmission of the present invention is microplate (Flit), and microplate is made up of header (Header) and load (Payload).Router can carry out dissection process after receiving microplate to header, and carries out routing forwarding according to content corresponding, then can directly transmit and does not carry out information extraction load.Header length is 16, and its content is as shown in table 1.The network-on-chip of 64 nodes is supported in current use 6 bit space coded addresses, it is expanded can make it support the network of more nodes (128,256, or 512).Table 2 item has been listed the coding to the microplate type.Loaded length can dispose as required, is generally 64 or 128.
Table 1
| 15-12 | 11-6 | 5-0 |
| The microplate type | The microplate destination address | The microplate source address |
Table 2
| The microplate type | Type coding |
| Request (Request) | 0000 |
| Feedback (Response) | 0001 |
| Data head (Data Head) | 0010 |
| Data (Data) | 0100 |
| Data tail (Data Tail) | 0101 |
| Keep | 0011，0110-1111 |
Router of the present invention is supported the worm channel exchange, and dissimilar microplates is handled respectively.In above-mentioned five kinds of microplate types, request can be carried out Route Selection with feedback kind, but can not take Virtual Channel; The data head type need be carried out Route Selection, and will take Virtual Channel; Data and data tail type do not need to carry out Route Selection, and data tail type can discharge Virtual Channel.
Block diagram of the present invention as shown in Figure 1, router uses modularized design.Router of the present invention comprises configuration of routers passage 110, cross bar switch 120, link controller 130, distributed path control deivce 140, Virtual Channel buffer memory 150, input Virtual Channel control 160, distributed arbiter 170, output channel control 180.Configuration signal (111-114) is from configuration module, and it can be processor or specialized configuration circuit.Configuration signal is used independently collocation channel and is separated with data transmission network.Network input signal (117-119) from upper level router or resource node network interface (NetworkInterface, NI).Network input signal comprises clock signal 117, request signal 118, and data-signal 119, they are synchronized with clock signal 117.When network requests 118 arrived, link controller 130 carried out the Virtual Channel buffer memory and distributes, and whether 141 decisions are allocated successfully according to signal.If be allocated successfully, controlling links gives feedback signal 121, and feedback signal is synchronized with clock signal 117, simultaneously microplate is sent into corresponding Virtual Channel buffer memory (FIFO) 150.After microplate is admitted to the Virtual Channel buffer memory, microplate 136 during Virtual Channel control unit 160 cushions with the taking-up of local clock territory according to certain condition, extract header 124 and give distributed path control deivce 140 and carry out route, export microplate 126 to cross bar switch simultaneously.Path control deivce carries out Route Selection according to header packet information, and sends route results 123 back to the Virtual Channel control unit.The route results that input Virtual Channel control unit feeds back according to path control deivce produces controls 180 to request signal 125 to the moderator 170 and the output channel of output channel.Moderator provides arbitration result according to the request situation, and control selector 190 is selected one as output signal 131 from a plurality of input data 129.Simultaneously, output channel control unit output local clock signal 132, request signal 133, data 135 are carried out the transmission of data next time after the feedback signal 134 that receives next stage.Provide the physical circuit design of each module below.
Table 3
| 15 | 14-12 | 11-9 | 8-6 | 5-3 | 2-0 | ||||
| Configuration effectively | | Input channel | 2 | Input channel | 3 | Input channel | 4 | Input channel | 5 configurations |
Table 4
| Output channel connects | |
| Output channel | |
| 1 | 000 |
| Output channel connects | |
| Output channel | |
| 2 | 001 |
| |
010 |
| |
011 |
| |
100 |
| Keep | 101-111 |
Link control unit is used to produce the feedback to upper level, the data flow of control input channel, and the Virtual Channel of control input microplate is selected.Fig. 3-a has provided the link control unit physical circuit figure when each input unit has a Virtual Channel.For the data of input link control, this unit need extract corresponding header, is respectively microplate type (351-353), microplate source address 354, microplate destination address 355.Whether occupied link control unit provides one group of register to be used to deposit the state of current link, comprise passage position 313, takies the source address 315 and destination address 314 of this passage microplate.Taking the condition that a new tunnel need satisfy is: 1) when the prepass free time, promptly 335 is high level; 2) current microplate type is a data head, and promptly 352 is high level; 3) current have a request, and promptly 118 is high level; 4) current Virtual Channel buffer memory is empty, and promptly 364 is high level.When the active channel condition satisfies, exporting 321 with door 319 is high level, or door 326 outputs 327 are high level, register enables effectively, delaying the effective register 320 of Virtual Channel in next clock rising will be set, and Virtual Channel source 340, destination register 330 also will be updated to source, the destination address in the current header.Article one, occupied Virtual Channel is released the condition that needs to satisfy: 1) passage is occupied, and promptly 313 is high level; 2) the microplate type is the data tail, promptly 351 and 352 is high level; 3) value in current occupied channel source, the destination register is consistent with source, destination address in the tail microplate, promptly 336,337 is high level; 5) current passage buffer storage still has vacantly, and promptly 341 is high level; 6) current have a request, and promptly 118 is high level.At this moment, enable signal 327 is a high level, and 321 is low level, and significance bit is cleared.The effective register of new tunnel more only during release channel, and source, destination register are not upgraded.For the microplate of other types, can not influence the content of registers in the link control unit.Link control unit after finishing Virtual Channel and distributing also knack settled before microplate whether can write in the buffer memory, then provide the Virtual Channel buffer memory and write enable signal 122 if can write, and feed back 121 to upper level.Microplate can write the condition that Virtual Channel need satisfy: 1) for the microplate of request, feedback kind, satisfy: a) the microplate type promptly 352,353 is low level for request, feedback kind; B) when the prepass free time, promptly 335 is high level; C) current Virtual Channel buffer memory is empty, and promptly 364 is high level; D) current have a request, and promptly 118 is high level, when above-mentioned 4 conditions satisfy, is output as high level with door 324; 2) for the data head microplate, satisfy: a) when the prepass free time, promptly 335 is high level; B) current microplate type is a data head, and promptly 352 is high level; C) current have a request, and promptly 118 is high level; D) current Virtual Channel buffer memory is empty, and promptly 364 is high level, when above-mentioned 4 conditions satisfy, is output as high level with door 319; 3) for data microplate and data tail microplate, satisfy: a) current request is data microplate or data tail microplate, and promptly 352 is that low level, 353 is high level; B) current have a request, and promptly 118 is high level; C) current Virtual Channel is cached with vacantly, and promptly 341 is high level; D) value in current occupied channel source, the destination register is consistent with source, destination address in the tail microplate, promptly 336,337 is high level, when above-mentioned four conditions satisfy, is output as high level with door 323.When any one satisfies when above-mentioned three conditions, or door 325 output feedback signals 121 directly export to the upper level router, deposit one by register 350 simultaneously and clap to produce and to write enable signal 361.Giving data in buffer 362 is added the data 318 that whether need behind the re-routing signals 342 and deposits one by register 360 and clap and obtain by data 119.361 signals and 362 signal combination are 122 signals among Fig. 1, and 363 signals and 364 signal combination are 141 signals among Fig. 1.Fig. 3-b is the physical circuit of one six bit congruence comparator 310 of using in 3-a, when minimum two of two signals of input be high level by XOR gate 370 back signals 371 not simultaneously, is low level through output signals 377 after the NOR gate 378 again.In like manner, when other corresponding position of input signal has not simultaneously, have at least one to be high level among the signal 372-376, make signal 377 be low level, when all corresponding positions of input were all identical, signal 371-376 was low level, 378 back outputs 377 are high level through NOR gate, finish comparing function.Whole link control unit is operated in the clock zone of input, and clock signal is provided by the upper level router.It is noted that in addition link controller that Fig. 3 provides only provides the control signal of a Virtual Channel, when many Virtual Channels exist simultaneously, need provide many group channel status registers to cooperate the control links.
The forwarding of data from the input channel to the output channel finished in the control of input Virtual Channel.Control module is operated in the local clock territory, therefrom reads microplate when in the Virtual Channel buffer memory microplate being arranged, and takes out microplate head 124 and send into router one 40 and carry out route, and the route results decoding of router is produced request to output channel.Fig. 4 (a) has provided the realization circuit diagram of input Virtual Channel.Can from the input Virtual Channel reading of data condition that need satisfy be: 1) data of not transmitting are arranged in the Virtual Channel buffer memory, and promptly 421 be low level; 2) the current output channel free time, promptly 413 is high level.Whether idle in order to express output channel, provide one 1 bit register 410 to represent the state of current output channel.During initial condition, register output 412 is high level, is low level through not gate 450 back signals 415, process and the request of door (461-465) back shielding to output channel.Signal 412 is a high level, through or door 430 back signals 413 be high level, signal 421 is a low level when the buffer memory non-NULL, through with door 460 after read enable signal 137 and become high level, postpone at next clock temporarily and deposit middle sense data.Simultaneously, signal 417 behind the anti-door 480 of signal 137 processes is a low level, signal 137 processes or door 470 back signals 416 are high level, register is write and is enabled effectively, thereby next clock is delayed register 410 and is obtained the value of signal 417 and export 412 becoming low level, through not gate 450 back signals 415 is high level, and input channel will provide request to output channel according to routing condition.At this moment, 1) if be buffered in and read the back and become empty and feedback signal is arranged, then signal 421 be a high level, through with door 460 after signals 137 be low level, following one-period is reading of data from buffer memory no longer.Simultaneously, because feedback signal is arranged, so signal 127 through or door 440 back output signals 414 be high level, this moment, signal 417 be a high level again, signals 411 are high level behind process and the door 420, a process or door 470 back signals 416 are high level again, register is write and is enabled effectively, delays the value of write signal 417 at next clock, and output signal 412 becomes high level, be that output channel becomes the free time, shielding is to the request of output channel.2) empty if buffer memory becomes, but do not have feedback signal, then by on know that signal 137 is low level; Owing to do not feed back, or door 440 output signals 414 are low level, so process is a low level with door 420 back signals 411, register write enable invalid, next clock is delayed signal 412 and still is low level, through not gate 450 back signals 415 is high level, does not influence the generation of request signal, so request will keep up to there being feedback to arrive.3) if remain microplate in addition and output channel has feedback in the buffer memory, then signal 421 is a low level, and signal 414 is a high level, and a process or door 430 back signals 413 are high level, so process is a high level with door 460 back signals 137, next clock is delayed and will be read new microplate.Simultaneously, because signal 137 is a high level, be low level through not gate 480 back signals 417, a process or door 470 back signals 416 are high level, and register is write and enabled effectively, and next clock is delayed signal 412 and is low level, through not gate 450 back signals 415 is high level, will produce request.4) if buffer memory in remain microplate in addition but output channel do not provide the feedback 127, then a process or door 440 back signals 414 are low level, because this moment, signal 412 was a low level, then a process or door 430 back signals 413 are low level, process is a low level with door 460 back signals 137 again, no longer reads the content in the new buffer memory.Simultaneously, signal 414 is a low level, through with door 420 back signals 411 be low level, again through or door 470 back signals 416 be low level, register is write and is enabled invalidly, next clock is delayed signal 412 maintenance low levels.Simultaneously, signal 412 is a low level, is high level through not gate 450 back signals 415, will produce the request signal to output channel, up to the arrival of feedback.Table 5 has provided the decoding situation of controller to the router route results, is about to route signal 123 and is transformed into request signal 422.The request signal 125 that outputs to moderator also depends on signal 415, and when signal 415 was low level, process was zero with door (461-465) back signal 125, does not produce request; When signal 415 is high level, through identical with signal 422 with door (461-465) back signal 125.Fig. 4-b has then provided the realization circuit diagram of 440 modules among Fig. 4-a, and it is with 8 input signals phases or back output.
Table 5
| Route results (signal 123) | Output channel request (signal 422) |
| 000 | 00001 |
| 001 | 00010 |
| 010 | 00100 |
| 011 | 01000 |
| 100 | 10000 |
| 101-111 | xxxxx |
Distributed path control deivce is distributed in each input Virtual Channel place, finishes the routing function to microplate, promptly goes out the output channel of microplate according to current router node address and microplate destination node address choice.Fig. 5 has provided the path control deivce circuit diagram that uses in the router of the present invention.Microplate destination node address 515 is sent into routing algorithm module 510 with present node address 139 and is drawn the passage 513 that select, and selects the result 511 or the new route results 513 of routes last time according to the signal 514 whether needs re-route.Signal 514,515 extracts from signal 124.Real route results also will be subjected to the control of collocation channel, and selector 540 is selected configuration result 517 outputs when disposing effective (signal 516 is a high level), selects route results 512 to export when invalid.When needs re-routed, signal 514 was a high level, and this moment, the route results register enabled effectively, delays at next clock route results 513 is deposited to register 520, and selector 530 selects signal 513 to export as current route results simultaneously.When not needing to re-route, 514 is low level, and the output 511 of selector 530 mask registers 520 is as route results.Fig. 5-b has provided the routing algorithm module of using in current network, it is divided into high-order portion and low portion with the address, at first carry out route during route according to low order address, after equating, low order address carries out route according to the high address again, should be noted that, here just provide a kind of optional routing algorithm, when needs change routing algorithm, only need replace corresponding routing algorithm module and get final product.Fig. 5-c is three congruent comparator circuit figure that use among the 5-b, is output as high level when input signal 521,522 equates, otherwise is low level.Fig. 5-d be use among the 5-b greater than comparison circuit figure, when input signal 523 is output as high level greater than 524 the time, otherwise be low level.Fig. 5-e be use among the 5-b less than comparison circuit figure, only can obtain less than comparison circuit, when input value signal 525 is output as high level less than 526 the time with the input of changing greater than comparator.
Can enter cross bar switch from the data of input channel output.Cross bar switch is connected to each output channel with each input data, and its schematic diagram as shown in Figure 9.Provided two physical channels among the figure, the interconnection situation during two Virtual Channels of each input channel in the cross bar switch, the connection of cross bar switch also needs the corresponding variation of making when number of channels changes, and guarantees that each input Virtual Channel can both link to each other with each output.After entering cross bar switch 910, will be connected to output signal 912 and output signal 913 outputs simultaneously when signal 911.
Input Virtual Channel controller can produce request to each output channel according to routing condition.Request signal is admitted in the distributed arbiter, and moderator obtains corresponding arbitration result according to input request situation and request priority information.Fig. 6 has provided the circuit diagram of distributed arbiter.Moderator receives the request signal 125 from each input Virtual Channel, and the request of 8 input Virtual Channels is provided among the figure, sends into band shielding priority arbitration device 610 in conjunction with priority arbitration mask off code 633.Moderator provides current arbitration result 128 according to certain priority rule and whether arbitration 138 is arranged, and its specific design is introduced in Fig. 7 in detail.Arbitration result 128 obtains new priority through the module 630 that moves to right and represents signal 631 in output, represent signal 632 through the priority that encoder 620 obtains encoding, signal 632 is being deposited in the register 640 behind the clock edge next time, inputs to band shielding priority arbitration device 610 as the priority mask off code 633 of arbitrating next time.Fig. 6-b has provided the circuit diagram of the module that moves to right, and will import one of ring shift right, i.e. sh_gnt[7:0]=gnt[0], gnt[7:1].Fig. 6-c has provided the circuit diagram of encoder 620, and its coding rule is as shown in table 6.
Table 6
| Input value (signal 631) | Encoded radio (signal 632) |
| 00000001 | 000 |
| 00000010 | 001 |
| 00000100 | 010 |
| 00001000 | 011 |
| 00010000 | 100 |
| 00100000 | 101 |
| 01000000 | 110 |
| 10000000 | 111 |
| Other | Xxx |
Fig. 7 has provided the circuit diagram of band shielding priority arbitration device 610.It represents that according to the request 125 of input and the priority of coding 633 provide the arbitration result (128,138) when prepass, and Fig. 7-a has provided whole block diagram.Priority shielded signal 633 at first passes through priority decoder 710, obtaining decoded 8 priority mask off codes 711 sends into and door 730 with raw requests signal 125, output obtains the request 712 after the shielding, 712 through or door 740 whether have after obtaining shielding request signal 713 from the request 712 after raw requests signal 125 and the shielding, to select one to send into fixed priority moderator 720 as request signal 715 as selector 750 selecting sides, select when being high signal 712 for selecting signal when signal 712, be request signal otherwise choose signal 125.Signal 715 is exported current arbitration result 128 through fixing by priority arbitration device 720 backs.Raw requests 125 through or door 760 (circuit obtains the current arbitration 138 that whether has referring to Fig. 4-b).Fig. 7-b has provided the circuit diagram of priority decoder 710, and its decoding rule is as shown in table 7.Fig. 8 has provided the realization circuit diagram of fixed priority moderator.Request signal 714 enters a priority encoder 810, and coding result 811 draws the result of arbitration again by decoder 820.Fig. 8-b provides the circuit diagram of priority encoder 810, and its coding rule is as shown in table 8.Fig. 8-c has provided the circuit diagram of decoder 820, and its decoding rule is as shown in table 9.
Table 7
| Input value (signal 633) | Decode value (signal 711) |
| 000 | 11111111 |
| 001 | 11111110 |
| 010 | 11111100 |
| 011 | 11111000 |
| 100 | 11110000 |
| 101 | 11100000 |
| 110 | 11000000 |
| 111 | 10000000 |
Table 8
| Input value (signal 715) | Encoded radio (signal 811) |
| xxxxxxx1 | 0111 |
| xxxxxx10 | 0110 |
| xxxxx100 | 0101 |
| xxxx1000 | 0100 |
| xxx10000 | 0011 |
| xx100000 | 0010 |
| Input value (signal 715) | Encoded radio (signal 811) |
| x1000000 | 0001 |
| 10000000 | 0000 |
| 00000000 | 1000 |
Table 9
| Input value (signal 811) | Decode value (signal 128) |
| 0000 | 00000001 |
| 0001 | 00000010 |
| 0010 | 00000100 |
| 0011 | 00001000 |
| 0100 | 00010000 |
| 0101 | 00100000 |
| 0110 | 01000000 |
| 0111 | 10000000 |
| 1000 | 00000000 |
By above-mentioned a series of operation, formed a distributed type testing router apparatus.
At last, it is also to be noted that what more than enumerate only is a specific embodiment of the present invention.Obviously, the invention is not restricted to above embodiment, many distortion can also be arranged.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention all should be thought protection scope of the present invention.
Claims (3)
1. distributed type testing on-chip network router is characterized in that comprising:
A plurality of physical transmission channels that number of channels can be prepared are used to provide the transmission of physical data, and width of channel is a microplate width; Input channel can provide a plurality of Virtual Channels, and is each Virtual Channel interpolation microplate buffer memory; The buffer memory width is a microplate width, and the degree of depth can be selected according to hardware resource; Output channel does not provide Virtual Channel and buffer memory; Simultaneously, each I/O channel provides control logic to transmit with the reception of finishing data;
A configuration of routers passage is independent of data transmission network, supports the connectivity test of router;
A plurality of channel link controllers are finished the distribution to input request responding and Virtual Channel, and its quantity is consistent with input channel quantity;
A cross bar switch provides the input Virtual Channel to the full connection between the output channel;
A plurality of distributed path control deivces are distributed in input Virtual Channel place, and according to the routing direction of microplate header decision microplate in the passage, its quantity is consistent with Virtual Channel quantity;
A plurality of distributed arbiters are distributed in the output channel, the ownership ownership of decision output channel when having the request of a plurality of input Virtual Channel to take output channel, and its quantity is consistent with output channel quantity.
2. distributed type testing on-chip network router according to claim 1 is characterized in that: router is operated in a plurality of clock zones, to adapt to the clock request in the network-on-chip; Each input channel of router all is operated in clock zone separately, and clock signal is transmitted by upper level router or resource node, and promptly input channel and upper level router or resource node are operated in same clock zone; Data are transformed into the local clock territory from the input clock territory after entering the Virtual Channel buffer unit, the cross bar switch in the router, distributed path control deivce and these parts of distributed arbiter all are operated in the local clock territory; Data in the router and forwarding these signals of request and local clock are transferred in the network synchronously; The local clock signal of router is also followed data-signal and is transferred to next stage router or resource node together as its input clock.
3. distributed type testing on-chip network router according to claim 2 is characterized in that: the configuration of routers passage provides the support to the test of router connectivity; Collocation channel separates with data transmission network on the sheet, is not subjected to the influence of data transmission network; By configuration the special modality of router is coupled together and be not subjected to that microplate influences in the passage, thereby provide the internuncial test of router; The router preparation is undertaken by the resource node in the network, and it can be processor, digital signal processor or special-purpose preparation module.
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| CN117156006B (en) * | 2023-11-01 | 2024-02-13 | 中电科申泰信息科技有限公司 | Data route control architecture of network on chip |
| CN117176674B (en) * | 2023-11-02 | 2024-02-02 | 上海芯高峰微电子有限公司 | Network-on-chip and data transmission method, chip and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005078465A1 (en) * | 2004-02-17 | 2005-08-25 | Institut National Polytechnique De Grenoble | Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit |
| US20080005402A1 (en) * | 2006-04-25 | 2008-01-03 | Samsung Electronics Co., Ltd. | Gals-based network-on-chip and data transfer method thereof |
-
2008
- 2008-01-25 CN CN2008100593444A patent/CN101232456B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005078465A1 (en) * | 2004-02-17 | 2005-08-25 | Institut National Polytechnique De Grenoble | Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit |
| US20080005402A1 (en) * | 2006-04-25 | 2008-01-03 | Samsung Electronics Co., Ltd. | Gals-based network-on-chip and data transfer method thereof |
Non-Patent Citations (2)
| Title |
|---|
| 谢伦国等.并行计算机互连网络技术-一种工程方法.电子工业出版社,2004,第30-56页,第257-319页. * |
| 饶永.基于虫洞交换技术的片上互连网络路由研究.中国优秀硕士学位论文全文数据库 信息科技辑.2007,I137-11. * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105359471A (en) * | 2013-12-20 | 2016-02-24 | 英特尔公司 | Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks |
| US10230665B2 (en) | 2013-12-20 | 2019-03-12 | Intel Corporation | Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks |
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