CN101231985A - Semiconductor package substrate for improving deform - Google Patents
Semiconductor package substrate for improving deform Download PDFInfo
- Publication number
- CN101231985A CN101231985A CN 200710000296 CN200710000296A CN101231985A CN 101231985 A CN101231985 A CN 101231985A CN 200710000296 CN200710000296 CN 200710000296 CN 200710000296 A CN200710000296 A CN 200710000296A CN 101231985 A CN101231985 A CN 101231985A
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- China
- Prior art keywords
- dielectric layer
- package substrate
- reinforcement
- conductor package
- pliability dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title abstract description 15
- 239000004020 conductor Substances 0.000 claims description 48
- 230000002787 reinforcement Effects 0.000 claims description 45
- 238000003466 welding Methods 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 11
- 230000005540 biological transmission Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
A semiconductor package substrate for preventing deformation mainly comprises a flexible dielectric layer, a plurality of pins, at least one reinforced metal pattern and a solder mask layer. All the pins and the reinforced metal pattern are formed on the same surface of the flexible dielectric layer, and the reinforced metal patterns are used for filling the pin blank section of the flexible dielectric layer. The solder mask layer is formed on the flexible dielectric layer to locally cover the pins and to cover or expose the reinforced metal patterns according to different application. The net-shaped formation positions of the reinforced metal patterns can prevent the flexible dielectric layer from crinkling or deforming.
Description
Technical field
The present invention relates to a kind of semiconductor packages carrier, particularly relate to a kind of conductor package substrate that improves distortion.
Background technology
The conventional semiconductor packages substrate can apply to semiconductor packages operation bearing wafer, but conductor package substrate should have the characteristics such as resistance to deformation of electrical interconnects, high temperature resistant and bearing wafer.In the semiconductor packages operation, wafer engages to solidify with adhesive body and all can make substrate be in the condition of high temperature, and it is higher but the time short that wafer engages the temperature that needs, and it is lower but the time is long that adhesive body solidifies the temperature that needs.Pliability/flexible base plate particularly adds the weight of bearing wafer for a long time in oven, the sinking that two transmission equipment sides of substrate to the section of wafer side deforms is easily subsided, and influences the outward appearance of product, even can cause the difficulty of follow-up surface engagement.
As shown in Figure 1, existing membrane of flip chip N-type semiconductor N packaging structure comprises a unit, a wafer 10 and an adhesive body 20 of semiconductor base plate for packaging 100.This wafer 10 has most projections 11, to be engaged to this conductor package substrate 100.And this adhesive body 20 is formed on this conductor package substrate 100, seals those projections 11.
As shown in Figures 1 and 2, this conductor package substrate 100 comprises a pliability dielectric layer 110, most individual pin 120 and a welding resisting layer 130.Those pins 120 are formed on this pliability dielectric layer 110.This welding resisting layer 130 is formed on this pliability dielectric layer 110, and local those pins 120 that cover.This welding resisting layer 130 has an opening 131, and it appears the inner of those pins 120, to engage those projections 11 of this wafer 10.As shown in Figure 2, two transmission equipment sides of this pliability dielectric layer 110 are formed with most chain holes 111.Usually conventional semiconductor packages substrate 100 in the center that is provided with wafer 10 to the position between two transmission equipment sides with chain hole 111 or the sparse position of other pin can be considered pin and stay the white area, the pin that promptly lacks sufficient amount is to reach structure-reinforced zone, cause the structure at this place thin, the weight that in processing procedure, is subjected to toasting high temperature and wafer distortion such as take place easily to sink to subsiding.
This shows that above-mentioned conventional semiconductor packages substrate obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of conductor package substrate of improvement distortion of new structure, just becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned conventional semiconductor packages substrate exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, conductor package substrate in the hope of the improvement distortion of founding a kind of new structure, can improve general conventional semiconductor packages substrate, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is to provide a kind of conductor package substrate that improves distortion, utilize the reinforcement of weld pattern of netted or other special shape to be formed at pin and stay the white area, can prevent that the pliability dielectric layer from producing the problem of fold or distortion, has the homodisperse effect of stress, preferable toughness is provided and blocks function, the distortion such as take place to sink to subsiding of two transmission equipment sides that particularly can reduce substrate to the section of central authorities.
Of the present invention time a purpose is to provide a kind of conductor package substrate that improves distortion, utilize the netted reinforcement of weld pattern that is aided with other special shape to be formed at pin and stay the white area, have homodisperse effect of stress and the cancellated effect of local reinforcement simultaneously.
Another object of the present invention is to provide a kind of conductor package substrate that improves distortion, the sinking that can the reduce substrate degree of subsiding, the distortion that more can avoid the stress traction to cause.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the present invention, a kind of conductor package substrate that improves distortion mainly comprises a pliability dielectric layer, most pins, at least one reinforcement of weld pattern and welding resisting layers.Those pins are formed on this pliability dielectric layer.This reinforcement of weld pattern is formed on this pliability dielectric layer, stays the white area with the pin of filling up this pliability dielectric layer, and wherein this reinforcement of weld pattern is netted.This welding resisting layer is formed on this pliability dielectric layer, covers those pins with the part.In another embodiment, this reinforcement of weld pattern can include the cross link of most interrupted shapes.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In aforesaid conductor package substrate, this welding resisting layer covers this reinforcement of weld pattern.
In aforesaid conductor package substrate, this reinforcement of weld pattern is revealed in outside this welding resisting layer.
In aforesaid conductor package substrate, this reinforcement of weld pattern more includes most loop circuits.
In aforesaid conductor package substrate, the both sides of this pliability dielectric layer are formed with most chain holes.
In aforesaid conductor package substrate, this reinforcement of weld pattern is near these both sides of this pliability dielectric layer.
In aforesaid conductor package substrate, this pin stays the white area can be between a wafer setting area of these both sides of this pliability dielectric layer and this substrate.
By technique scheme, the conductor package substrate that the present invention improves distortion has following advantage at least:
1, utilizes the reinforcement of weld pattern of netted or other special shape to be formed at pin and stay the white area, prevent that the pliability dielectric layer from producing fold or distortion, has the homodisperse effect of stress, preferable toughness is provided and blocks function, the distortion such as take place to sink to subsiding of two transmission equipment sides that particularly can reduce substrate to the section of central authorities.
2, utilize the netted reinforcement of weld pattern that is aided with other special shape to be formed at pin and stay the white area, have homodisperse effect of stress and the cancellated effect of local reinforcement simultaneously.
3, the sinking that the has reduced substrate degree of subsiding, the distortion of more having avoided the stress traction to cause.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1: the schematic cross-section of conventional semiconductor packages structure.
Fig. 2: conventional semiconductor packages is constructed another schematic cross-section of employed conductor package substrate.
Fig. 3: according to first specific embodiment of the present invention, a kind of end face schematic diagram that improves the conductor package substrate of distortion.
Fig. 4: according to first specific embodiment of the present invention, the schematic cross-section of this conductor package substrate.
Fig. 5: according to second specific embodiment of the present invention, the another kind of end face schematic diagram that improves the conductor package substrate of distortion.
Fig. 6: according to second specific embodiment of the present invention, the schematic cross-section of this conductor package substrate.
Fig. 7: according to the 3rd specific embodiment of the present invention, the another kind of end face schematic diagram that improves the conductor package substrate of distortion.
10: wafer 11: projection
20: adhesive body 100: conductor package substrate
110: pliability dielectric layer 111: the chain hole
120: pin 130: welding resisting layer
131: opening 200: conductor package substrate
210: pliability dielectric layer 211: the chain hole
220: pin 230: the reinforcement of weld pattern
240: welding resisting layer 241: opening
300: conductor package substrate 310: the pliability dielectric layer
311: chain hole 320: pin
330: reinforcement of weld pattern 331: the loop circuit
340: welding resisting layer 341: opening
400: conductor package substrate 410: the pliability dielectric layer
411: chain hole 420: pin
430: reinforcement of weld pattern 431: cross link
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, its embodiment of conductor package substrate, structure, feature and the effect thereof of the improvement distortion that foundation the present invention is proposed, describe in detail as after.
According to first specific embodiment of the present invention, disclose a kind of conductor package substrate that improves distortion.As shown in Figures 3 and 4, this conductor package substrate 200 mainly comprises a pliability dielectric layer 210, most pins 220, at least one reinforcement of weld pattern 230 and welding resisting layers 240.Those pins 220 all are formed on the same surface of this pliability dielectric layer 210 with this reinforcement of weld pattern 230.This pliability dielectric layer 210 is organic dielectric film layer, usually the material of this pliability dielectric layer 210 can be polyimides (polyimide, PI) or polyesters (PET) etc., as the film carrier of those pins 220 with this reinforcement of weld pattern 230, especially can be for coil type transmission carrying out semiconductor packages operation.This conductor package substrate 200 includes most the carrier elements corresponding to encapsulating products.
This reinforcement of weld pattern 230 is formed on this pliability dielectric layer 210, stay the white area with the pin of filling up this pliability dielectric layer 210, refer to not to be formed with the white space of those pins 220, this pin stays the white area can be between a wafer setting area of these both sides of this pliability dielectric layer 210 and this substrate usually.Perhaps according to the various variations of the pin design attitude of substrate, those pins stay the white area can be positioned at other position of this pliability dielectric layer 210.
In the present embodiment, the both sides of this pliability dielectric layer 210 are formed with most chain holes 211, as transmission equipment side.This reinforcement of weld pattern 230 sinks to being out of shape with anti-with the bearing strength of strengthening bearing wafer near these both sides of this pliability dielectric layer 210.This reinforcement of weld pattern 230 is netted, and energy is dispersive stress evenly, preferable toughness to be provided and to block function.
As shown in Figures 3 and 4, this welding resisting layer 240 is formed on this pliability dielectric layer 210, covers those pins 220 with the part, but the inner of those pins 220 and outer end should be and expose.Wherein, this welding resisting layer 240 has out 241, and it appears the inner of those pins 220, for joint wafer.This welding resisting layer 240 can be liquid photosensitive welding cover layer (liquid photoimagable solder mask, LPI), photosensitive cover lay (photoimagable cover layer, PIC) or can be the non-conductive printing ink or the cover layer (cover layer) of general non-photosensitive dielectric material.In the present embodiment, this welding resisting layer 240 more covers this reinforcement of weld pattern 230, to strengthen the structural strengthening effect of this reinforcement of weld pattern 230.
In second specific embodiment, disclose the another kind of conductor package substrate that improves distortion.As Fig. 5 and shown in Figure 6, this conductor package substrate 300 mainly comprises a pliability dielectric layer 310, most pins 320, at least one reinforcement of weld pattern 330 and welding resisting layers 340.The both sides of this pliability dielectric layer 310 are formed with most chain holes 311, in order to the transmission of this conductor package substrate 300.Those pins 320 all are formed on the same surface of this pliability dielectric layer 310 with this reinforcement of weld pattern 330.Wherein, the pin that this reinforcement of weld pattern 330 is filled up this pliability dielectric layer 310 stays the white area, to prevent this pliability dielectric layer 310 buckling deformations.In the present embodiment, this reinforcement of weld pattern 330 is revealed in outside this welding resisting layer 340, can be for eliminating static.This reinforcement of weld pattern 330 more includes most loop circuits 331 to connect those cross hatch except network structure, except having the homodisperse effect of stress, have more the local cancellated effect of strengthening.This welding resisting layer 340 is formed on this pliability dielectric layer 310, covers those pins 320 with the part.Wherein, this welding resisting layer 340 has an opening 341, and it appears the inner of those pins 320, for joint wafer.
As shown in Figure 7, in the 3rd specific embodiment, disclose the another kind of conductor package substrate 400 that improves distortion, mainly comprise a pliability dielectric layer 410, most pins 420 and at least one reinforcement of weld pattern 430.The both sides of this pliability dielectric layer 410 can be formed with most chain holes 411.Those pins 420 are formed on the same surface of this pliability dielectric layer 410 with this reinforcement of weld pattern 430.This reinforcement of weld pattern 430 stays the white area in order to the pin of filling up this pliability dielectric layer 410.In the present embodiment, this reinforcement of weld pattern 430 contains the cross link 431 of most interrupted shapes, because its circuit does not connect, can avoid the stress traction.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (11)
1. conductor package substrate that improves distortion is characterized in that comprising:
One pliability dielectric layer;
A most pin, it is formed on this pliability dielectric layer;
At least one reinforcement of weld pattern, it is formed on this pliability dielectric layer, stays the white area with the pin of filling up this pliability dielectric layer, and wherein this reinforcement of weld pattern is netted; And
One welding resisting layer, it is formed on this pliability dielectric layer, covers above-mentioned pin with the part.
2. conductor package substrate according to claim 1 is characterized in that wherein said welding resisting layer covers the reinforcement of weld pattern.
3. conductor package substrate according to claim 1 is characterized in that wherein said reinforcement of weld pattern is revealed in outside the welding resisting layer.
4. conductor package substrate according to claim 1 is characterized in that wherein said reinforcement of weld pattern more includes most loop circuits, to connect cross hatch.
5. conductor package substrate according to claim 1 is characterized in that the both sides of wherein said reinforcement of weld pattern near the pliability dielectric layer.
6. conductor package substrate according to claim 5 is characterized in that wherein said pin stays the white area between a wafer setting area of the both sides of pliability dielectric layer and substrate.
7. conductor package substrate that improves distortion is characterized in that comprising:
One pliability dielectric layer;
A most pin, it is formed on this pliability dielectric layer;
At least one reinforcement of weld pattern, it is formed on this pliability dielectric layer, stays the white area with the pin of filling up this pliability dielectric layer, and wherein this reinforcement of weld pattern includes the cross link of most interrupted shapes; And
One welding resisting layer, it is formed on this pliability dielectric layer, covers above-mentioned pin with the part.
8. conductor package substrate according to claim 7 is characterized in that wherein said welding resisting layer covers the reinforcement of weld pattern.
9. conductor package substrate according to claim 7 is characterized in that wherein said reinforcement of weld pattern is revealed in outside the welding resisting layer.
10. conductor package substrate according to claim 7 is characterized in that the both sides of wherein said reinforcement of weld pattern near the pliability dielectric layer.
11. conductor package substrate according to claim 10 is characterized in that wherein said pin stays the white area between a wafer setting area of the both sides of pliability dielectric layer and substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710000296 CN100580919C (en) | 2007-01-23 | 2007-01-23 | Semiconductor package substrate for improving deform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710000296 CN100580919C (en) | 2007-01-23 | 2007-01-23 | Semiconductor package substrate for improving deform |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101231985A true CN101231985A (en) | 2008-07-30 |
| CN100580919C CN100580919C (en) | 2010-01-13 |
Family
ID=39898318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710000296 Active CN100580919C (en) | 2007-01-23 | 2007-01-23 | Semiconductor package substrate for improving deform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100580919C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050475A (en) * | 2012-12-18 | 2013-04-17 | 苏州日月新半导体有限公司 | Anti-warping packaging substrate |
| CN103402303A (en) * | 2013-07-23 | 2013-11-20 | 南昌欧菲光电技术有限公司 | Flexible printed circuit board and manufacturing method thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201812816U (en) * | 2010-06-24 | 2011-04-27 | 潮州三环（集团）股份有限公司 | Ceramic packaging base |
-
2007
- 2007-01-23 CN CN 200710000296 patent/CN100580919C/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050475A (en) * | 2012-12-18 | 2013-04-17 | 苏州日月新半导体有限公司 | Anti-warping packaging substrate |
| CN103050475B (en) * | 2012-12-18 | 2015-10-14 | 苏州日月新半导体有限公司 | Anti-warping packaging substrate |
| CN103402303A (en) * | 2013-07-23 | 2013-11-20 | 南昌欧菲光电技术有限公司 | Flexible printed circuit board and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100580919C (en) | 2010-01-13 |
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