CN101231808A - Display device - Google Patents
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- CN101231808A CN101231808A CN 200810003697 CN200810003697A CN101231808A CN 101231808 A CN101231808 A CN 101231808A CN 200810003697 CN200810003697 CN 200810003697 CN 200810003697 A CN200810003697 A CN 200810003697A CN 101231808 A CN101231808 A CN 101231808A
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- 230000003139 buffering effect Effects 0.000 claims abstract description 4
- 238000013500 data storage Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000005059 dormancy Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 30
- 230000009471 action Effects 0.000 description 18
- 238000006073 displacement reaction Methods 0.000 description 13
- TWDJIKFUVRYBJF-UHFFFAOYSA-N Cyanthoate Chemical compound CCOP(=O)(OCC)SCC(=O)NC(C)(C)C#N TWDJIKFUVRYBJF-UHFFFAOYSA-N 0.000 description 6
- 101000743485 Homo sapiens V-set and immunoglobulin domain-containing protein 1 Proteins 0.000 description 4
- 101000743488 Homo sapiens V-set and immunoglobulin domain-containing protein 4 Proteins 0.000 description 4
- 102100038293 V-set and immunoglobulin domain-containing protein 1 Human genes 0.000 description 4
- 102100038296 V-set and immunoglobulin domain-containing protein 4 Human genes 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- ARLKVQYMFRECLV-JSGCOSHPSA-N (2s)-2-[[(2s)-2-amino-3-(1h-indol-3-yl)propanoyl]amino]-4-methylsulfanylbutanamide Chemical compound C1=CC=C2C(C[C@H](N)C(=O)N[C@@H](CCSC)C(N)=O)=CNC2=C1 ARLKVQYMFRECLV-JSGCOSHPSA-N 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 101100283936 Caenorhabditis elegans gsr-1 gene Proteins 0.000 description 1
- 241001269238 Data Species 0.000 description 1
- 101000693970 Homo sapiens Scavenger receptor class A member 3 Proteins 0.000 description 1
- 102100027192 Scavenger receptor class A member 3 Human genes 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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Abstract
A display panel is scanned every two lines during a period of binary writing area in the first half of one frame period in partial display (or in small gradation display) and a steady-state current of an output amplifier for buffering gradation signals supplied to the display panel in a non-scanning period in the second half of one frame period is reduced.
Description
The application is based on the Japan of submitting on January 22nd, 2007 patented claim 2007-010952 and Japan of submitting on January 22nd, 2007 patented claim 2007-011740 formerly formerly, and requiring to enjoy its right of priority, a application in back is all incorporated the application into way of reference.
Technical field
The present invention relates to have the display device and the driving method thereof of multi-grayscale display mode and few gray shade scale display mode (the gray shade scale number lacks than the multi-grayscale display mode), relate in particular to LCD, OLED display, plasma display, field-emitter display and driving method thereof.
And, the present invention relates to reduce the display device of the consumed power when partly showing.
Background technology
U.S.'s publication 2005/0179677 (TOHKEMY 2005-234029 communique) discloses a kind of image display device, this device used for image display when multirow selects part to show non-display area and carry out signal and write, possesses the sweep circuit that constitutes by shift register and AND circuit, described shift register and Hsync carry out data transmission synchronously, and described AND circuit serves as that the basis generates output signal with the output signal and the Enable signal of shift register.The Hi level time that makes the enabling signal of input shift register is a plurality of horizontal cycles---4 horizontal cycles for example, make the Enable signal in a plurality of horizontal cycles, having only a horizontal cycle---for example having only a horizontal cycle in 4 horizontal cycles is the signal of Hi level, by the sweep circuit that can realize that like this multirow (4 horizontal line) is simultaneously selected.
U.S. Register patent 6781605 (TOHKEMY 2002-366115 communique) discloses a kind of display device, the display gray scale number of degrees reduces to flow through in the circuit that generates a plurality of grayscale voltages after a little while, generate show the electric current that flows through in the circuit part (ladder resistance) of unwanted grayscale voltage.
And,,, be difficult to realize the part display mode if do not reduce the consumed power of part when showing in the display device of carrying.
Put down in writing a kind of display device in the United States Patent (USP) 7123247 (TOHKEMY 2006-3923 communique), each frame period turntable driving part viewing area of this display device, non-display area beyond every odd-numbered frame intermittent scanning drive part viewing area has reduced consumed power thus.
Because even the action (clock signal etc.) of selecting shift register under the situation that multirow writes at the same time is the same during also with normal demonstrations, so U.S.'s publication 2005/0179677 (TOHKEMY 2005-234029 communique) is carrying out being difficult to reduce shift register consumed power partly under the situation that part shows.Even owing to black data is being write under the situation of non-display area, carry out voltage with the ratio of 1 horizontal period in a plurality of horizontal period and write, so U.S.'s publication 2005/0179677 (TOHKEMY 2005-234029 communique) is difficult to stop output amplifier for a long time and cut down firm power.
Owing to only reduce to generate the electric current that flows through in the circuit part that shows the unwanted grayscale voltage of institute, so U.S. Register patent 6781605 (TOHKEMY 2002-366115 communique) reduction consumed power is insufficient.
And, as record in the United States Patent (USP) 7123247 (TOHKEMY 2006-3923 communique), when carrying out the part demonstration with the frame upset, when showing the such display pattern of tartan or horizontal stripe in the part viewing area, because the frequency height of this display pattern, so the power of drive signal line becomes big.
Summary of the invention
Purpose of the present invention is exactly that a kind of display device and driving method thereof that has reduced consumed power will be provided.Especially the deterioration of image quality and the consumed power of reduction driving circuit in the time of will suppressing part demonstration or few gray shade scale demonstration.
And, the objective of the invention is to provide a kind of image quality that part shows, display device that has reduced consumed power of can not worsening.
In the 1st display mode (for example non-part demonstration, multi-grayscale show), display panel of every n (n is the integer more than 1) line scanning in during 1 image duration whole, (for example part shows at the 2nd display mode, few gray shade scale shows) in, (for example between first-half period) every m during the part in 1 image duration (m for be big integer than n) once above-mentioned display panel of line scanning, the other times in 1 image duration (between for example between latter half) reduce to drive the electric current that flows through in the driving circuit (for example buffer amplifier) of display panel.
For example, sweep circuit is made of shift register and AND circuit, described shift register will only move 2 horizontal cycles for the input signal of Hi level in 2 horizontal period, described AND circuit is used for that (the Hi level: 2 horizontal period) time is assigned to 2 horizontal period, and 2 drive clock of distributing according to the time that is input in the AND circuit are selected horizontal line successively and shown with the output data of shift register.When part shows (demonstrations of 8 looks), cycle of the control clock of shift register is shortened to 1/2, carry out the selections simultaneously of 2 row by making 2 drive clock same-phases.Because the electric capacity that signal is write fashionable domination is the drain line electric capacity, though therefore select simultaneously times that 2 row write also can with normal condition under identical, can be shortened to half under the normal condition write time of a picture.Reduce to drive the steady current of the amplifier of drain line in during not scanning.And the shift register of interscan circuit also stops during this period.
In the part viewing area according to display pattern switch frame upset or row upset, the non-display area frame upset beyond in the part viewing area.
When carrying out the part demonstration, carry out the frame upset or the AC signal of overturning of going according to the control signal generation that the indicating section from the outside shows.Utilize this AC signal that the every row of common electric voltage or every frame are overturn.And relatively the video data of 2 row generates AC signal.
According to the present invention,, therefore can reduce the consumed power of driving circuit because the other times in 1 image duration reduce to drive the electric current that flows through in the driving circuit of display panel.That is, because therefore the steady current that can reduce the amplifier of signal efferent not sweep time in 1 image duration can cut down consumed power.
According to the present invention and since can be provided with make that shift register stops during, therefore can stop to drive the power supply relation of shift register at stopping period, can cut down consumed power.Owing to can fully guarantee the write time image quality aggravation in the time of therefore can suppressing partly to show.And,, therefore can suppress circuit scale and increase owing to carry out in the sweep circuit not needing special signal when part shows.
According to the present invention, owing to the every row of common electric voltage or every frame are overturn and show display pattern, therefore can reduce the power that discharges and recharges of the signal voltage that offers signal wire, can expect low-powerization.And, owing to, therefore guarantee low-power with the fixing non-display part of frame upset.And owing to also be that part shows (8 look) when comparing the video data of 2 row, therefore data volume relatively is few, so the enough little circuit scales of energy are realized.
Description of drawings
The structural drawing of the display device of Fig. 1 embodiments of the invention 1.
The interior block diagram of the image signal generating circuit of Fig. 2 embodiments of the invention 1.
The cut-away view of the output circuit of Fig. 3 embodiments of the invention 1.
The structural drawing of the sweep circuit of Fig. 4 embodiments of the invention 1.
The structural drawing of the selection circuit of Fig. 5 embodiments of the invention 1.
Timing diagram when the non-part of Fig. 6 embodiments of the invention 1 shows.
Timing diagram when having shortened sweep time under the part display mode of Fig. 7 embodiments of the invention 1.
Other timing diagrams that the part of Fig. 8 embodiments of the invention 1 shows.
The display frame of Fig. 9 embodiments of the invention 1.
The structural drawing of the sweep circuit of Figure 10 embodiments of the invention 2.
The structural drawing of the selection circuit of Figure 11 embodiments of the invention 2.
Timing diagram when the non-part of Figure 12 embodiments of the invention 2 shows.
Timing diagram when having shortened sweep time under the part display mode of Figure 13 embodiments of the invention 2.
Other timing diagrams that the part of Figure 14 embodiments of the invention 2 shows.
The display frame of Figure 15 embodiments of the invention 2.
The structural drawing of Figure 16 display device of the present invention.
The interior block diagram of the signal voltage generation circuit 11 that Figure 17 is shown in Figure 16.
The interior block diagram of the gated sweep circuit 13 that Figure 18 is shown in Figure 16.
The interior block diagram of the common scanning circuit 12 that Figure 19 is shown in Figure 16.
The display image of Figure 20 display part.
Timing diagram when Figure 21 carries out normal show shown in Figure 20 (a).
Timing diagram when Figure 22 partly shows the display pattern of the tartan shown in Figure 20 (b).
Timing diagram when Figure 23 partly shows white square display pattern shown in Figure 20 (c).
Other block schemes of the signal voltage generation circuit 11 that Figure 24 is shown in Figure 16.
The block scheme of the interchange decision circuitry 91 that Figure 25 is shown in Figure 24.
The display image of Figure 26 display part.
Figure 27 judges the output map of signal MSEL.
Figure 28 represents the timing diagram of the action of interchange decision circuitry 91 shown in Figure 25.
Timing diagram when Figure 29 shows display pattern shown in Figure 26.
Embodiment
[embodiment 1]
Fig. 1 is the structural drawing of the display device of embodiments of the invention 1.1 is the display panel that a plurality of pixel arrangement become matrix shape among Fig. 1; 2 is to generate the power circuit that shows necessary grayscale voltage by supply voltage; 3 is from control signal or setting value and video datas such as peripheral unit (for example MPU of portable phone) input PSL signal, synchronizing signals, generates and export the control circuit of control signal; 4 is the interim storer of preserving video data, and 5 for will be applied to the image signal generating circuit of drain line D1～Dm with the corresponding grayscale voltage of video data, 6 sweep circuits for each row or gate lines G a 1～Gn of every a few line scanning.
Fig. 2 is the interior block diagram of the image signal generating circuit of embodiments of the invention 1.51 and 52 is the data-latching circuit that latchs the video data of 1 amount of going among Fig. 2, and 53 for being transformed into digitized video data in the DA transducer of analog gray scale voltage gradation, and 54 for being applied to grayscale voltage the output circuit on drain line D1～Dm.
The control signal group comprises timing signal, according to the PSL signal distinguishing partly shows and non-part shows signal.When non-part showed, as shown in Figure 6, image signal generating circuit 5 was transformed into a plurality of grayscale voltage VDH～VDL and output with video data.On the other hand, when part showed, as Fig. 7, shown in Figure 8, image signal generating circuit 5 was transformed into 2 values (VPH, VPL) and output with it.
Data-latching circuit 51 is imported video data successively according to the control signal group, the video data of the amount of output 1 row.Data-latching circuit 52 keeps a horizontal cycle according to the video data of the amount of control signal group input 1 row, the video data of the amount of output 1 row.DA transducer 53 is selected corresponding each grayscale voltage of each video data in the video data with the amount of 1 row according to the control signal group from a plurality of grayscale voltages of power circuit 2 output.Output circuit 54 is applied to each grayscale voltage on each drain line.
Fig. 3 is the inner structure of the output circuit of embodiments of the invention 1.541 output amplifiers for the buffering grayscale voltage among Fig. 3,542 and 543 is the current control circuit of the steady current of control output amplifier 541.Article 1, on the drain line D (x) 1 output amplifier 541 is set.
BIAS signal (aanalogvoltage) is included in the control signal group of control circuit 3 outputs. Current control circuit 542 and 543 preferred MOS switches.The grid of BIAS signal input MOS switch is by the steady current of BIAS voltage of signals value control output amplifier 541.
Fig. 4 is the structural drawing of the sweep circuit of embodiments of the invention 1.61 is shift register among Fig. 4, and 62 for according to the selection circuit of the GCK signal (gated clock signal) that comprises in the output signal of shift register 61 and the control signal group to gate line output gating signal.Be provided with one on per 2 gate lines and select circuit 62.
ST signal (enabling signal), SCK signal (shift clock signal) A and SCK signal (shift clock signal) B that shift register 61 inputs comprise from the control signal group of control circuit 3 outputs, output SR signal (shift LD signal) 1～s (s for example is n/2).Select circuit 62 by the time distribution gating signal to be exported to 2 gate lines according to GCK signal (gated clock signal) A that comprises the SR signal 1～s that exports from shift register 61, the control signal group and GCK signal (gated clock signal) B.
Fig. 5 is the structural drawing of the selection circuit of embodiments of the invention 1.621 and 622 is logical circuit among Fig. 5.Though preferably (be connected level shift diode between the G signal 1～n), also can be arranged on other place with the output of selecting circuit 62 in output signal (logic amplitude) from control circuit 3.
Fig. 6 is the timing diagram of the non-part of embodiments of the invention 1 when showing.The PSL signal was a low level when non-part showed.Only electric current I (nml) when being set at non-part and driving for the steady current Icnt with output amplifier 541 is the V (nml) that non-part shows usefulness with the BIAS signal sets.The output amplifier 541 shared BIAS signals of all drain line D1～Dm.
The ST signal is the signal that changes to high level from low level in per 1 image duration.The SCK signal is the signal that changes repeatedly between inherent low level of per 2 horizontal cycles and the high level.SCK signal A is a high level in initial 2 horizontal cycles of 1 image duration, and SCK signal B is a high level in 2 horizontal cycles subsequently.The GCK signal is the signal that changes repeatedly between inherent high level of per 1 horizontal cycle and the low level.GCK signal A 1 initial horizontal cycle in 1 frame period is a high level, and GCK signal B is a high level at a horizontal cycle subsequently.The SR signal is the signal of high level for being the cycle with the frame in 2 horizontal cycles.SR signal 1 is a high level in initial 2 horizontal cycles of 1 image duration.SR signal 2 is a high level in 2 horizontal cycles subsequently.SR signal 3 is a high level in subsequently 2 horizontal cycles again.That is, SR signal 1～s become high level during be per 2 horizontal cycles displacement.G signal (gating signal) is the signal of high level for being the cycle with the frame in a horizontal cycle.G signal 1 is high level in 1 image duration in initial 1 horizontal cycle.G signal 2 is a high level at next horizontal cycle.G signal 3 is a high level at next horizontal cycle again.That is, G signal 1～n be high level during the displacement of each horizontal cycle.
When the ST signal is high level, at SCK signal A is (2 horizontal cycles) between high period, shift register 61 makes SR signal 1 be high level, being that (2 horizontal cycles) makes SR signal 2 be high level between high period at SCK signal B then, is that (2 horizontal cycles) makes SR signal 3 be high level between high period at SCK signal A then again.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal A, select the logical circuit 621 of circuit 62 to make G signal 1 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal B, select the logical circuit 622 of circuit 62 to make G signal 2 be high level.On the other hand, at each horizontal cycle, apply and the corresponding grayscale voltage D of video data (x) to each drain line D1～Dm from image signal generating circuit 5.That is, the pixel of a display panel of each line scanning in non-part shows applies and the corresponding grayscale voltage of video data for each pixel.
Fig. 7 is the timing diagram when having shortened sweep time under the part display mode of embodiments of the invention 1.The PSL signal is a high level under the part display mode.The first-half period of 1 image duration scans all pixel columns (between active stage) successively under the part display mode, does not scan any pixel column (between rest period) between the latter half of 1 image duration.And, under the part display mode, the first-half period of 1 image duration is V (ps) with the BIAS signal sets, the steady current Icnt of output amplifier 541 is set at I (ps), between the latter half of 1 image duration, be V (slp), the steady current Icnt of output amplifier 541 is set at I (slp) the BIAS signal sets.Make V (nml)＞V (ps)＞V (slp), by making I (nml)＞I (ps)＞I (slp) like this.Therefore, (power of output amplifier 541 when non-part shows)＞(when part shows between active stage the power of output amplifier 541)＞(when part shows between rest period the power of output amplifier 541).Electric current when I (slp) is in halted state or dormant state for output amplifier 541.Therefore, the part display mode can reduce the consumed power of output amplifier.
The ST signal changed to high level from low level in per 1 image duration.The SCK signal changes between low level and high level in each horizontal cycle repeatedly at the first-half period of 1 image duration, becomes low level between the latter half of 1 image duration.In initial 1 horizontal cycle of SCK signal A in 1 image duration is high level, and SCK signal B is a high level in 1 horizontal cycle subsequently, and between the latter half of 1 image duration, SCK signal A and SCK signal B are low level.GCK signal A and GCK signal B are that the first-half period in an image duration is a high level, are low level between the latter half of 1 image duration.The SR signal is high level at the first-half period of an image duration in a horizontal cycle, is low level between the latter half of an image duration.SR signal 1 is a high level in the initial horizontal cycle in an image duration.SR signal 2 is high level in next horizontal cycle.SR signal 3 is a high level in subsequently 1 horizontal cycle again.That is, SR signal 1～s become high level during be per 1 horizontal cycle displacement.G signal (gating signal) is high level at the first-half period of an image duration in 1 horizontal cycle, is low level between the latter half of an image duration.G signal 1 and G signal 2 all are to be high level in 1 image duration in initial 1 horizontal cycle.G signal 3 and G signal 4 all are to be high level at next horizontal cycle.G signal 5 and G signal 6 all are to be high level at next horizontal cycle again.That is, G signal 1～n is one group with 2 adjacent G signals, become high level during be each horizontal cycle displacement.
When the ST signal is high level, at SCK signal A is (1 horizontal cycle) between high period, shift register 61 makes SR signal 1 be high level, being that (1 horizontal cycle) makes SR signal 2 be high level between high period at SCK signal B then, is that (1 horizontal cycle) makes SR signal 3 be high level between high period at SCK signal A then again.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal A, select the logical circuit 621 of circuit 62 to make G signal 1 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal B, select the logical circuit 622 of circuit 62 to make G signal 2 be high level.On the other hand, at each horizontal cycle, from image signal generating circuit 5 to each drain line D1～Dm apply with corresponding 2 grayscale voltages of video data some voltage D (x), between the latter half of 1 image duration, do not apply any grayscale voltage.
Make control signals of shift registers (ST signal, SCK signal A, the SCK signal B) cycle shorten 1/2, gate line is selected to be made as in-phase signal with GCK signal A, GCK signal B, output at every turn in each horizontal cycle, thus, the part display mode can be rewritten the voltage of all horizontal scanning lines in the half the time of non-part display mode.And, owing to make the voltage that is applied on the pixel only for controlling these 2 values of VPL, VPH of ON/OFF, even 2 value controls (RGB is shown as 8 looks and shows) also are not easy to produce image quality aggravation, and are therefore optimum by the steady current that makes output amplifier, can make it than generally speaking little.
Under the part display mode, the first-half period of 1 image duration does not scan any pixel column (between rest period), scans all pixel columns (between active stage) between the latter half of 1 image duration successively.And, needn't be half of 1 image duration between active stage and between rest period.If make between active stage than long between rest period, then can improve image quality; If make between rest period than long between active stage, then can further reduce consumed power.
Though not expression among the figure, but owing to do not need to make shift register action between the latter half of 1 image duration, therefore make power supply that shift register work uses or the steady current that generates the amplifier of control signal group (ST signal, SCK signal, GCK signal) usefulness be in dormant state.Thus, the part display mode can reduce the consumed power of sweep circuit 6.And, though not expression among the figure, but under the part display mode, the circuit that generate to show institute's unwanted grayscale voltage (for example removing the grayscale voltage of minimum and maximum centre) is quit work, between the latter half of 1 image duration (between rest period) circuit of all grayscale voltages of generation is quit work.Thus, under the part display mode, can reduce the consumed power of power circuit 2.And, between the latter half of 1 image duration, also can reduce the electric current that flows through in power circuit 2, image signal generating circuit 5 and the sweep circuit 6, power circuit 2, image signal generating circuit 5 and sweep circuit 6 are quit work or be in dormant state.
Fig. 8 is other a timing diagram of the part display mode of embodiments of the invention 1.Different with Fig. 7, not only be provided with between rest period, and prolongation (has been approximately normal 2 times) write time of every row (scan period).Thus, the steady current of output amplifier is suppressed at very little, reduces consumed power.
The ST signal changed to high level from low level in per 1 image duration.The SCK signal changes between low level and high level in per 2 horizontal cycles repeatedly.SCK signal A is a high level in initial 2 horizontal cycles of 1 image duration, and SCK signal B is a high level in 2 horizontal cycles subsequently.GCK signal A and GCK signal B are high level in the whole time of 1 image duration.The SR signal is the cycle with the frame, is high level in 2 horizontal cycles.Initial 2 horizontal cycles of SR signal 1 in 1 image duration are high level.SR signal 2 is a high level in 2 horizontal cycles subsequently.SR signal 3 is a high level in subsequently 2 horizontal cycles again.That is, SR signal 1～s become high level during be per 2 horizontal cycles displacement.G signal (gating signal) is the cycle with the frame, is high level in 2 horizontal cycles.G signal 1 and G signal 2 are high level in 1 image duration in initial 2 horizontal cycles.G signal 3 and G signal 4 are high level at following 2 horizontal cycles.G signal 5 and G signal 6 are high level at following 2 horizontal cycles again.That is, G signal 1～n is one group with 2 adjacent G signals, become high level during be per 2 horizontal cycles displacement.
When the ST signal is high level, at SCK signal A is (2 horizontal cycles) between high period, shift register 61 makes SR signal 1 be high level, being that (2 horizontal cycles) makes SR signal 2 be high level between high period at SCK signal B then, is that (2 horizontal cycles) makes SR signal 3 be high level between high period at SCK signal A then again.When SR signal 1 is high level, be (2 horizontal cycles) between high period at GCK signal A, select the logical circuit 621 of circuit 62 to make G signal 1 be high level.When SR signal 1 is high level, be (2 horizontal cycles) between high period at GCK signal B, select the logical circuit 622 of circuit 62 to make G signal 2 be high level.On the other hand, at per 2 horizontal cycles, from image signal generating circuit 5 to each drain line D1～Dm apply with corresponding 2 grayscale voltages of video data some voltage D (x).That is, the pixel of a display panel of per 2 line scannings under the part display mode, apply with corresponding 2 grayscale voltages of video data in some voltage D (x).
Fig. 9 (a) is the display frame (corresponding with Fig. 6) that the non-part of embodiments of the invention 1 shows.And Fig. 9 (b) is the display frame (corresponding with Fig. 7 or Fig. 8) that the part of embodiments of the invention 1 shows.
The corresponding brightness of video data (for example 6 bits or 8 bits) of each pixel demonstration and multi-grayscale under the non-part display mode.Per 2 row pixels show and the corresponding brightness of video data (for example 1 bit) of lacking gray shade scale under the part display mode.The resolution of vertical direction reduce part because therefore 2 row are selected simultaneously when showing, but the special demonstration that is called " part shows " be out of question when (for example the clock of portable phone etc. or information receiving state etc. do not need the information of resolution) (especially panel resolution is under the contour situation of VGA).
[embodiment 2]
Fig. 1 to Fig. 3 and embodiment 1 are shared.
Figure 10 is the structural drawing of the sweep circuit 6 of embodiments of the invention 2.63 is shift register among Figure 10, and 64 for selecting circuit.Corresponding 4 gate lines are provided with one and select circuit 64.
Input comprises from the control signal group of control circuit 3 outputs in the shift register 63 ST signal, SCK signal A and SCK signal B, output SR signal 1～s (s for example is n/4).Select circuit 64 according to the GCK signal A, GCK signal B, GCK signal C and the GCK signal D that comprise the SR signal 1～s that exports from shift register 63, the control signal group, distribute by the time gating signal is exported to 4 gate lines.
Figure 11 is the structural drawing of the selection circuit of embodiments of the invention 2.641～644 is logical circuit among Figure 11.
Figure 12 is the timing diagram of the non-part of embodiments of the invention 2 when showing.The meaning of PSL, BIAS, Icnt etc. is identical with embodiment 1.
The ST signal is the signal that changes to high level from low level in per 1 image duration.The SCK signal is the signal that changes repeatedly between inherent low level of per 4 horizontal cycles and the high level.SCK signal A is a high level in initial 4 horizontal cycles of 1 image duration, and SCK signal B is a high level in 4 horizontal cycles subsequently.The GCK signal is signal that horizontal cycle is a high level in the cycle of 4 horizontal cycles.GCK signal A 1 image duration 1 initial horizontal cycle be high level, GCK signal B is a high level at a horizontal cycle subsequently, GCK signal C is a high level at subsequently a horizontal cycle again, GCK signal D is a high level at a horizontal cycle more subsequently.That is, GCK signal A～D be high level during be each horizontal cycle displacement.The SR signal is to be the signal of high level in 4 horizontal cycles.SR signal 1 is high level in 1 image duration in initial 4 horizontal cycles.SR signal 2 is a high level in 4 horizontal cycles subsequently.SR signal 3 is a high level in subsequently 4 horizontal cycles again.That is, SR signal 1～s become high level during per 4 horizontal cycles move.And, the cycle of SR signal 1～s and the cycle synchronisation of frame.G signal (gating signal) is to be the signal of high level in a horizontal cycle.G signal 1 is high level in 1 image duration in initial 1 horizontal cycle.G signal 2 is a high level at next horizontal cycle.G signal 3 is a high level at next horizontal cycle again.That is, G signal 1～n be high level during each horizontal cycle move.And, the cycle of G signal 1～n and the cycle synchronisation of frame.
When the ST signal is high level, at SCK signal A is (4 horizontal cycles) between high period, shift register 63 makes SR signal 1 be high level, being that (4 horizontal cycles) makes SR signal 2 be high level between high period at SCK signal B then, is that (4 horizontal cycles) makes SR signal 3 be high level between high period at SCK signal A then again.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal A, select the logical circuit 641 of circuit 64 to make G signal 1 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal B, select the logical circuit 642 of circuit 64 to make G signal 2 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal C, select the logical circuit 643 of circuit 64 to make G signal 3 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal D, select the logical circuit 644 of circuit 64 to make G signal 4 be high level.On the other hand, at each horizontal cycle, apply and the corresponding grayscale voltage D of video data (x) for each drain line D1～Dm from image signal generating circuit 5.That is, under non-part display mode, the pixel of a display panel of each line scanning applies and the corresponding grayscale voltage of video data to each pixel.
Figure 13 is the timing diagram when having shortened sweep time under the part display mode of embodiments of the invention 2.Carry out part with whole image among Figure 13 and show, promptly in whole image, show video data.Drive simultaneously in order to carry out 2 row, making the cycle of the control signal (ST signal, SCK signal A, SCK signal B and GCK signal) of shift register 63 is 1/2, and makes 4 GCK signal A=GCK signal B, GCK signal C=GCK signal D in the GCK signal).For in order to carry out that part shows and (non-scan period) makes output amplifier stop output current to the inhibition of output amplifier electric current and between rest period in scan period, can obtain the effect identical with embodiment 1.
The ST signal changed to high level from low level in per 1 image duration.The SCK signal changes between high level and low level in per 2 horizontal cycles repeatedly at the first-half period of 1 image duration, becomes low level between the latter half of 1 image duration.SCK signal A is a high level in initial 2 horizontal cycles of 1 image duration, and SCK signal B is a high level in 2 horizontal cycles subsequently, and between the latter half of 1 image duration, SCK signal A and SCK signal B are low level.The GCK signal changes between high level and low level in per 1 horizontal cycle repeatedly at the first-half period of 1 image duration, becomes low level between the latter half of 1 image duration.GCK signal A and GCK signal B are high level in 1 image duration in initial 1 horizontal cycle.GCK signal C and GCK signal D are high level in next horizontal cycle.The SR signal is high signal at the first-half period of an image duration in 2 horizontal cycles, is low level between the latter half of an image duration.SR signal 1 is a high level in initial 2 horizontal cycles in an image duration.SR signal 2 is a high level in 2 horizontal cycles subsequently.SR signal 3 is a high level in subsequently 2 horizontal cycles again.That is, SR signal 1～s become high level during be per 2 horizontal cycles displacement.G signal (gating signal) is high level at the first-half period of an image duration in 1 horizontal cycle, is low level between the latter half of an image duration.G signal 1 and G signal 2 all are to be high level in 1 image duration in initial 1 horizontal cycle.G signal 3 and G signal 4 all are to be high level at next horizontal cycle.G signal 5 and G signal 6 all are to be high level at next horizontal cycle again.That is, G signal 1～n is one group with 2 adjacent G signals, become high level during be each horizontal cycle displacement.
When the ST signal is high level, at SCK signal A is (2 horizontal cycles) between high period, shift register 63 makes SR signal 1 be high level, being that (2 horizontal cycles) makes SR signal 2 be high level between high period at SCK signal B then, is that (2 horizontal cycles) makes SR signal 3 be high level between high period at SCK signal A then again.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal A, select the logical circuit 641 of circuit 64 to make G signal 1 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal B, select the logical circuit 642 of circuit 64 to make G signal 2 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal C, select the logical circuit 643 of circuit 64 to make G signal 3 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal D, select the logical circuit 644 of circuit 64 to make G signal 4 be high level.On the other hand, at each horizontal cycle, from image signal generating circuit 5 to each drain line D1～Dm apply with corresponding 2 grayscale voltages of video data some voltage D (x), between the latter half of 1 image duration, do not apply any grayscale voltage.
Figure 14 is other a timing diagram of the part display mode of embodiments of the invention 2.The part demonstration is carried out in the first half zone among Figure 14, and remaining the latter half zone does not show (the black demonstration).In non-demonstration (the black demonstration) zone, the resolution of selecting simultaneously to cause reduces unquestionable.Therefore, by selecting 4 row can make non-scan period longer simultaneously.Thus, because the time that makes output amplifier become dormant state increases, therefore can realize low consumpting power.
The ST signal changed to high level from low level in per 1 image duration.The SCK signal the 1 first-half period image duration scan period of viewing area (complete) 2/3 during (2 values as the viewing area write the zone) variation repeatedly between high level and low level in per 2 horizontal cycles, 1 image duration first-half period residue 1/3 during (as the black zone that writes of non-display area) in each horizontal cycle, between high level and low level, change repeatedly, be low level in (beyond the scan period of full viewing area during) between the latter half of 1 image duration.SCK signal A is a high level in initial 2 horizontal cycles of 1 image duration, and SCK signal B is a high level in 2 horizontal cycles subsequently, and between the latter half of 1 image duration, SCK signal A and SCK signal B are low level.The GCK signal 1 image duration first-half period 2/3 during (2 values write the zone) in per 1 horizontal cycle, between high level and low level, change repeatedly, 1 image duration first-half period residue 1/3 during (black write zone) be high level, be low level between the latter half of 1 image duration.GCK signal A and GCK signal B are high level in 1 horizontal cycle initial in 1 image duration, be low level between the latter half of 1 image duration.GCK signal C and GCK signal D are high level in next horizontal cycle, be low level between the latter half of 1 image duration.The SR signal is for being the cycle with the frame, 1 image duration first-half period 2/3 during (2 values write the zone) in 2 horizontal cycles for high level, (the black zone that writes) is high level in a horizontal cycle during 1 image duration first-half period remaining 1/3, is low level between the latter half of 1 image duration.In initial 2 horizontal cycles of SR signal 1 in 1 image duration is high level.SR signal 2 is a high level in 2 horizontal cycles subsequently.SR signal 3 is a high level in subsequently 2 horizontal cycles again.Promptly, SR signal 1～s 1 image duration first-half period 2/3 during (2 values write the zone) become high level during be per 2 horizontal cycles displacement, (the black zone that writes) during the 1 image duration first-half period remaining 1/3 become high level during each horizontal cycle move.G signal (gating signal) is high level at the first-half period of 1 image duration in a horizontal cycle, is low level between the latter half of 1 image duration.G signal 1 and G signal 2 that 2 values write the zone all are to be high level in 1 image duration in initial 1 horizontal cycle.G signal 3 and G signal 4 that 2 values write the zone are high level in next horizontal cycle.G signal 5 and G signal 6 that 2 values write the zone all are to be high level in a horizontal cycle subsequently.Black G signal 9, G signal 10, G signal 11 and the G signal 12 that writes the zone all is to be high level in initial 1 horizontal cycle during 1 image duration first-half period remaining 1/3.Promptly, G signal 1～n 1 image duration first-half period 2/3 during (2 values write the zone) be one group with 2 adjacent G signals, become high level during be per 1 horizontal cycle displacement, during 1 image duration first-half period remaining 1/3 (the black zone that writes), with 4 adjacent G signals is one group, become high level during be per 1 horizontal cycle displacement.
When the ST signal is high level, at SCK signal A is between high period, shift register 63 makes SR signal 1 be high level, is that high period chien shih SR signal 2 is high level at SCK signal B then, is that high period chien shih SR signal 3 is high level at SCK signal A then again.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal A, select the logical circuit 641 of circuit 64 to make G signal 1 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal B, select the logical circuit 642 of circuit 64 to make G signal 2 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal C, select the logical circuit 643 of circuit 64 to make G signal 3 be high level.When SR signal 1 is high level, be (1 horizontal cycle) between high period at GCK signal D, select the logical circuit 644 of circuit 64 to make G signal 4 be high level.On the other hand, the first-half period of 1 image duration 2/3 during in (2 values write the zone), each horizontal cycle give from image signal generating circuit 5 each drain line D1～Dm apply with corresponding 2 grayscale voltages of video data some voltage D (x); During 1 image duration first-half period remaining 1/3, in (the black zone that writes), during each horizontal cycle, apply and the corresponding grayscale voltage of black data; Between the latter half of 1 image duration, do not apply any grayscale voltage.
Figure 15 (a) is the display frame (corresponding with Figure 12) that the non-part of embodiments of the invention 2 shows.And, the display frame (corresponding) that Figure 15 (b) partly shows for the whole image of embodiments of the invention 2 with Figure 13.Figure 15 (c) is the display frame (corresponding with Figure 14) that the first half zone of the whole image of embodiments of the invention 2 shows for part.
The whole image of part viewing area (Figure 15 (b)) and the subregional resolution of the first half of Figure 15 (c) are low identical with embodiment 1.
The present invention can be used in the LCD of portable phone.
[embodiment 3]
Figure 16 is the structural drawing of display device of the present invention.Among Figure 16, be input to the signal voltage generation circuit 11 from the outside with input signal INPUT_SIG and control signal REG, signal voltage generation circuit 11 generates the signal voltage that is applied on the signal wire SIGn (n=1～N, N are integer) according to input signal INPUT_SIG.And signal voltage generation circuit 11 generates the AC signal M that offers common scanning circuit 12 according to the control signal REG of input.
And, signal voltage generation circuit 11 generates the sweep signal SFT_ST that offers common scanning circuit 12 and gated sweep circuit 13 according to the synchronizing signal among the input signal INPUT_SIG, and generates high level common electric voltage VCOMH and the low level common electric voltage VCOML that offers common scanning circuit 12.
Sweep signal SFT_ST and AC signal M that common scanning circuit 12 uses input select the high level common electric voltage VCOMH of input and any voltage among the low level common electric voltage VCOML, drive concentric line COMn (n=1～N, N are integer).
Thin film transistor (TFT) 14 is connected on the cross part of gate lines G n and signal wire SIGn, drives display element 15 by this thin film transistor (TFT) 14.Gate lines G n of every line scanning, apply from signal voltage of each next row of signal wire SIGn and each common electric voltage of going that comes from concentric line COMn to display element, thus, each row drive thin film transistors 14 and display element 15, carry out this process in an image duration repeatedly, show and the corresponding image of signal voltage.
Figure 17 is the interior block diagram of signal voltage generation circuit 11 shown in Figure 16.Among Figure 17, input signal INPUT_SIG stores in the storer 22 by control circuit 21.Control circuit 21 control stores 22 and DAC/ output circuit 23, the data conversion that will read from storer 22 with DAC/ output circuit 23 becomes signal voltage VSIG.And control signal REG stores in the register 24, reads with control circuit 21, and control circuit 21 usefulness AC signal generative circuits 25 generate AC signal M.And control circuit 21 generates sweep signal SFT_ST according to the synchronizing signal among the input signal INPUT_SIG with sweep signal generative circuit 26.In addition, high level common electric voltage VCOMH and low level common electric voltage VCOML are generated by common voltage generation circuit 27.
When showing, part, controls the part viewing area or the AC signal M (upset of frame upset/row) of display part by being stored in the setting in the register 24.
Figure 18 is the interior block diagram of gated sweep circuit 13 shown in Figure 16.Among Figure 18, sweep signal SFT_ST input gating shift register GSRn (n=1～N, N is an integer) the gating shift register GSR1 of initial period, transmit successively by gated clock SFT_GCK1 and SFT_GCK2, export grid voltage to gate lines G n from each gating shift register GSRn with mutual upset relation.In addition, gated clock SFT_GCK1 and SFT_GCK2 are provided by signal voltage generation circuit.
Figure 19 is the interior block diagram of common scanning circuit 12 shown in Figure 16.Among Figure 19, sweep signal SFT_ST input common shift register CSRn (n=1～N, N is an integer) the common shift register CSR1 of original segment, transmit successively by common clock SFT_CCK1 and SFT_CCK2, export public shift pulse from each common shift register CSRn with mutual upset relation.In addition, common clock SFT_CCK1 and SFT_CCK2 are provided by signal voltage generation circuit.
Import public selector switch COM_SELn (n=1～N from the public shift pulse of common shift register CSRn, N is an integer), public selector switch COM_SELn and public shift pulse are synchronous, at AC signal M is under the situation of high level, select high level common electric voltage VCOMH to export to concentric line COMn, at AC signal M is under the low level situation, selects low level common electric voltage VCOML to export to concentric line COMn.
Figure 20 is the display image of display part, this figure (a) is the normal demonstration when display part has shown multi-grayscale, this figure (b) has been for having shown tartan, situation when non-display part has shown black box at part display part point (Dot), this figure (c) is for having shown white square, situation when non-display part has shown black box at the part display part.Though make display part show 4 * 8 points here, make the part display part show 4 * 4 points, non-display part shows 4 * 4 points, is not limited thereto.
Among Figure 20 (a), corresponding with the gate lines G n that selects, apply the signal voltage VSIGn of multi-grayscale in normal viewing area, common electric voltage is carried out the frame upset, carry out the demonstration different with each point with gray shade scale.Among Figure 20 (b), show tartan in the viewing area with the row upset, overturning with frame at non-display area shows black box.In Figure 20 (c), overturning with frame in the viewing area shows white square, and overturning with frame at non-display area shows black box.
Timing when Figure 21 is normal demonstration of carrying out shown in Figure 20 (a).Among Figure 21,, generate grid voltage VGn (n=1～8) with gated clock SFT_GCK1 and the SFT_GCK2 sweep signal SFT_ST in displacement 1 frame period of expression successively synchronously.In a frame period, show multi-grayscale signal voltage VSIGn (n=1～4) successively all the time with corresponding each row of each grid voltage VGn.
At this moment, corresponding with the level of AC signal M, synchronously select high level common electric voltage VCOMH or low level common electric voltage VCOML with common clock SFT_CCK1 and SFT_CCK2, generate common electric voltage VCOMn (n=1～8).
Among Figure 21, the frame upset of each frame period upset makes common electric voltage VCOMn become high level common electric voltage VCOMH and low level common electric voltage VCOML alternately.In an initial frame period, common electric voltage VCOMn is a high level, and in the next frame period, common electric voltage VCOMn is a low level.
Timing diagram when Figure 22 is the tartan display pattern that partly shows shown in Figure 20 (b).What Figure 22 was different with Figure 21 is to overturn at the every row of the part viewing area of preceding half part (4 * 4 point) AC signal M.Therefore, the every row upset of common electric voltage VCOM1～VCOM4.So, during this 4 line scanning, be low level, high level, low level, high level by making signal voltage VSIG1～VSIG4, can show the display pattern of tartan.In the next frame period, by upset AC signal M, signal voltage VSIG1～VSIG4 also overturns and is high level, low level, high level, low level.
That is, owing to every trade upset that common electric voltage is whenever advanced, therefore not needing to make line by line signal voltage is high level or low level, can make whole 4 behavior high level or low levels.This is because the frequencies go lower of signal voltage, and therefore with the driving power reduction of the signal voltage generation circuit of the low signal voltage drive signal line of this frequency, the consumed power of display device diminishes.
In addition, at half non-display area in back (4 * 4 black box shows), because common electric voltage VCOM5～VCOM8 is the frame upset of high level, therefore making signal voltage VSIG1～VSIG4 is that high level is deceived demonstration.In the next frame period, because common electric voltage VCOM5～VCOM8 is low level frame upset, therefore making signal voltage VSIG1～VSIG4 is that low level is deceived demonstration.
At this, as shown in figure 17, set AC signal M according to the control signal that is stored in the register 24 with control circuit 21, control circuit 21 reduces the frequency of signal voltage VSIG according to display pattern.
Timing diagram when Figure 23 shows white square display pattern shown in Figure 20 (c) for part.What Figure 23 was different with Figure 22 is, in the part viewing area is not to go upset, but carries out the frame upset.Therefore, in common electric voltage VCOMn was the initial frame period of high level, making signal voltage VSIGn in the part viewing area was low level, and making signal voltage VSIGn at the non-display area that shows black box is high level.In the next frame period, make these voltage upsets.
So, when part showed white square, as shown in figure 22, when going upset, signal voltage VSIGn also must overturn line by line, so the frequency height of signal voltage VSIGn, does not adopt the frame upset so do not adopt the row upset.
[embodiment 4]
Figure 24 is other block schemes of signal voltage generation circuit 11 shown in Figure 16, is provided with to exchange decision circuitry 91 in signal voltage generation circuit shown in Figure 17 11.Exchange the data (Data) of the amounts of 2 row that decision circuitry 91 relatively sends from storer 22 under the control of control circuit 21, whether go the judgement signal MSEL of upset common electric voltage to 25 outputs of AC signal generative circuit according to the reference value REF that sets in the register 24.AC signal generative circuit 25 is according to the AC signal M that judges 21 indications of signal MSEL reverse control circuit.
Figure 25 is the block scheme of interchange decision circuitry 91 shown in Figure 24.In Figure 24, the data storage of the lastrow that sends from storer 22 is to data storage circuitry 101, by the data comparison circuit 102 relatively data (DataR) of these lastrows and the data (Data) of current line.This data comparison circuit 102 is made of for example EOR circuit, when each data of lastrow are identical with each data of current line, each data output 0, each data does not export 1 simultaneously, relatively aggregate value and reference value REF of the output of each data of the amount of this delegation.When relatively result for the aggregate value of output during, in order to suppress the power that discharges and recharges of signal wire, to the capable upset of common electric voltage, when the aggregate value of exporting during less than reference value REF, not to the capable upset of common electric voltage more than or equal to reference value REF.
Figure 26 is the display image of the display part of the above-mentioned action of explanation, and making display part is that 4 * 8 points, part display part are that 4 * 4 points, non-part display part are 4 * 4 points, but is not limited thereto.
Figure 27 is for the quantity of as shown in figure 26 data that make horizontal direction is 4, to make reference value REF be 2, the output map of judgement signal MSEL when obtaining the aggregate value sum of each data output of amount of 1 row, when judging that signal MSEL is 0, not to the capable upset of common electric voltage, when MSEL is 1, to the capable upset of common electric voltage.
Figure 28 is for representing the timing diagram of the action that 91 pairs of display patterns shown in Figure 26 of interchange decision circuitry carry out.Among Figure 28, since the 2nd row, with each data of current line and each data addition without carry (Exor) of lastrow, accumulative total (Sum) this result, when this accumulative total (Sum) 2 when above, making judgement signal MSEL is high level, when adding up (Sum) when being not less than 2, making judges that signal MSEL is a low level.
That is, when each data of current line and each correlation of data of lastrow low (Sum is more than 2),, when correlativity height (Sum is less than 2),, proceed the frame upset not to the capable upset of common electric voltage to the capable upset of common electric voltage.Can reduce the frequency of signal voltage thus.
In addition, be subjected to owing to initial row therefore not adopt and judge signal MSEL about the interchange upset of display element (liquid crystal) self.That is, form with from the synchronizing signal in the input signal of outside synchronous exchange upset.This point with from the 5th the row non-display part exchange the upset in too.Therefore, as shown in figure 28, influence the 2nd row to the 4th row owing to judge signal MSEL, so both can be that high level also can be a low level in other the row.
Figure 29 is the timing diagram of the above-mentioned action of expression, and different with timing diagram before this is, uses and judges the signal MSEL AC signal M that overturns.Reduce the frequency of signal voltage VSIGn by capable upset of common electric voltage VCOM3 among Figure 29 to the 3rd row.
Claims (29)
1. the display device with the 1st display mode and the 2nd display mode is characterized in that,
In above-mentioned the 1st display mode, during 1 image duration whole in, display panel of every n line scanning, n is the integer more than 1,
In above-mentioned the 2nd display mode, during the part in above-mentioned 1 image duration, the once above-mentioned display panel of every m line scanning is during other in above-mentioned 1 image duration, reduce to flow to the electric current of the driving circuit that is used to drive above-mentioned display panel, m is for being big integer than n.
2. display device as claimed in claim 1 is characterized in that,
Above-mentioned driving circuit comprises the output circuit to above-mentioned display panel output gray level level signal,
Reduce the electric current that flows through in the above-mentioned output circuit, as the electric current that flows to above-mentioned driving circuit.
3. display device as claimed in claim 1 is characterized in that,
Above-mentioned driving circuit comprises the amplifier of buffering to the gray shade scale signal of above-mentioned display panel output,
Reduce the steady current of above-mentioned amplifier, as the electric current that flows to above-mentioned driving circuit.
4. display device as claimed in claim 3 is characterized in that,
Above-mentioned driving circuit comprises the translation circuit that video data is transformed into the gray shade scale signal,
The above-mentioned gray shade scale signal of above-mentioned amplifier buffer after by above-mentioned translation circuit conversion.
5. display device as claimed in claim 1 is characterized in that,
When setting the dirty electric current to above-mentioned driving circuit of above-mentioned the 1st display mode is that the electric current that flows to above-mentioned driving circuit under Inml, above-mentioned the 2nd display mode during the part in above-mentioned 1 image duration is the electric current that flows to above-mentioned driving circuit under Ips, above-mentioned the 2nd display mode during other in above-mentioned 1 image duration when being Islp, Inml＞Ips＞Islp.
6. display device as claimed in claim 1 is characterized in that,
Display gray scale number of degrees under above-mentioned the 2nd display mode is less than the display gray scale number of degrees under above-mentioned the 1st display mode.
7. display device as claimed in claim 6 is characterized in that,
Display gray scale number of degrees under above-mentioned the 1st display mode is whole gray shade scale numbers,
Display gray scale number of degrees under above-mentioned the 2nd display mode is 2 gray shade scales of each color of red, green, blue.
8. display device as claimed in claim 1 is characterized in that,
The viewing area of the above-mentioned display panel under above-mentioned the 2nd display mode is less than the viewing area of the above-mentioned display panel under above-mentioned the 1st display mode.
9. display device as claimed in claim 8 is characterized in that,
The viewing area of the above-mentioned display panel under above-mentioned the 1st display mode is whole viewing areas of above-mentioned display panel,
The viewing area of the above-mentioned display panel under above-mentioned the 2nd display mode is the part viewing area of above-mentioned display panel.
10. display device as claimed in claim 8 is characterized in that,
Under above-mentioned the 2nd display mode, every m line scanning is the part viewing area of above-mentioned display panel once,
Under above-mentioned the 2nd display mode, per 1 line scanning is other viewing areas of above-mentioned display panel once, and 1 is the integer bigger than m.
11. display device as claimed in claim 1 is characterized in that,
Said n is 1,
Above-mentioned m is 2,
During the part in above-mentioned 1 image duration the scan period of rewriting the gray shade scale signal of above-mentioned viewing area in above-mentioned 1 image duration,
It during in above-mentioned 1 image duration other scan period of rewriting above-mentioned viewing area gray shade scale signal in addition in above-mentioned 1 image duration.
12. a display device has the 1st display mode and the 2nd display mode, it is characterized in that,
In above-mentioned the 1st display mode, during 1 image duration whole in, display panel of every n line scanning, n is the integer more than 1,
In above-mentioned the 2nd display mode, during the part in above-mentioned 1 image duration, the once above-mentioned display panel of every m line scanning is during other in above-mentioned 1 image duration, be used in the driving circuit that drives above-mentioned display panel and be in and stop or dormancy dormancy state, m is for being big integer than n.
13. a display device is characterized in that, comprising:
Display panel possesses and is arranged in rectangular a plurality of pixels;
Signal generating circuit is to above-mentioned display panel output and the corresponding gray shade scale signal of video data; And
Sweep circuit, scanning will receive the pixel column of above-mentioned gray shade scale signal successively;
Whole pixels of the above-mentioned display panel of scanning stop the scanning of pixel during the part of above-mentioned sweep circuit in 1 image duration during other in above-mentioned 1 image duration,
Above-mentioned signal generating circuit comprises above-mentioned video data is transformed into the translation circuit of above-mentioned gray shade scale signal and buffering by the amplifier of the above-mentioned gray shade scale signal after the above-mentioned translation circuit conversion,
During in above-mentioned 1 image duration other, reduce the steady current of above-mentioned amplifier.
14. a display device is characterized in that possessing:
Many gate lines;
Many signal wires intersect with above-mentioned gate line;
A plurality of display elements have been applied in the signal voltage from above-mentioned signal wire;
Concentric line applies the common electric voltage that frame overturns to each display element of going;
The gated sweep circuit, the once above-mentioned gate line of each line scanning;
Signal voltage generation circuit drives above-mentioned signal wire; And
The common scanning circuit scans above-mentioned concentric line;
Above-mentioned signal voltage generation circuit generates the AC signal that makes the capable upset of above-mentioned common electric voltage according to the control signal from the outside, make the capable upset of the common electric voltage that is applied on the concentric line with above-mentioned common scanning circuit, and the low signal voltage of generated frequency composition comes drive signal line.
15. display device as claimed in claim 14 is characterized in that,
Above-mentioned signal voltage generation circuit possesses:
Register, storage is from the control signal of outside;
The AC signal generative circuit is according to the setting value generation AC signal of this register; And
Control circuit, the signal voltage that the generated frequency composition is low.
16. display device as claimed in claim 15 is characterized in that,
Above-mentioned control circuit basis generates signal voltage from the display mode of the input signal of outside.
17. display device as claimed in claim 14 is characterized in that,
Above-mentioned signal voltage generation circuit generates the AC signal make above-mentioned common electric voltage frame upset when common display, when part showed, the display mode according to from the input signal of outside generated the AC signal that makes capable upset of above-mentioned common electric voltage or frame upset.
18. display device as claimed in claim 14 is characterized in that,
Above-mentioned common scanning circuit possesses public selector switch, and this public selector switch is selected high level common electric voltage or low level common electric voltage according to AC signal.
19. display device as claimed in claim 14 is characterized in that,
Above-mentioned signal voltage generation circuit has:
Storer, storage is from the input signal of outside;
Exchange decision circuitry, compare each data and generation judgement signal from adjacent 2 row of above-mentioned storer, when their relevance was hanged down, described judgement signal made the capable upset of above-mentioned common electric voltage, when their relevance was high, described judgement signal made above-mentioned common electric voltage frame upset; And
The AC signal generative circuit generates AC signal according to above-mentioned judgement signal.
20. display device as claimed in claim 19 is characterized in that,
Above-mentioned interchange decision circuitry has:
Data storage circuitry, storage is from the data of the delegation of above-mentioned storer; And
Data comparison circuit will compare from each data of the lastrow of above-mentioned data storage circuitry and each data when previous row from above-mentioned storer;
According to the result of above-mentioned data comparison circuit with from the reference value of outside, generate and judge signal.
21. display device as claimed in claim 20 is characterized in that,
Above-mentioned data comparison circuit has the EOR circuit, and this EOR circuit carries out XOR with each data of lastrow and each data of current line.
22. display device as claimed in claim 19 is characterized in that:
When above-mentioned interchange decision circuitry shows in part, generate the judgement signal that makes the capable upset of above-mentioned common electric voltage according to reference value from the outside.
23. a display device is characterized in that possessing:
A plurality of display elements are arranged in rectangular;
Signal voltage generation circuit applies and the corresponding signal voltage of importing from the outside of picture signal above-mentioned display element;
Sweep circuit, scanning will apply the row of the above-mentioned display element of above-mentioned signal voltage; And
Common voltage generation circuit applies common electric voltage to above-mentioned display element on the contrary with above-mentioned signal voltage;
Under non-part display mode, to each above-mentioned picture signal frame, be that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element with above-mentioned common electric voltage,
Under the part display mode, display element for the viewing area, to each above-mentioned picture signal frame or row, with above-mentioned common electric voltage is that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element, display element for non-display area, is that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element to each above-mentioned picture signal frame with above-mentioned common electric voltage
For the display element of the above-mentioned viewing area under the above-mentioned part display mode, selecting according to the displaying contents of above-mentioned picture signal is that each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element, or each above-mentioned picture signal row switched the voltage that remains in the above-mentioned display element.
24. display device as claimed in claim 23 is characterized in that:
Above-mentioned common electric voltage comprises the common electric voltage and the low level common electric voltage of high level,
Above-mentioned common voltage generation circuit switches the positive pole and the negative pole that remain on the voltage in the above-mentioned display element by switching the common electric voltage and the low level common electric voltage of above-mentioned high level.
25. display device as claimed in claim 23 is characterized in that:
Display element for the above-mentioned viewing area under the above-mentioned part display mode, when the frequency content of the displaying contents of above-mentioned picture signal is high, each above-mentioned picture signal row is switched the voltage that remains in the above-mentioned display element, when the frequency content of the displaying contents of above-mentioned picture signal is low, each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element.
26. display device as claimed in claim 23 is characterized in that:
The gray shade scale number of the picture signal that will show in above-mentioned viewing area under the above-mentioned part display mode is less than the gray shade scale number of the above-mentioned picture signal under the above-mentioned non-part display mode.
27. a display device is characterized in that possessing:
A plurality of display elements are arranged in rectangular;
Signal voltage generation circuit applies and the corresponding signal voltage of importing from the outside of picture signal to above-mentioned display element;
Sweep circuit, scanning will apply the row of the above-mentioned display element of above-mentioned signal voltage; And
Common voltage generation circuit applies common electric voltage to above-mentioned display element on the contrary with above-mentioned signal voltage;
Under the many multi-grayscale display modes of the gray shade scale of above-mentioned picture signal, to each above-mentioned picture signal frame, be that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element with above-mentioned common electric voltage,
Under the few few gray shade scale display mode of the gray shade scale of above-mentioned picture signal, to each above-mentioned picture signal frame or row, be that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element with above-mentioned common electric voltage,
Under above-mentioned few gray shade scale display mode, according to the displaying contents of above-mentioned picture signal, selection is that each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element, or each above-mentioned picture signal row switched the voltage that remains in the above-mentioned display element.
28. display device as claimed in claim 27 is characterized in that:
Above-mentioned common electric voltage comprises the common electric voltage and the low level common electric voltage of high level,
Above-mentioned common voltage generation circuit switches the positive pole and the negative pole that remain on the voltage in the above-mentioned display element by switching the common electric voltage and the low level common electric voltage of above-mentioned high level.
29. display device as claimed in claim 27 is characterized in that:
Under above-mentioned few gray shade scale display mode, when the frequency content of the displaying contents of above-mentioned picture signal is high, each above-mentioned picture signal row is switched the voltage that remains in the above-mentioned display element, when the frequency content of the displaying contents of above-mentioned picture signal is low, each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007011740A JP5081456B2 (en) | 2007-01-22 | 2007-01-22 | Display device |
| JP011740/2007 | 2007-01-22 | ||
| JP010952/2007 | 2007-01-22 | ||
| JP2007010952A JP5395328B2 (en) | 2007-01-22 | 2007-01-22 | Display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101135811A Division CN101872585B (en) | 2007-01-22 | 2008-01-21 | Display device |
Publications (2)
| Publication Number | Publication Date |
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| CN101231808A true CN101231808A (en) | 2008-07-30 |
| CN101231808B CN101231808B (en) | 2011-05-04 |
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ID=39703220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100036972A Active CN101231808B (en) | 2007-01-22 | 2008-01-21 | Display device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5395328B2 (en) |
| CN (1) | CN101231808B (en) |
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Also Published As
| Publication number | Publication date |
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| JP2008176159A (en) | 2008-07-31 |
| CN101231808B (en) | 2011-05-04 |
| JP5395328B2 (en) | 2014-01-22 |
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