CN101211895B - Structure for supervising memory array unit interval and the method - Google Patents
Structure for supervising memory array unit interval and the method Download PDFInfo
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- CN101211895B CN101211895B CN2007101728073A CN200710172807A CN101211895B CN 101211895 B CN101211895 B CN 101211895B CN 2007101728073 A CN2007101728073 A CN 2007101728073A CN 200710172807 A CN200710172807 A CN 200710172807A CN 101211895 B CN101211895 B CN 101211895B
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- random access
- static random
- access memory
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- field oxygen
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- 230000015654 memory Effects 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 17
- 230000003068 static effect Effects 0.000 claims abstract description 28
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 26
- 239000001301 oxygen Substances 0.000 claims abstract description 26
- 238000012544 monitoring process Methods 0.000 claims abstract description 14
- 230000003071 parasitic effect Effects 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 230000024241 parasitism Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 5
- 230000005055 memory storage Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 1
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a structure for monitoring element spacing of a memory array and a method thereof, which is used for monitoring whether or not the spacing value between arbitrary two adjacent static random access memory (SRAM) in the memory array of the SRAM meets requirements. Wherein, a first terminal and a second terminal is the respectively connected and formed by the adjacent SRAM; a third terminal is connected and formed by a polysilicon across the adjacent SRAM; a fourth terminal is connected and formed by a P type well region; a parasitic field oxygen transistor is formed by the four terminals. First, a normal working condition of the SRAM is provided; then, the parameter of the parasitic field oxygen transistor is measured; lastly, the spacing value waited for monitoring is determined whether meets requirements or not according to the parameter of the parasitic field oxygen transistor. By the structure for monitoring element spacing of a memory array and a method thereof of the invention, whether the element spacing of the memory array of the SRAM meets requirements can be monitored effectively. The invention also has the advantage of simple and easy to be realized.
Description
Technical field
The present invention relates to the supervising memory array method for quality, specifically, relate to a kind of structure and method of unit interval of supervising memory array.
Background technology
Static random access memory (Static Random Access Memory, SRAM) storage array is used very extensive in modern VLSI (very large scale integrated circuit) chip, whether the good job of storage array quality has decisive influence to integrated circuit (IC) chip, therefore must design a lot of test structures and come supervising memory array to have problems.
The storage array spacing is a very important parameter index in the parameters of SRAM storage array, the storage array spacing is more for a short time to mean that memory capacity can be big more under equal area, so it is considerable determining a rational distance values, design a kind of method of unit interval of the SRAM of monitoring storage array and structure also becomes of industry and studies focus.
Summary of the invention
Main purpose of the present invention provides a kind of structure and method of unit interval of supervising memory array, and whether its unit monitors that can monitor the SRAM storage array effectively meets the requirements.
For achieving the above object, the invention provides a kind of structure of unit interval of supervising memory array, whether the distance values that is used for monitoring between any two the adjacent static random access memorys of static random access memory storage array meets the requirements, described adjacent static random access memory connects the formation first and second terminal respectively, connect formation the 3rd terminal across the polysilicon of crossing described adjacent static random access memory, P type well region connects formation the 4th terminal, form the field oxygen transistor of a parasitism by described first to fourth terminal, wherein, the transistorized channel length of field oxygen of described parasitism is a distance values to be monitored, described adjacent static random access memory, across the polysilicon of crossing described adjacent static random access memory, and P type well region is all connected by metal wire by contact hole.
The present invention also provides a kind of method of unit interval of supervising memory array, whether the distance values that is used for monitoring between any two the adjacent static random access memorys of static random access memory storage array meets the requirements, wherein, described adjacent static random access memory connects the formation first and second terminal respectively, connect formation the 3rd terminal across the polysilicon of crossing described adjacent static random access memory, P type well region connects formation the 4th terminal, form the field oxygen transistor of a parasitism by described first to fourth terminal, described method at first provides described static random access memory normality condition of work, then measure the transistorized parameter of field oxygen of described parasitism, judge according to the transistorized parameter of field oxygen of described parasitism whether distance values to be monitored meets the requirements at last, wherein, the measured transistorized parameter of described parasitic fields oxygen comprises leakage current at least, threshold voltage and punchthrough current.
The structure of the unit interval of supervising memory array of the present invention forms parasitic field oxygen transistor by leading-out terminal, by measuring the parasitic transistorized parameter of field oxygen, thereby judging whether distance values to be measured meets the requirements, is a kind of simply and effectively design.
Description of drawings
To the description of a preferred embodiment of the present invention, can further understand purpose, specific structural features and the advantage of its invention by following in conjunction with its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1 is the schematic diagram of a preferred embodiment of structure of the unit interval of supervising memory array of the present invention.
Embodiment
Following basis specifies a better embodiment of the present invention in conjunction with the accompanying drawings.
Fig. 1 is the schematic diagram of a preferred embodiment of structure of the unit interval of supervising memory array of the present invention.As shown in the figure, whether the structure 1 of the unit interval of the supervising memory array of the present invention distance values d that is used for monitoring between any two sram cells 10 of static random access memory (SRAM) storage array meets the requirements.Need to prove, structure for the unit interval that clearly illustrates supervising memory array of the present invention, two adjacent sram cells 10 only draw in Fig. 1, but those skilled in the art should know monitoring structure of the present invention can be used for the storage array formed more than two sram cells, only need between adjacent arbitrarily sram cell, set up monitoring structure of the present invention or use method for supervising of the present invention to get final product.
Described adjacent S ram cell 10 even goes out to constitute first and second terminal by contact hole 20 by metal wire 30 respectively, even go out constitute three terminal by contact hole 20 by metal wire 30 across the polysilicon 40 of crossing described adjacent S ram cell 10, P type well region connects formation the 4th terminal, form the field oxygen transistor of a parasitism by described first to fourth terminal, wherein, the channel length d of the field oxygen transistor T of described parasitism is distance values to be monitored.
When actual design is tested, at first, provide SRAM normality condition of work.Therefore in more detail,,, should provide corresponding condition during the unit interval value in monitoring SRAM storage array when operate as normal Yi Bian be in electronegative potential Yi Bian the adjacent S ram cell must be to be in high potential, with guarantee monitoring accurately.
Then, measure the transistorized parameter of field oxygen of described parasitism.In more detail, these parameters comprise leakage current, threshold voltage and punchthrough current etc. at least.
At last, judge according to the transistorized parameter of field oxygen of described parasitism whether distance values to be monitored meets the requirements.In more detail, can be by going out the parasitic transistorized channel length d of field oxygen such as calculation of parameter such as leakage current, threshold voltage and punchthrough current, distance values promptly to be monitored, and then judge whether this distance values d meets the requirements.
In sum, the invention provides a kind of structure and method of unit interval of supervising memory array, it is by measuring the parasitic transistorized parameter of field oxygen, thereby judges whether distance values to be measured meets the requirements, and is a kind of simple and effective design.
Of particular note, the structure of the unit interval of supervising memory array of the present invention and method are not limited to step execution sequence defined in the foregoing description, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement the present invention, and not breaking away from the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (7)
1. the structure of the unit interval of a supervising memory array, whether the distance values that is used for monitoring between any two the adjacent static random access memorys of static random access memory storage array meets the requirements, it is characterized in that, described adjacent static random access memory connects the formation first and second terminal respectively, connect formation the 3rd terminal across the polysilicon of crossing described adjacent static random access memory, P type well region connects formation the 4th terminal, form the field oxygen transistor of a parasitism by described first to fourth terminal, wherein, the transistorized channel length of field oxygen of described parasitism is a distance values to be monitored.
2. the structure of the unit interval of supervising memory array according to claim 1, it is characterized in that, described adjacent static random access memory, all connect by metal wire by contact hole across the polysilicon of crossing described adjacent static random access memory and P type well region.
3. the structure of the unit interval of supervising memory array according to claim 1, it is characterized in that, by measuring the transistorized parameter of field oxygen of described parasitism, calculate the parasitic transistorized distance values to be monitored of field oxygen, and then judge whether distance values to be monitored meets the requirements.
4. the structure of the unit interval of supervising memory array according to claim 3 is characterized in that, the transistorized parameter of field oxygen of measured described parasitism comprises leakage current, threshold voltage and punchthrough current at least.
5. the method for the unit interval of a supervising memory array, whether the distance values that is used for monitoring between any two the adjacent static random access memorys of static random access memory storage array meets the requirements, wherein, described adjacent static random access memory connects the formation first and second terminal respectively, connect formation the 3rd terminal across the polysilicon of crossing described adjacent static random access memory, P type well region connects formation the 4th terminal, form the field oxygen transistor of a parasitism by described first to fourth terminal, described method at first provides described static random access memory normality condition of work, then measure the transistorized parameter of field oxygen of described parasitism, and calculate the parasitic transistorized distance values to be monitored of field oxygen, and then judge whether distance values to be monitored meets the requirements.
6. the method for the unit interval of supervising memory array according to claim 5, it is characterized in that, described adjacent static random access memory, all connect by metal wire by contact hole across the polysilicon of crossing described adjacent static random access memory and P type well region.
7. the method for the unit interval of supervising memory array according to claim 5 is characterized in that, the transistorized parameter of field oxygen of measured described parasitism comprises leakage current, threshold voltage and punchthrough current at least.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101728073A CN101211895B (en) | 2007-12-21 | 2007-12-21 | Structure for supervising memory array unit interval and the method |
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| CN2007101728073A CN101211895B (en) | 2007-12-21 | 2007-12-21 | Structure for supervising memory array unit interval and the method |
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| CN101211895A CN101211895A (en) | 2008-07-02 |
| CN101211895B true CN101211895B (en) | 2011-09-21 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1366342A (en) * | 2001-01-16 | 2002-08-28 | 三菱电机株式会社 | Semiconductor memory |
| US6703641B2 (en) * | 2001-11-16 | 2004-03-09 | International Business Machines Corporation | Structure for detecting charging effects in device processing |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1366342A (en) * | 2001-01-16 | 2002-08-28 | 三菱电机株式会社 | Semiconductor memory |
| US6703641B2 (en) * | 2001-11-16 | 2004-03-09 | International Business Machines Corporation | Structure for detecting charging effects in device processing |
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Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20121128 Owner name: SHANGHAI MUNICIPAL ELECTRIC POWER COMPANY SHANGHAI Effective date: 20121128 |
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Inventor after: Kang Xiaoyan Inventor after: Zhang Jin Inventor after: Shen Jianzhong Inventor after: Shen Yiye Inventor after: Dong Weiyi Inventor after: Hu Jian Inventor after: Li Po Inventor before: Hu Jian Inventor before: Li Po |
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Free format text: CORRECT: ADDRESS; FROM: 201203 PUDONG NEW AREA, SHANGHAI TO: 100031 XICHENG, BEIJING Free format text: CORRECT: INVENTOR; FROM: HU JIAN LI PO TO: KANG XIAOYAN ZHANG JIN SHEN JIANZHONG SHEN YIYE DONG WEIYI HU JIAN LI PO |
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Effective date of registration: 20121128 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: Shanghai Electric Power Corporation Patentee after: Shanghai Xin Xin Information Technology Co., Ltd. Address before: 201203 Shanghai Zhangjiang hi tech park GuoShouJing Road No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |