CN101211765B - Shallow impurity drain domain logical operation method capable of diminishing ion implantation shadow effect - Google Patents
Shallow impurity drain domain logical operation method capable of diminishing ion implantation shadow effect Download PDFInfo
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- CN101211765B CN101211765B CN2007101727329A CN200710172732A CN101211765B CN 101211765 B CN101211765 B CN 101211765B CN 2007101727329 A CN2007101727329 A CN 2007101727329A CN 200710172732 A CN200710172732 A CN 200710172732A CN 101211765 B CN101211765 B CN 101211765B
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Abstract
The invention relates to a logic operation method for shallowly doped drain layout for reducing the shadow effect in ionic implantation, which comprises the steps as follows: the channel region of the metal oxide semiconductor transistor for which a grid is overlapped with an active region is determined and then each edge of the region is expanded by a; the ionic implantation is carried out in the region eventually determined so as to generate a doped drain. The logic operation method for shallowly doped drain layout for reducing the shadow effect in dip ionic implantation provided by the invention deflates the layout area, ensures the process quality and simultaneously enhances the integration while reducing the shadow effect.
Description
Technical field
The present invention relates to a kind of shallow impurity drain domain logical operation method that reduces inclination angle ion implantation shadow effect of semiconductor manufacturing.
Background technology
LDD (the shallow doped-drain of lightly doped drain) produces by the domain logical operation.Carrying out LDD and Halo (halo) (claiming Pocket again) twice ion implants, it is also non-perpendicular when partial L DD and most Halo ion are implanted, but the inclination certain angle, this just might close on the photoresistance influence of masking layer on the subject wafer, thereby produces shadow effect (as Fig. 1).In general, the LDD that the domain logical operation produces is along the border (as Fig. 2) of heavy implanted layer (Plus implant layer), this makes needs strict more heavy implanted layer layout design rules in some special domains, as introducing the restriction of m1 and m2 minimum dimension among Fig. 3, be used to draw back and close on the masking layer photoresistance to the distance of device channel, reduce the inclination angle ion and implant shadow effect (for example in some 0.15 micron logic processing procedure, the minimum dimension of regulation m1 and m2 is 0.4 micron).And in processing procedure, also need photoresistance (PR) thickness of attenuate LDD as far as possible, the precision of control CD (the key size of critical dimension) and alignment overlay (stack is aimed at).
Summary of the invention
A kind of shallow impurity drain domain logical operation method that the inclination angle ion is implanted shadow effect that reduces provided by the invention when having reduced shadow effect, has tightened chip area, has guaranteed processing quality, has improved integrated level simultaneously.
In order to achieve the above object, the invention provides a kind of shallow impurity drain domain logical operation method that ion is implanted shadow effect that reduces, comprise following steps:
Step 1, determine the channel region of metal-oxide semiconductor (MOS) (MOS) pipe of grid and active area (ACT) crossover;
Step 2, regional every limit that step 1 the is determined big a that rises, wherein a can adjust according to concrete processing procedure ability;
Step 3, in the zone that step 2 is determined, carry out ion and implant, generate LDD.
Utilize domain logical operation provided by the invention, m1 and m2 minimum dimension no longer directly are subjected to the restriction of processing procedure ability during layout design, and the unique and parameter processing procedure direct correlation becomes a, and this can tighten chip area.M1 and m2 are less than a generally speaking, this means by the N type or the P type LDD layer (NLDD/PLDD layer) of domain logical operation generation provided by the invention and understand the adjacent P+/N+ heavily doped region (Plus) of some covering, because LDD still is that the degree of depth all can not show a candle to heavily doped region (Plus) from concentration in general logic processing procedure, so can not produce any influence to heavily doped region.And the injection of LDD/Halo ion has only the part of next-door neighbour's metal-oxide-semiconductor raceway groove just can the metal-oxide-semiconductor characteristic to be exerted an influence, so than the logical operation of traditional LDD domain, the ion implantation region territory that this logical operation reduces can not produce any effect to the metal-oxide-semiconductor characteristic.
Description of drawings
Fig. 1 is the schematic diagram that the inclination angle ion is implanted shadow effect in the background technology;
Fig. 2 is the zone boundary schematic diagram of the LDD that traditional domain logical operation produces in the background technology;
Fig. 3 is a layout design rules relevant with shadow effect in the background technology;
Fig. 4 is a kind of area schematic that the inclination angle ion is implanted the LDD that the shallow impurity drain domain logical operation method of shadow effect produces that reduces provided by the invention.
Embodiment
Followingly specify better embodiment of the present invention according to Fig. 4:
As shown in Figure 4, the invention provides a kind of shallow impurity drain domain logical operation method that the inclination angle ion is implanted shadow effect that reduces, comprise following steps:
Step 1, determine the channel region of metal-oxide semiconductor (MOS) (MOS) pipe of grid and the district's crossover of having chance with;
Step 2, regional every limit that step 1 the is determined big a that rises, in some 0.15 micron logic processing procedure, the scope that can select a value is 0.3-0.5um;
Step 3, in the zone that step 2 is determined, carry out ion and implant, generate LDD.
Utilize logic processing procedure provided by the invention, m1 and m2 minimum dimension no longer directly are subjected to the restriction of processing procedure ability during layout design, tighten chip area thereby can suitably lower the requirement.Unique and the parameter processing procedure direct correlation becomes a, and (as in 0.15 micron system, be subjected to the processing procedure capabilities limits, m1 and m2 minimum dimension are 0.4 micron.But after having used this novel domain logical operation, m1 and m2 can drop to 0.25 micron, only needing that a is set at 0.4 micron gets final product) m1 and m2 be less than a generally speaking, this means by the N type or the P type LDD layer (NLDD/PLDD layer) of domain logical operation generation provided by the invention and understand the adjacent P+/N+ heavily doped region (Plus) of some covering, because LDD still is that the degree of depth all can not show a candle to heavily doped region (Plus) from concentration in general logic processing procedure, so can not produce any influence to heavily doped region.And the injection of LDD/Halo ion has only the part of next-door neighbour's metal-oxide-semiconductor raceway groove just can the metal-oxide-semiconductor characteristic to be exerted an influence, so than the logical operation of traditional LDD domain, the ion implantation region territory that this logical operation reduces can not produce any effect to the metal-oxide-semiconductor characteristic.
Claims (1)
1. one kind can be reduced the shallow impurity drain domain logical operation method that ion is implanted shadow effect, it is characterized in that, comprises following steps:
Step 1, determine the channel region of the MOS (metal-oxide-semiconductor) transistor of grid and active area crossover;
Step 2, regional every limit that step 1 the is determined big a that rises, the span of described a is 0.3-0.5um;
Step 3, in the zone that step 2 is determined, carry out ion and implant, generate shallow doped-drain.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101727329A CN101211765B (en) | 2007-12-21 | 2007-12-21 | Shallow impurity drain domain logical operation method capable of diminishing ion implantation shadow effect |
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| CN2007101727329A CN101211765B (en) | 2007-12-21 | 2007-12-21 | Shallow impurity drain domain logical operation method capable of diminishing ion implantation shadow effect |
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| CN101211765A CN101211765A (en) | 2008-07-02 |
| CN101211765B true CN101211765B (en) | 2011-09-21 |
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| CN2007101727329A Active CN101211765B (en) | 2007-12-21 | 2007-12-21 | Shallow impurity drain domain logical operation method capable of diminishing ion implantation shadow effect |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103178094B (en) * | 2011-12-22 | 2015-08-19 | 无锡华润上华科技有限公司 | Comprise the domain structure of ldd structure |
| CN112928159B (en) * | 2021-01-22 | 2023-11-24 | 上海华虹宏力半导体制造有限公司 | Method for trimming MOSFET device layout |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492693B2 (en) * | 1998-08-12 | 2002-12-10 | Micron Technology, Inc. | Low voltage high performance semiconductor devices and methods |
| CN1979781A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for relieving MOS transistor reversed narrow-path effect |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492693B2 (en) * | 1998-08-12 | 2002-12-10 | Micron Technology, Inc. | Low voltage high performance semiconductor devices and methods |
| CN1979781A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for relieving MOS transistor reversed narrow-path effect |
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| CN101211765A (en) | 2008-07-02 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140424 |
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Effective date of registration: 20140424 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |