CN1979781A

CN1979781A - Method for relieving MOS transistor reversed narrow-path effect

Info

Publication number: CN1979781A
Application number: CN 200510111282
Authority: CN
Inventors: 伍宏; 陈晓波
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2005-12-08
Filing date: 2005-12-08
Publication date: 2007-06-13

Abstract

The invention makes public a kind of method of relieving the reversed narrow-channel effect of MOS transistor, on the routine technology basis to modify the source leakage ion injection mask level layout so as to avoid the source leakage intermingled ion from injecting into the MOS transistor that closes to the edge position of silicon area of shallow channel separation area: first of all the width (a) of the juncture between the area from the source leakage intermingled ion injection area's edge to the silicon area of MOS transistor and the shallow channel separation area must be defined, and then correct the relevant mask level layout, finally make mask level layout and perform tape-out. The invention can improve the threshold voltage (Vt) of MOS transistor.

Description

A kind of method of relieving MOS transistor reversed narrow-path effect

Technical field

The present invention relates to a kind of semiconductor fabrication process, particularly a kind of method of relieving MOS transistor reversed narrow-path effect.

Background technology

In present conventional metal-oxide-semiconductor field effect transistor layout design, it is to cover whole M OS transistor area that ion implanted region is leaked in general source, and the used silicon area of MOS transistor is contained by source leakage ion implanted region, shown in Fig. 1 (A).But might cause comparatively serious reversed narrow-path effect in the metal-oxide-semiconductor field effect transistor of utilization shallow trench isolation technology (STI, ShallowTrench Isolation), this transistorized threshold voltage (Vt) can descend.This mainly is because reversed narrow-path effect is equivalent in " main transistor " both sides near local in parallel added two threshold voltages (Vt) relatively low " parasitic transistor " of silicon area with the shallow trench isolation region intersection.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method of relieving MOS transistor reversed narrow-path effect, improves the problem that threshold voltage (Vt) that the reversed narrow-path effect of MOS transistor causes descends.

For solving the problems of the technologies described above, the method of a kind of relieving MOS transistor reversed narrow-path effect of the present invention, the modification source is leaked ion injection photolithography plate domain and is injected the silicon area marginal portion of MOS transistor near shallow trench isolation regions to avoid the source to leak dopant ion on the common process basis: at first determine the width (a) of leakage edge, dopant ion injection region, source to the intersection of MOS transistor silicon area and shallow trench isolation region, revise corresponding photolithography plate domain then, make photolithography plate at last and carry out flow.

The present invention is owing to ion injection photolithography plate domain is leaked in modification source on the common process basis, make MOS transistor not be included in the leakage ion implanted region territory, source near the silicon area marginal portion of shallow trench isolation regions, thereby make this zone not be injected into the source and leak the dopant ion that ion injects, improve the threshold voltage (Vt) of " parasitic transistor ", also just improved the threshold voltage (Vt) of total MOS transistor.

Description of drawings

Fig. 1 is that metal-oxide-semiconductor field effect transistor domain schematic diagram compares under the inventive method and the common process, and wherein Figure 1A is a common process, and Figure 1B is the inventive method.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and the specific embodiments.

Principle of the present invention is: the modification source is leaked ion and is injected the photolithography plate domain on the common process basis, make MOS transistor not be included in the leakage ion implanted region territory, source, leak the dopant ion that ion injects thereby make this zone not be injected into the source near the silicon area marginal portion of shallow trench isolation regions; So, carrier depletion (poly depletion) can increase in the polysilicon gate of MOS transistor fringe region, and being equivalent to this regional gate oxide thickness increases, and this helps improving the i.e. threshold voltage (Vt) of " parasitic transistor " in this zone.In addition, because near the doping content of polysilicon gate part MOS transistor silicon area and shallow trench isolation region intersection and outside silicon area significantly lowers, this part polysilicon gate by fringing field (fringing field) to the MOS transistor fringe region to influence meeting weakened, this also helps the raising of " parasitic transistor " threshold voltage (Vt).Because the threshold voltage (Vt) of " parasitic transistor " is at reversed narrow-path effect the made decision threshold voltage (Vt) of total MOS transistor of serious situation comparatively, improve the threshold voltage (Vt) of " parasitic transistor ", also just improved the threshold voltage (Vt) of total MOS transistor.

As shown in Figure 1, be that metal-oxide-semiconductor field effect transistor domain schematic diagram compares under the inventive method and the common process, wherein Figure 1A is a common process, Figure 1B is the inventive method.As Figure 1B, promptly be that ion injection photolithography plate domain is leaked in the modification source on the common process basis in the specific embodiment of the invention, make MOS transistor not be included in the leakage ion implanted region territory, source near the silicon area marginal portion of shallow trench isolation regions, wherein geometric parameter " a " does not leak the width of the MOS transistor silicon area of ion injection for not carrying out the source, and promptly the distance of ion implanted region edge to the intersection of MOS transistor silicon area and shallow trench isolation region leaked in the source.Parameter in practical operation " a " need be optimized and determine according to the order of severity of transistor reversed narrow-path effect, transistorized all ion implanting conditions, transistorized comprehensive device property (comprise source leakage-substrate PN junction electric leakage with breakdown characteristics etc.) and relevant layout design rules.To pay special attention to make electric leakage of source leakage-substrate PN junction and the obvious variation of breakdown characteristics in the MOS transistor in the optimizing process.If desired, can suitably finely tune the ion implanting conditions relevant and improve this PN junction characteristic with MOS transistor source leakage-substrate PN junction characteristic.After parameter " a " and ion injection fine setting decision, modification source leakage ion injection photolithography plate domain carries out the photolithography plate making again and flow gets final product.

Need to prove that specific embodiment shows that the inventive method undopes when mainly being applicable to the polysilicon gate deposit and exists light doped source and drain ion to inject (LDD implant) but do not have the halo ion to inject the situation of (Halo implant).

In sum, the inventive method is leaked ion by the modification source and is injected the photolithography plate domain to avoid the silicon area marginal portion of source leakage dopant ion injection MOS transistor near shallow trench isolation regions on the common process basis, solve threshold voltage (Vt) the decline problem that the reversed narrow-path effect of MOS transistor causes, thereby improved the reversed narrow-path effect of MOS transistor.

Claims

1, a kind of method of relieving MOS transistor reversed narrow-path effect, it is characterized in that, the modification source is leaked ion injection photolithography plate domain and is injected the silicon area marginal portion of MOS transistor near shallow trench isolation regions to avoid the source to leak dopant ion: at first determine the width (a) of leakage edge, dopant ion injection region, source to the intersection of MOS transistor silicon area and shallow trench isolation region, revise corresponding photolithography plate domain then, make photolithography plate at last and carry out flow.

2, the method for relieving MOS transistor reversed narrow-path effect according to claim 1, it is characterized in that leakage edge, dopant ion injection region, described definite source refers to that to the width (a) of the intersection of MOS transistor silicon area and shallow trench isolation region the order of severity according to transistor reversed narrow-path effect, transistorized ion implanting conditions, transistorized comprehensive device property and layout design rules are definite.

3, the method for relieving MOS transistor reversed narrow-path effect according to claim 2 is characterized in that, described transistorized comprehensive device property comprises source leakage-substrate PN junction electric leakage and breakdown characteristics.

4, according to the method for claim 1,2 or 3 described relieving MOS transistor reversed narrow-path effects, it is characterized in that, undope when can be used for the polysilicon gate deposit and exist light doped source and drain ion to inject but the technology that do not have the halo ion to inject.