CN101211654A

CN101211654A - Output signal driver circuit and method for driving output signal

Info

Publication number: CN101211654A
Application number: CNA2006101717962A
Authority: CN
Inventors: 陈逸琳
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2006-12-29
Filing date: 2006-12-29
Publication date: 2008-07-02

Abstract

The invention provides an output signal driving circuit, which comprises a first switch, a second switch, a third switch and a fourth switch. The first switch is used for selectively connecting a first power source voltage and a first endpoint according to a first control signal. The second switch is used for selectively connecting a second power source voltage and a second endpoint according to a second control signal. The third switch is used for selectively connecting the first endpoint and an output end of the output signal driving circuit according to a third reference voltage. The fourth switch is used for selectively connecting the output end and the second endpoint according to a fourth reference voltage. The voltage levels of the third and the fourth reference voltages is arranged between the voltage level of the first power source voltage and the voltage level of the second power source voltage.

Description

The method of output signal driver circuit and drive output signal

Technical field

The invention provides a kind of circuit and correlation technique thereof of output signal, especially refer to a kind of output signal driver circuit and method thereof that is applied to storer (for example DDR storer) access.

Background technology

Along with processor performance is constantly soaring, bandwidth of memory has become a present big bottleneck that influences the usefulness of computer system, so each big semiconductor factory and chip factory all constantly develop the solution that new storer specification and bussing technique are used as bandwidth of memory, present double data transfer rate (Doubledata rate, DDR) storer Development Technology is no exception, from initial DDRI, DDRII is to up-to-date DDRIII memory transfer specification, yet, when significantly promoting the memory data access amount, (application specific integrated circuit, ASIC) manufacturing plant but can't provide state-of-the-art technical matters to use for the client to general special IC immediately.According to the ordered DDR specification of world semiconductor ANSI (JDEC), the DDRI storer must be followed the SSTL-25 specification, i.e. the voltage of the I/O of its storer (IO) port must be 2.5V; The DDRII storer must be followed the SSTL-18 specification, and promptly the voltage of the input/output end port of its storer must be 1.8V; The DDRIII storer then must be followed the SSTL-15 specification, the voltage that is the input/output end port of its storer must be 1.5V, but general asic chip manufacturing plant only provides two kinds of process components (that is low voltage component and high voltage device) to use for the client, therefore, when the I/O tie point (IO pad) of design memory controller (memory controller), generally be to operate on the high voltage transistor element operation (DDRI) under 2.5V voltage of 3.3V originally, or will operate on the high voltage transistor element operation (DDRII) under 1.8V of 3.3V originally.Please refer to Fig. 1, Fig. 1 is transistorized electric current one voltage characteristic curve of 3.3V.Can learn according to Fig. 1, when the transistor of 3.3V operates in the 1.8V of DDRII institute standard, its operating current I ₂Operating current I in the time of all can operating in normal 3.3V than script ₁Little, yet the I/O tie point is in order to charge to rational voltage level in the time of DDRII defined, then the drive current under 1.8V may be big inadequately, therefore in this case, then must to increase the area of transistorized width size (width) and I/O tie point in order to improve amount of drive current, so will increase circuit area and cause cost to increase.Similarly, when the transistor of 3.3V operates in the 1.5V of DDRIII institute standard, its operating current I ₃Operating current I in the time of can operating in normal 3.3V than script ₃Little, and can be than littler under the above-mentioned situation that is applied to DDRII, therefore required circuit area will be bigger.

Summary of the invention

Therefore, one of fundamental purpose of the present invention is to provide a kind of output signal driver circuit and method thereof that is applied to storer (for example DDR storer) access, and it can save I/O tie point area to solve the problem of known technology.

According to one embodiment of the invention, it discloses a kind of output signal driver circuit.This output signal driver circuit includes: one first switch, a second switch, one the 3rd switch, and one the 4th switch.One end of this first switch is coupled to one first supply voltage, and its other end is coupled to one first end points, wherein this first switch conduction whether according to one first control signal with optionally with this first supply voltage and this first end points conducting.One end of this second switch is coupled to a second source voltage, and its other end is coupled to one second end points, wherein this second switch conducting whether according to one second control signal with optionally with this second source voltage and this second end points conducting.One end of the 3rd switch is coupled to this first end points, and its other end is coupled to an output terminal, wherein the 3rd switch conduction whether according to one the 3rd reference voltage with optionally with this first end points and this output terminal conducting.One end of the 4th switch is coupled to this output terminal, and its other end is coupled to this second end points, wherein the 4th switch conduction whether according to one the 4th reference voltage with optionally with this output terminal and this second end points conducting; Wherein the voltage level of the 3rd reference voltage and the 4th reference voltage is between the voltage level of the voltage level of this first supply voltage and this second source voltage.

According to one embodiment of the invention, it discloses a kind of driving method of output signal.This driving method includes: according to one first control signal with optionally with one first supply voltage and one first end points conducting; According to one second control signal with optionally with second source voltage and one second end points conducting; According to one the 3rd reference voltage with optionally with this first end points and an output terminal conducting; And according to one the 4th reference voltage with optionally with this output terminal and this second end points conducting; Wherein the voltage level of the 3rd, the 4th reference voltage is between the voltage level of the voltage level of this first supply voltage and this second source voltage.

Description of drawings

Fig. 1 is the transistorized current-voltage characteristic curve figure of known 3.3V.

Fig. 2 is the synoptic diagram according to an embodiment of output signal driver circuit of the present invention.

Fig. 3 is the current-voltage characteristic curve figure of the p type field effect transistor shown in second figure.

Fig. 4 is the current-voltage characteristic curve figure of the n type field effect transistor shown in second figure.

Fig. 5 is the process flow diagram of the driving method of output signal of the present invention.

The main element symbol description

200	Output signal driver circuit
200	Output signal driver circuit	202、204、206、208	Switch
210、212	Buffer circuit	202、204、206、208	Switch
210、212	Buffer circuit	220	The I/O tie point
302、304、402、404	Curve	220	The I/O tie point

Embodiment

Please refer to Fig. 2, Fig. 2 is the synoptic diagram according to an embodiment of output signal driver circuit 200 of the present invention.Output signal driver circuit 200 includes one first switch 202, a second switch 204, one the 3rd switch 206, one the 4th switch 208, one first predrive circuit 210 and one second predrive circuit 212.In the present embodiment, first switch, 202 one ends are coupled to one first supply voltage V _Dd, its other end is coupled to one first end points N ₁, whether these first switch, 202 conductings are according to one first control signal V _C1With optionally with the first supply voltage V _DdWith the first end points N ₁Conducting; Second switch 204 one ends are coupled to a second source voltage V _Gnd, its other end is coupled to one second end points N ₂, whether these second switch 204 conductings are according to one second control signal V _C2With optionally with second source voltage V _GndWith the second end points N ₂Conducting; The 3rd switch 206 one ends are coupled to the first end points N ₁, its other end is coupled to an output terminal N of output signal driver circuit 200 _Out, whether 206 conductings of the 3rd switch are according to one the 3rd reference voltage V _Ref3With optionally with the first end points N1 and output terminal N _OutConducting; The 4th switch 208 one ends are coupled to the second end points N ₂, its other end is coupled to an output terminal N of output signal driver circuit 200 _Out, whether 208 conductings of the 4th switch are according to one the 4th reference voltage V _Ref4With optionally with the second end points N2 and output terminal N _OutConducting; First predrive circuit 210 is coupled to first switch 202, receives and the foundation first input signal V ₁With from the first supply voltage V _DdExamine voltage V with a Wucan _Ref5In choose one as the first control signal V _C1, that is first predrive circuit 210 is a voltage conversion circuit (levelshifter), according to the first input signal V ₁With the first control signal V _C1Voltage level be set at the first supply voltage V _DdPerhaps Wucan is examined voltage V _Ref5And second predrive circuit 212 be coupled to second switch 204, receive and according to the second input signal V ₂With from second source voltage V _GndWith one the 6th reference voltage V _Ref6In choose one as the second control signal V _C2, similarly, second predrive circuit 212 is voltage conversion circuits, according to the second input signal V ₂With the second control signal V _C2Voltage level be set at second source voltage V _GndPerhaps the 6th reference voltage V _Ref6On the other hand, the output terminal N of output signal driver circuit 200 _OutMore be coupled to an I/O tie point (IOpad) 220 and make output terminal N _OutHas an equivalent capacitor C _Out

Note that according to one embodiment of the invention first switch 202 has breadth length ratio by one and is (W/L) ₁P type field effect transistor M _P1Realized, second switch 204 has breadth length ratio for (W/L) by one ₂N type field effect transistor M _N1Realized, the 3rd switch 206 has breadth length ratio for (W/L) by one ₃P type field effect transistor M _P2Realized, the 4th switch 208 has breadth length ratio for (W/L) by one ₄N type field effect transistor M _N2Realized, first predrive circuit 210 (comprises p type field effect transistor M by a phase inverter _P3With n type field effect transistor M _N3) realized and second predrive circuit 212 (comprises p type field effect transistor M by a phase inverter _P4With n type field effect transistor M _N4) realized.Yet, have in this technical field and to know that usually the knowledgeable can recognize, elements such as described first switch 202 of present embodiment, second switch 204, the 3rd switch 206, the 4th switch 208, first predrive circuit 210 and second predrive circuit 212, all can by etc. other electronic components of effect replaced, the internal circuit configuration of its replaceable element changes in this and just no longer adds to give unnecessary details.

Moreover, in present embodiment, p type field effect transistor M _P1, M _P2With n type field effect transistor M _N1, M _N2Be low voltage component, and because p type field effect transistor M _P1, M _P2With n type field effect transistor M _N1, M _N2Be to adopt low voltage component, so in order to make p type field effect transistor M _P1, M _P2With n type field effect transistor M _N1, M _N2Can normally operate above-mentioned the 3rd, the 4th, the 5th, the 6th reference voltage V _Ref3-V _Ref6Voltage level set between the first supply voltage V _DdVoltage level and second source voltage V _GndVoltage level between.Along with the progress of technology, as the first supply voltage V _DdVoltage level when also reducing gradually, so-called low voltage level also will with reduction, therefore in the low voltage component of embodiment indication when operating in the element of 1.3V, be example only, and be not in order to restriction the present invention with 1.3V.

In addition, for the running of clearer description output signal driver circuit 200, can set all corresponding same voltage level V of the 3rd, the 4th, the 5th, the 6th reference voltage in the present embodiment _Ref, V wherein _RefBe V _Dd/ 2, and V _DdCan be that 2.5V is (as working as output terminal N _OutWhen being coupled to the DDRI storer) or 1.8V (as output terminal N _OutWhen being coupled to the DDRII storer) or 1.5V (as when output terminal Nout is coupled to the DDRIII storer), V _GndBe 0V.The present invention is not limited to above-mentioned voltage and sets, and only is to be example with 2.5V, 1.8V and 1.5V, has in this technical field and knows that usually the knowledgeable should understand, and all magnitudes of voltage that reaches same effect must belong to claim protection domain of the present invention.

Suppose that output signal driver circuit 200 is applied to the access of DDRIII storer, so under default state, V _DdBe that 1.5V (is V _RefBe 0.75V), and output terminal N _OutOutput voltage V _OutBe 0V, at this moment the first input signal V ₁Be 0V, the second input signal V ₂Be 0V.As the first input signal V ₁With the second input signal V ₂When switching to high-voltage level such as 1.5V simultaneously, the phase inverter in the phase inverter in first predrive circuit 210 and second predrive circuit 212 export the first control signal V of 0.75V respectively _C1And the second control signal V of 0V _C2Because p type field effect transistor M _P1Gate-to-source between voltage be 0.75V (surpass threshold voltage vt h), so p type field effect transistor M _P1Understand conducting and cause p type field effect transistor M _P2So conducting thereupon is the first supply voltage V _DdCan be to output terminal N _OutEquivalent capacity C _OutCharge; On the other hand, the second control signal V _C2Can turn-off n type field effect transistor M _N1And make its disconnection, so under this state, output voltage V _OutCan be charged to till the high-voltage level 1.5V always.

Please refer to Fig. 3, Fig. 3 is p type field effect transistor M shown in Figure 2 _P1, M _P2Current-voltage characteristic curve figure.Work as output voltage V _OutRise to the process of 1.5V from 0V, can learn, low pressure p type field effect transistor M according to the curve among Fig. 3 302 _P1, M _P2Electric current can Billy be greater with the known electric current (curve 304) that the high-voltage P-type transistor is operated under the 1.5V, this means the p type field effect transistor M of present embodiment _P1, M _P2Current charges efficient be reasonable.

Next, if output terminal N _OutOutput voltage V _OutIn the time that 0V must being switched to, mean p type field effect transistor M _P1, M _P2The essential disconnection, and n type field effect transistor M _N1, M _N2Then must conducting with to output capacitance C _OutDischarge to reduce output voltage V _OutTherefore, the first input signal V ₁With the second input signal V ₂Switch to low voltage level 0V simultaneously, and the phase inverter 2122 in the phase inverter in first predrive circuit 210 and second predrive circuit 212 respectively output the first control signal V _C11And the second control signal V _C2All becoming is high-voltage level, i.e. the first control signal V _C1Be 1.5V, the second control signal V _C2Be 0.75V.Because n type field effect transistor M _N1Gate-to-source between voltage be that 0.75V (surpasses threshold voltage V _Th), so n type field effect transistor M _N1Can conducting and make n type field effect transistor M _N2With conducting, so output terminal N _OutEquivalent capacity C _OutCan be to second source voltage V _GndDischarge, on the other hand, the first control signal V _C1Can turn-off p type field effect transistor Mp1 and make its disconnection, so according to embodiments of the invention, output voltage V _OutCan be discharged to till the low voltage level 0V always.

Please refer to Fig. 4, Fig. 4 is n type field effect transistor M shown in Figure 2 _N1, M _N2Current-voltage characteristic curve figure.Work as output voltage V _OutDrop to the process of 0V from 1.5V, can learn, low pressure n type field effect transistor M according to the curve among Fig. 4 402 _N1, M _N2Electric current can Billy be greater with the known electric current (curve 404) that high-pressure N-shaped transistor is operated under the 1.5V, this means the n type field effect transistor M of present embodiment _N1, M _N2Current charges efficient be reasonable.

Please note, in the present embodiment, the all crystals Guan Jun that is utilized in the output signal driver circuit 200 is the field effect transistor of the low-voltage technology that provided of asic chip manufacturing plant, therefore the present invention can use single kind of technology (that is low-voltage technology) just to reach the requirement that meets non-low-voltage specification, as the requirement of DDRI, DDRII and DDRIII memory transfer specification.

The foregoing description illustrates with the access that output signal driver circuit 200 is applied to the DDRIII storer, yet the present invention, only needs V for other application not as limit _DdChange, and to the 3rd, the 4th, the 5th, the 6th reference voltage V _Ref3-V _Ref6Do corresponding setting and get final product, can understand how to set suitable voltage level via the disclosed circuit structure of Fig. 2 easily, therefore will no longer add to describe owing to haveing the knack of this skill person.

On the other hand, as the output terminal N of output signal driver circuit 200 _OutNeed be when subordinate's circuit receive an external voltage, p type field effect transistor M _P2With n type field effect transistor M _N2Also can not produce the phenomenon of puncture (breakdown).For example, with V _DdFor 1.5V is an example, this moment V _RefBe 0.75V, and as output terminal N _OutExternal voltage when being 1.5V or 0V, p type field effect transistor M _P2With n type field effect transistor M _N2Gate-to-source between voltage all can not surpass 1.3V, therefore, can learn according to above-described mode of operation, no matter at output terminal N _OutCharging, discharge or receive the process (such as being coupled to DDRI, DDRII or DDRIII storer) of external signal, voltage all can not surpass 1.3V between the gate-to-source of any field effect transistor, so the P type under the operated in 1.3V of present embodiment, n type field effect transistor all can not puncture because of cross-pressure is excessive.

Please refer to Fig. 5, Fig. 5 is the process flow diagram of the driving method of output signal of the present invention, and it includes step down:

Step 502: beginning;

Step 504: receive one first input signal V ₁With one second input signal V ₂

Step 506: cushion the first input signal V ₁To produce one first control signal V _C1, cushion the second input signal V ₂To produce one second control signal V _C2

Step 508: judge the first control signal V _C1With the second control signal V _C2, if the first control signal V _C1Be high-voltage level, and the second control signal V _C2Be low voltage level, then skip to step 510; If the first control signal V _C1Be high-voltage level, and the second control signal V _C2Be high-voltage level, then skip to step 512; If the first control signal V _C1Be low voltage level, and the second control signal V _C2Be low voltage level, then skip to step 514;

Step 510: output terminal N _OutNeed receive an external voltage from subordinate's circuit;

Step 512: with second source voltage V _GndWith output terminal N _OutConducting is with to output terminal N _OutDischarge;

Step 514: with the first supply voltage V _DdWith output terminal N _OutConducting is with to output terminal N _OutCharging.

The driving method of embodiments of the invention output signal at first can receive the first input signal V simultaneously in step 504 ₁And the second input signal V ₂ Step 506 can the buffering first input signal V ₁To produce one first control signal V _C1, cushion the second input signal V ₂To produce one second control signal V _C2 Step 508 can be according to the first control signal V _C1With the second control signal V _C2For high-voltage level or low voltage level decide output signal.Wherein, as if being example with output signal driver circuit 200 of the present invention, high-voltage level is V _Dd, and low voltage level is V _Dd/ 2.

The above only is the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims

1. output signal driver circuit, it includes:

One first switch, one end are coupled to one first supply voltage, and its other end is coupled to one first end points, wherein this first switch conduction whether according to one first control signal with optionally with this first supply voltage and this first end points conducting;

One second switch, one end are coupled to a second source voltage, and its other end is coupled to one second end points, wherein this second switch conducting whether according to one second control signal with optionally with this second source voltage and this second end points conducting;

One the 3rd switch, one end are coupled to this first end points, and its other end is coupled to an output terminal, wherein the 3rd switch conduction whether according to one the 3rd reference voltage with optionally with this first end points and this output terminal conducting; And

One the 4th switch, the one end is coupled to this output terminal, its other end is coupled to this second end points, wherein the 4th switch conduction whether according to one the 4th reference voltage with optionally with this output terminal and this second end points conducting;

Wherein the voltage level of the 3rd reference voltage and the 4th reference voltage is between the voltage level of the voltage level of this first supply voltage and this second source voltage.

2. output signal driver circuit as claimed in claim 1 also includes:

One first predrive circuit is coupled to this first switch and receives one first input signal, and examines with this first supply voltage and a Wucan certainly according to this first input signal and to choose one as this first control signal in the voltage; And

One second predrive circuit is coupled to this second switch and receives one second input signal, and according to this second input signal to choose one as this second control signal in this second source voltage and one the 6th reference voltage certainly;

Wherein this Wucan voltage level of examining voltage and the 6th reference voltage is between the voltage level of the voltage level of this first supply voltage and this second source voltage.

3. output signal driver circuit as claimed in claim 2, the wherein corresponding same voltage level of the 3rd reference voltage and the 4th reference voltage.

4. output signal driver circuit as claimed in claim 2, wherein this Wucan is examined voltage and the corresponding same voltage level of the 6th reference voltage.

5. output signal driver circuit as claimed in claim 1, wherein this first switch, this second switch, the 3rd switch and the 4th switch are field effect transistor, and the grid of these a plurality of switches receives this first control signal, this second control signal, the 3rd reference voltage and the 4th reference voltage respectively.

6. output signal driver circuit as claimed in claim 1, it is arranged in the storer.

7. output signal driver circuit as claimed in claim 6, wherein this storer is the heavy data transmission rate storer of a pair of.

8. output signal driving method, it includes:

According to one first control signal with optionally with one first supply voltage and one first end points conducting;

According to one second control signal with optionally with second source voltage and one second end points conducting;

According to one the 3rd reference voltage with optionally with this first end points and an output terminal conducting; And

According to one the 4th reference voltage with optionally with this output terminal and this second end points conducting;

9. method as claimed in claim 8 also includes:

Examine with this first supply voltage and a Wucan certainly according to one first input signal and to choose one as this first control signal in the voltage; And

Foundation one second input signal is to choose one as this second control signal in this second source voltage and one the 6th reference voltage certainly;

10. method as claimed in claim 9, the wherein corresponding same voltage level of the 3rd reference voltage and the 4th reference voltage, and this Wucan are examined voltage and corresponding another same voltage level of the 6th reference voltage.