CN101207116B - 在封装之间具有插头-插座型线连接的半导体封装上封装 - Google Patents

在封装之间具有插头-插座型线连接的半导体封装上封装 Download PDF

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CN101207116B
CN101207116B CN2007101962263A CN200710196226A CN101207116B CN 101207116 B CN101207116 B CN 101207116B CN 2007101962263 A CN2007101962263 A CN 2007101962263A CN 200710196226 A CN200710196226 A CN 200710196226A CN 101207116 B CN101207116 B CN 101207116B
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pcb
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张景来
卢权营
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Samsung Electronics Co Ltd
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Abstract

一种半导体封装上封装，包括下部封装、叠置在所述下部封装上的上部封装、结合至所述下部封装的上部和所述上部封装的下部中的任何一者的插头线以及结合至所述下部封装的上部和所述上部封装的下部中的任何一者的插座线。将所述插头线插入到所述插座线内，从而使所述上部和下部封装电连接。

Description

在封装之间具有插头-插座型线连接的半导体封装上封装
技术领域
本发明涉及半导体封装，更具体而言，设计具有插头-插座型线连接的半导体封装上封装。
背景技术
随着电子工业领域的技术发展，电子部件变得具有高功能性，并且高度紧凑。为了跟上这一发展，已经开发出了一种作为封装制造方法的在下部封装上叠置上部封装的封装上封装(POP)技术，以实现高密度封装，此外还开发出了半导体封装上封装技术，从而在单个衬底上安装多个集成电路。POP被越来越多地用于应用处理器(AP)和介质，其在结构上包括上部封装、下部封装以及连接所述上部封装和下部封装的连接单元。
图1示出了普通半导体POP100的正视图。参考图1，半导体POP100包括上部封装10和下部封装20。一般而言，上部封装10包括多个存储芯片12、第一印刷电路板(PCB)14、多条第一连接线16、第一模制区(moldingarea)18和多个第一球19，例如，焊球。
将存储芯片12设置在第一PCB14上。第一连接线16连接存储芯片12和第一PCB14。第一模制区18采用环氧树脂模制物料(EMC)覆盖并保护存储芯片12和第一PCB14。
第一球19位于第一PCB14下面，并且通过与形成于下部封装20的上表面上的球连接盘(未示出)结合使上部和下部封装10和20电连接。一般而言，下部封装20包括逻辑器件22、第二PCB24、多条第二连接线26、第二模制区28和多个第二球29，例如焊球。
逻辑器件22位于第二PCB24的中央。第二模制区28采用EMC覆盖并保护逻辑器件22。第二连接线26连接逻辑器件22和第二PCB24。所述多个第二球29形成于所述第二PCB24的下表面上，并将POP100电连接至母板(未示出)，POP100被机械安装到所述母板上。
如上所述，覆盖逻辑器件22的第二模制区26存在于POP100的下部封装20的中央。因此，不能将焊球布置到POP100的上部封装10的对应于下部封装20的第二模制区的区域内。
因此，随着上部封装10内包含的存储芯片的容量的增大，上部和下部封装10和20之间的互连的数量也增大。但是，布置在上部封装10内的焊球的数量受到下部封装20的结构的限制。而且，常规POP100存在与上部和下部封装10和20之间的焊球的接触的焊球可靠性相关的问题。
第一PCB14、位于第一PCB14的下表面上的第一焊球19和包括与第一焊球19接触的球连接盘(未示出)的第二PCB24的热膨胀系数互不相同。因此，当安装在母板上的下部封装20受到应力时，由于第一PCB14、第一焊球19和第二PCB24的热膨胀系数互不相同，可能在第一焊球19内产生裂纹，其将在最终的产品中，例如，在母板或存储模块中导致缺陷。
因此，需要这样一种连接POP的上部和下部封装的连接器结构，其能够提高POP的互连数量，并且能够降低由应力导致的来自母板的不利影响。
发明内容
为了解决上述和/或其他问题，本发明的示范性实施例提供了具有连接上部和下部封装的连接器的POP，其能够提高所述上部和下部封装之间的互连的数量，并且能够降低来自母板的应力的影响。
根据本发明的示范性实施例，一种半导体封装上封装包括下部封装、叠置在所述下部封装上的上部封装和多个导线连接器，每一所述导线连接器使所述上部封装和下部封装电连接，并且具有插头-插座形状的线连接。
每一导线连接器包括结合至所述下部封装的上部和所述上部封装的下部之一的插头线(plug wire)以及结合至所述下部封装的上部和所述上部封装的下部中的另一个的插座线(socket wire)，其中，将所述插头线插到所述插座线内。所述插头线可以从所述插座线上拆卸下来。
将所述插头线的两个端点结合至所述下部封装的上部和所述上部封装的下部中的任何一者，并且所述插头线具有至少一个顶点。所述插头线的厚度不同于所述插座线的厚度。
所述插座线包括第一线和第二线，所述第一和第二线中的每者使其两个端点均结合至所述下部封装的上部和所述上部封装的上部中的任何一者并且具有至少一个顶点，其中，所述第一和第二线之间具有能够使所述插头线插入到所述第一线和第二线之间的间隔，处于所述第一线和第二线之间的一端的间隔不同于处于所述第一线和第二线之间的另一端的间隔。
根据本发明的示范性实施例，一种封装上封装半导体器件包括第一封装和叠置在所述第一封装上的第二封装，其中，所述第一封装包括第一PCB、叠置在所述第一PCB上并电连接至所述第一PCB的多个存储芯片、覆盖所述存储芯片和所述第一PCB的第一模制区以及电结合至所述第一PCB的下部的一个区域的第一线，所述第二封装包括第二PCB、结合至所述第二PCB上的一个区域的逻辑器件、覆盖所述逻辑器件并结合至所述第一PCB的下部的另一个区域以支持所述第一封装的第二模制区、以及结合至所述第二PCB上的另一个区域的第二线，所述第一线和第二线具有可拆卸的插头-插座型连接。
所述第一线具有插头形状和插座形状之一，所述第二线具有插头形状和插座形状中的另一种形状，所述第一线和所述第二线插入到彼此当中。第一线的厚度不同于第二线的厚度。
将所述第一线的两个端点均结合至所述第一PCB的下部的一个区域，所述第一线具有至少一个顶点，所述第二线包括第三线和第四线，将所述第三线和第四线中的每者的两个端点均结合至所述第二PCB上的另一区域，所述第三线和第四线中的每者均具有至少一个顶点，所述第三线和第四线具有使所述第一线插入到所述第三和第四线之间的间隔，并且处于所述第三和第四线之间的一端的间隔不同于处于所述第三和第四线之间的另一端的间隔。
附图说明
通过下文结合附图的详细说明，本发明的示范性实施例将得到更为充分的理解，在附图中：
图1示出了普通半导体POP的正视图；
图2示出了根据本发明的示范性实施例的包括接线型连接器的半导体POP的正视图；
图3示出了图2所示的器件的插头线和插座线的正面透视图；
图4示出了图2所示的器件的插头线和插座线的平面图；
图5示出了图2所示的器件的插头线和插座线的背面透视图；
图6示出了图2所示的器件的插头线和插座线的侧视图。
具体实施方式
将参考示出了本发明的示范性实施例的附图，以获得对本发明、本发明的优点以及通过实施本发明而完成的目标的充分理解。在下文中，将通过参考附图说明本发明的示范性实施例来详细描述本发明。附图中的类似的附图标记表示类似的元件。
图2示出了根据本发明的示范性实施例的包括接线型连接器(wire-typeconnector)的半导体封装上封装(POP)的正视图。参考图2，半导体POP200包括上部封装210和下部封装220。上部封装210包括存储芯片12、第一印刷电路板(PCB)14、第一连接线16、第一模制区18和多条插头线212。
存储芯片12被叠置到第一PCB14上，并通过第一连接线16电连接到第一PCB14。第一模制区18覆盖存储芯片12和第一PCB14，以保护上部封装210。可以将每条插头线212结合或连接至上部封装210的下部和下部封装220的上部之一。例如，可以将每条插头线212电结合或连接至第一PCB14的下部的区域。
下部封装220包括逻辑器件22、第二PCB24、多条第二连接线26、第二模制区221、多条插座线222和多个第二球29，例如焊球。逻辑器件22位于第二PCB24上的区域内。
第二模制区221覆盖并保护逻辑器件22。第二模制区221改善了具有叠置结构的上部封装210和下部封装220的组合的特性并结合至第一PCB14的下部的另一区域以支持上部封装210。
可以将每条插座线222与上部封装210的下部和下部封装220的上部中的另一个结合。例如，可以将每条插座线222结合至第二PCB24上的另一区域。将插头线212之一形成为插到插座线(222)中的对应插座线内。将插头线212之一形成为以可拆卸的方式插到插座线222中对应于所述插头线的插座线内。
可以将插头线212形成为具有与对应的插座线222不同的厚度。插头线212中的任何一条以及插座线222中的任何一条都能够电连接上部和下部封装210和220。
具有POP200的插头线212和插座线222的互连器，例如，212与222相结合，所占据的空间比常规互连器，例如图1所示的第一焊球19更小。因而，与常规技术相比，根据示范性实施例的POP200能够提高互连器的数量。通过第二焊球29将POP200安装到母板(未示出)上。下部封装220通过第二焊球29受到母板的应力作用。
在采用焊球连接器的常规POP100中，当POP100受到应力作用时，可能在焊球29内产生裂纹。采用根据所述示范性实施例的具有插头-插座型结构的线连接器的POP200能够缓冲第一PCB14和第二PCB24之间的应力差异，也就是说，能够防止由于热膨胀系数差导致的在连接第一PCB14和第二PCB24的连接器内产生裂纹。
图3示出了图2所示的插头线和插座线的正面透视图，图4是图2所示的插头线和插座线的平面图。图5是图2所示的插头线和插座线的背面透视图，图6是图2所示的插头线和插座线的侧视图。
参考图3到图6，插头线212之一的两个端点与诸如第二PCB24的下部封装220的上部和诸如第一PCB14的上部封装210的下部之一结合。将插头线212的形状构造为具有至少一个顶点，以形成(例如)梯形。
每条插座线222包括第一线312和第二线314。将第一线和第二线312和314中的每者的两个端点结合或连接至诸如第二PCB24的下部封装220的上部和诸如第一PCB14的上部封装210的下部中的另一个。可以将第一线和第二线312和314中的每者形成为具有至少一个顶点。
如图4所示，将第一线和第二线312和314形成为具有间隔d1，从而使插头线212能够插到第一线312和第二线314之间。
将插头线212插到第一线和第二线312和314之间。由于将插头线212插到了第一和第二线312和314之间，因而使上部和下部封装210和220相互电连接。这样，由于将插头线212插到了插座线312和314之间，因此与常规技术相比根据所述示范性实施例的POP200能够降低POP的高度。
将第一和第二线312和314形成为，使处于第一和第二线312和314之间的一端的间隔d1不同于处于第一和第二线312和314之间的另一端的间隔d2(d1≠d2)。例如，第一线312可以具有梯形形状，而第二线314可以具有从第一线312朝外弯曲的梯形形状，如图4所示。这样可以使插头线212容易地插入到第一和第二线312和314之间。
如上所述，根据本发明的示范性实施例的半导体POP采用了具有插头-插座型接线结构的连接器，因而能够提高上部和下部封装之间的互连的数量。而且，根据本发明的示范性实施例的半导体POP能够防止由于来自母板的应力导致在连接器内产生裂纹，并且能够降低POP的高度。
尽管已经参考本发明的示范性实施例对本发明进行了具体的图示和文字描述，但是本领域的普通技术人员应当理解，在不背离由权利要求界定的本发明的精神和范围的情况下可以对其做出各种形式和细节上的改变。
本申请根据35U.S.C.§119要求于2006年12月22日提交的韩国专利申请No.10-2006-0133153的优先权，在此将其全文引入以供参考。

Claims (7)

1.一种半导体封装上封装，包括：
下部封装；
叠置在所述下部封装上的上部封装；以及
多个导线连接器，所述导线连接器中的每者使所述上部封装和所述下部封装电连接，并且具有插头-插座形状的线连接，
其中，每一导线连接器包括：
插头线，其结合至所述下部封装的上部和所述上部封装的下部之一；以及
插座线，其结合至所述下部封装的上部和所述上部封装的下部中的另一个，
其中，所述插头线插到所述插座线内，以及
所述插头线的两个端点结合至所述下部封装的上部和所述上部封装的下部之一，并且所述插头线具有至少一个顶点。
2.根据权利要求1所述的半导体封装上封装，其中，可以将所述插头线从与所述插座线的连接中拆下。
3.根据权利要求1所述的半导体封装上封装，其中，所述插头线的厚度与所述插座线的厚度不同。
4.根据权利要求1所述的半导体封装上封装，其中，所述插座线包括第一线和第二线，所述第一和第二线中的每者使其两个端点结合至所述下部封装的上部和所述上部封装的下部中的任何一者并且具有至少一个顶点，
其中，所述第一和第二线之间具有间隔，从而使所述插头线能够插入到所述第一线和第二线之间，且处于所述第一线和第二线之间的一端的间隔不同于处于所述第一线和第二线之间的另一端的间隔。
5.一种封装上封装半导体器件，其包括第一封装和叠置在所述第一封装下的第二封装，其中，所述第一封装包括：
第一印刷电路板；
多个存储芯片，其叠置在所述第一印刷电路板上，并且电连接到所述第一印刷电路板；
第一模制区，其覆盖所述多个存储芯片和所述第一印刷电路板；以及
第一线，其电结合至所述第一印刷电路板的下部的一个区域，并且其中，所述第二封装包括：
第二印刷电路板；
位于所述第二印刷电路板的一个区域上的逻辑器件；
第二模制区，其覆盖所述逻辑器件，并结合至所述第一印刷电路板的下部的另一区域，以支持所述第一封装；以及
第二线，其结合至所述第二印刷电路板上的另一区域，并且
所述第一线和所述第二线具有可拆卸的插头-插座连接，
其中，所述第一线具有插头形状，所述第二线具有插座形状，所述第一线插入到所述第二线内，所述第一线的两个端点结合至所述第一印刷电路板的下部的所述一个区域，并且所述第一线具有至少一个顶点，或者
所述第一线具有插座形状，所述第二线具有插头形状，所述第二线插入到所述第一线内，所述第二线的两个端点结合至所述第二印刷电路板上的所述另一区域，并且所述第二线具有至少一个顶点。
6.根据权利要求5所述的封装上封装半导体器件，其中，所述第一线的厚度不同于所述第二线的厚度。
7.根据权利要求6所述的封装上封装半导体器件，其中，所述第一线的两个端点均结合至所述第一印刷电路板的下部的一个区域，且所述第一线具有至少一个顶点，所述第二线包括第三线和第四线，所述第三线和第四线中的每者的两个端点均结合至所述第二印刷电路板上的另一区域，且所述第三线和第四线中的每者均具有至少一个顶点，所述第三线和第四线具有使得所述第一线插入到所述第三和第四线之间的间隔，并且处于所述第三和第四线之间的一端的间隔不同于处于所述第三和第四线之间的另一端的间隔。
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