CN101203919A - Fast read port for register file - Google Patents

Abstract

Separate read (RWL, RBL) and write (WL, BL, BL ports in a memory system allow simultaneous access to a memory cell array (302) by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks (315, 320) connected to memory cell latch loops (305, 310) allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack (345) of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier (440) provides a mid- supply- level precharging capability provided by a feedback device (415) within a front-end inversion stage (420) . When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage (430) provides a rapid read response.

Description

The fast read port that is used for register file

Technical field

The present invention relates to accumulator system and read operation.More particularly, the present invention has the single-ended read port of integral precharge capability and sensor amplifier.

Background technology

Usually using the static memory cell that is made of six transistors in reservoir designs satisfies at lacking access cycle time, high-frequency data speed, low power consumption and to the requirement of the fabulous immunity of extreme environmental conditions.

Referring to Figure 1A, in prior art static memory cell Figure 101, the numerical data in the memory cell latch loop that the phase inverter that six transistors (6-T) unit latches is coupled by pair of cross forms.First complementary inverter is made of a PMOS transistor 115 and first nmos pass transistor 125.Second complementary inverter is made of the 2nd PMOS transistor 120 and second nmos pass transistor 130.A pair of access device is used to make memory cell latch loop and bit line BL and paratope line Connect and disconnection.Described access device is the 3rd nmos pass transistor 105 and the 4th nmos pass transistor 110 that is connected to the input of second complementary inverter that is connected to the input of first complementary inverter.Access device is enabled by the selection signal on the word line WL.

Referring to Figure 1B, in prior art dual port memory cell Figure 102, memory cell latch loop is expressed as cross-linked phase inverter 140,145, and has two pairs of access devices that form two access ports.Access when utilizing memory array to improve to two different memory positions providing by the dual-memory port.By be connected to the first bit line BL1 and first paratope line from memory cell latch loop

First pair nmos transistor 110,105 form first access port.The first word line WL1 enables described first pair of access device.Be connected to the second bit line BL2 and second paratope line from memory cell latch loop

Second pair nmos transistor 165,160 form second access port.

The second word line WL2 enables described second pair of access device.

Referring to Fig. 1 C, in prior art accumulator system Figure 103, row decoder 180 selects to be connected to the word line of the memory cell in the memory cell array 170.The bit line of column decoder 185 selection memory unit.Reading and write amplifier 190 is connected to bit line and reads and the write store unit after selected pair of bit lines being used for.Controll block 175 is connected to row decoder 180, column decoder 185 and reads and write amplifier 190, to be provided for reading address and the control signal with write operation.

Give the 6th of being entitled as of people such as Sheffield " Static Memory with Low Power Write Port ", 005, No. 794 United States Patent (USP)s are described the port circuit that writes of static memory cell, it is included in first output of latch and the first condition conducting path between the ground connection, word line input that and if only if in described path and effective when writing the true bit line input of data and all receiving useful signal.The said write port circuit is included in second output of latch and the second condition conducting path between the ground connection, and if only if in described path word line and effective when writing data complement code bit line and all receiving useful signal.The described first and second condition conducting paths can be formed by being connected in series of two transistorized source electrode-drain path.In each condition conducting path, the grid of the first transistor receives corresponding column signal, and the grid of transistor seconds is connected to word line.But shared word line transistor between the bitline transistor of the memory cell in the adjacent column of single memory cell or a plurality of adjacency.Memory cell can comprise a plurality of inbound ports of writing, and wherein writes port circuit and is used for each examples of ports.Although ' 794 patents use pull-down stack and on draw and pile up both and drive reading bit line, drawing on each that repeats in each unit needs two PMOS transistors in piling up.On draw to pile up and repeat to have increased global memory array size and complicacy.

Referring to Fig. 2, in prior art phase inverter transfer characteristic Figure 200, transfer curve 210 is at V _InAxle (horizontal ordinate) and V _OutThe intercept of axle (ordinate) is for about The some place get over equipotential line 205.Described equipotential line is by making input voltage equal output voltage (V _Out=V _In) and the track of the point that defines.Therefore, described equipotential line is the line of the one-tenth miter angle that begins from initial point.The transfer characteristic of phase inverter is general, and it has corresponding to high-level output voltage V _OutLow-level input voltage V _In, and vice versa.Under the situation of the CMOS of phase inverter transistor embodiment, the β ratio of drawing upwardly device and pull device is through mating to realize that equipotential line is about

The transfer curve at place intersects.

More particularly, draw on pull device at operating point $V_{\mathrm{in}}=\frac{{\mathrm{<figure-callout\; id="2"\; label="V\; DD"\; filenames="S2006800071566E00021.png,S2006800071566E00081.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{DD}}}{2}$ Be in its saturation region separately and operate.For the transfer curve that makes equipotential line is getted over about

The place takes place, and as far as possible closely follow following design and consider: the saturation current of p type drawing upwardly device is $I_{\mathrm{dsp}}=-\frac{{\mathrm{\&beta;}}_p}{2}{(V_{\mathrm{in}}-V_{\mathrm{DD}}-V_{\mathrm{tp}})}^2,$ The saturation current of n type pull device is $I_{\mathrm{dsn}}=-\frac{{\mathrm{\&beta;}}_n}{2}{(V_{\mathrm{in}}-V_{\mathrm{tn}})}^2,$ And since on draw with pull device and be connected in series, I so _DsP=-I _DsnFind the solution V _In:

$V_{\mathrm{in}}=\frac{V_{\mathrm{DD}}+V_{\mathrm{tp}}+V_{\mathrm{tn}}\sqrt{\frac{{\mathrm{\&beta;}}_n}{{\mathrm{\&beta;}}_{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="S2006800071566E00051.png,S2006800071566E00061.png"\; state="\{\{state\}\}">p</figure-callout>}}}}}{1+\sqrt{\frac{{\mathrm{\&beta;}}_n}{{\mathrm{\&beta;}}_p}}},$ And setting β _n=β _pAnd V _Tn=-V _Tp, then the result is $\mathrm{Vin}=\frac{V_{\mathrm{<figure-callout\; id="2"\; label="DD"\; filenames="S2006800071566E00021.png,S2006800071566E00081.png"\; state="\{\{state\}\}">DD</figure-callout>}}}{2}.$

Summary of the invention

In the accumulator system read separately and write inbound port allow read with write operation in access memory unit array simultaneously.The single cycling of being coupled to the CPU (central processing unit) of memory cell array depends on to incorporate into the storage access ability that reads simultaneously with write operation.The a pair of pull-down stack of transistors that is coupled to memory cell latch loop allows the selected single pull-down stack of described centering that memory cell latch loop is triggered to required data content and without any need for the precharge scheme.The extra single pull-down stack of transistors that is connected to memory cell latch loop provides the read port that has low input load and upset the minimum possibility of memory cell data content in read operation.Sensor amplifier provides the intermediate power supplies level precharge capability that is produced by the feedback assembly in the front end inverter stages.Provide quick read response with the front end inverter stages of the second inverter stages cascade.Memory cell of the present invention can be used for register file, special-purpose SRAM or general SRAM.

Description of drawings

Figure 1A is the synoptic diagram of prior art six transistor static memory cell.

Figure 1B is the synoptic diagram with prior art six transistor static memory cell of dual-port access.

Fig. 1 C is the figure with prior art accumulator system of the memory cell array of being made up of the unit of six transistor static memory cell of for example Figure 1A.

Fig. 2 is the figure of the transfer curve of prior art CMOS phase inverter.

Fig. 3 A is the exemplary schematic representation of static memory cell of the present invention.

Fig. 3 B is the exemplary schematic representation with static memory cell of dual port read access of the present invention.

Fig. 4 A is the schematic block diagram of sensor amplifier of the present invention.

Fig. 4 B is that the sensor amplifier at Fig. 4 A detects an equivalent electrical circuit electric current flow graph as data content in the read operation of the static memory cell of Fig. 3 A.

Fig. 4 C is that the sensor amplifier at Fig. 4 A detects the zero equivalent electrical circuit electric current flow graph as data content in the read operation of the static memory cell of Fig. 3 A.

Fig. 5 is the concept map of feedback behavior in the first order of the sensor amplifier of Fig. 4 A.

Fig. 6 is the amplification characteristic figure corresponding to sequence of inverters in the sensor amplifier of Fig. 4 A.

Fig. 7 be incorporate into memory array is arranged, the example system block scheme of the present invention of multiplexer and sensor amplifier.

Fig. 8 be Fig. 4 A sensor amplifier reading bit line precharge and read the round-robin logic timing figure.

Embodiment

Referring to Fig. 3 A, in the exemplary schematic representation of static memory cell 301, a CMOS phase inverter 305 and the 2nd CMOS phase inverter 310 cross-couplings.The described first and second CMOS phase inverters 305,310 form the memory cell latch loop 333 of static RAM (SRAM) unit.Output by the first and second CMOS phase inverters 305,310 forms first output Q of memory cell latch loop and second output of memory cell latch loop respectively

The first output Q of memory cell latch loop is connected to the output drain electrode of first transistor stack 315.Second output of memory cell latch loop

Be connected to the output drain electrode of second transistor stack 320.Second output of memory cell latch loop Be also connected to the data input of the 3rd transistor stack 345.Described first, second is shown as being connected in series of (for example) nmos pass transistor with the 3rd transistor stack 315,320,345, and wherein common-source-drain diffusion is connected with conduction.

Word line WL is connected in first and second transistor stack 315,320 the control input of each.First and second transistor stack 315,320 are connected to pair of bit lines.The first bit line BL is connected to the data input of second transistor stack 320.Second bit line Be connected to the data input of first transistor stack 315.Reading bit line RBL is connected to the output drain electrode of the 3rd transistor stack 345 to form read port.Read word line RWL and be connected to the first control input of the 3rd transistor stack 345.

In another embodiment (not shown), the read port that is formed by the 3rd transistor stack 345 can use with incorporating the cell array of writing inbound port just like the standard shown in Figure 1A into.As described previously, the 3rd transistor stack 345 is connected to With read word line RWL, and drive reading bit line RBL.

Referring to Fig. 3 B, in the exemplary schematic representation of dual port sram cell 302, second output of memory cell latch loop

Be also connected to the data input of third and fourth transistor stack 345,355.Described third and fourth transistor stack 345,355 is shown as being connected in series of (for example) nmos pass transistor, and wherein common-source-drain diffusion is connected with conduction.

The first reading bit line RBL1 is connected to the output drain electrode of the 3rd transistor stack 345 to form first read port.Second reading bitline RBL2 is connected to the output drain electrode of the 4th transistor stack 355 to form second read port.First reads the control input that word line RWL1 is connected to the 3rd transistor stack 345.Second reads the control input that word line RWL2 is connected to the 4th transistor stack 355.

Referring to Fig. 4 A, the output of reading bit line multiplexer 405 is connected to the exemplary amplifier 440 of reading.The input of sensor amplifier 440 is connected to the output drain electrode of drawing upwardly device 410 and the input of first phase inverter 420.Drawing upwardly device 410 is connected to V _DDLevel and control the input through bias voltage to be in pull-up state continuously.Drawing upwardly device 410 can (for example) by having the V of being connected to _DDSource node, the drain electrode of input that is connected to sensor amplifier 440 and the PMOS transistor that is connected to the control input of ground connection constitute.The output of first phase inverter 420 is connected to the input of second phase inverter 430 and the input of feedback assembly 415.The output of feedback assembly 415 is connected to the input of first phase inverter 420.Because conduction of current is by the cause of the symmetric property of the input of the feedback assembly 415 and first phase inverter 420, the first order of sensor amplifier 440 is transimpedance amplifiers.Equalizing signal is connected to the control input EQ of feedback assembly 415.The output of second phase inverter 430 is connected to data output DOUT.In an exemplary embodiment, reduce equalizing signal to close the control input EQ of feedback assembly, so that reduce power consumption.Yet, in another embodiment, can change (for example) into EQ is linked V continuously _DDTo obtain the access time faster.When feedback assembly 415 is enabled, sensor amplifier 440 will still be read.Can mate the transfer characteristic of first phase inverter 420 and second phase inverter 430 approx to reduce skew by simplated placement's technology.In order to the simplated placement's technology that reduces to be offset is that the those skilled in the art is well-known.

Many reading bit line (RBL1, RBL2, RBL3 ..., RLBn) be connected to each bit line input of reading bit line multiplexer 405.Reading bit line multiplexer 405 read address input RA receive the reading bit line that is connected to memory cell to be read (RBL1, RBL2, RBL3 ..., RLBn) in one address.Read and enable input RD and receive to read and enable signal with the control read operation.By the exemplary total reading bit line load capacitance of reading bit line load capacitor 455 expressions that is connected to (for example) high-order bit line RBLn.

The one exemplary embodiment of the present invention of Fig. 4 A also comprises the exemplary amplifier 440 of reading with intrinsic precharge capability.Sensor amplifier 440 is incorporated into the feedback assembly 415 of crossing over first phase inverter 420, and it causes the input of sensor amplifier 440 to be sought about V _DDAnd the stationary voltages level of the midpoint between the ground connection (that is, $V_{\mathrm{in}}\&cong;\frac{{\mathrm{<figure-callout\; id="2"\; label="V\; DD"\; filenames="S2006800071566E00021.png,S2006800071566E00081.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{DD}}}{2}$ )。Sensor amplifier 440 is twin-stage non-inverting buffers.The cascade of two anti-phase buffer stages 420,430 produces high-gain and short reading the access time.Weak point reads the access time permission and in the single clock circulation system same memory cell array is write simultaneously.

Referring to Fig. 4 B, the data content of selected unit 460 is one (" 1 ").The pull-down stack 345 (Fig. 3 A) that is connected to reading bit line RBL receives from memory cell latch loop 333

The low logic level signal of output.The read port that is formed by pull-down stack 345 disconnects, and therefore non-leakage any electric current passes equivalent pull-down current source 465 (that is, zero current or I=0).It is the constant source electric current of I that drawing upwardly device 410 (Fig. 4 A) provides the value by 411 expressions of equivalent pullup device current source.Electric current I from equivalent pullup device current source 411 flows into sensor amplifier 440 inputs.Enabled under the situation of feedback assembly 415 by the input control grid that continues to be connected to the supply of (for example) high-voltage level, electric current I flows into feedback assembly 415 and flows into the output of first phase inverter 420.The electric current I that the output of first phase inverter 420 is passed in 480 indications of first equivalent current source flow to ground connection.For the help to understanding is provided, suppose (promptly, in fact not being the part of sensor amplifier 440 circuit) voltage potential measurement device 499 monitors the output of first phase inverter 420, and the indication output potential is in following (that is V, of input current potential of first phase inverter 420 _Out＜V _In).First phase inverter, 420 places are because the equivalent current source generation of drawing upwardly device 411 is passed the electric current of (resistive) feedback assembly 415 and caused on the phase inverter 420 from being input to the voltage drop (V of output from the potential difference (PD) that outputs to input _In-V _OutFor just) cause.From relatively low voltage feed-in second phase inverter 430 of first phase inverter, 420 outputs, and the data content in the selected unit 460 of generation indication, DOUT node place is one high level output.

Referring to Fig. 4 C, the data content of selected unit 460 is zero (" 0 ").The pull-down stack 345 (Fig. 3 A) that is connected to reading bit line RBL receives from memory cell latch loop 333 The high logic level signal of output.Connect and guide the electric current 2I that represents by equivalent pull-down current source 465 by the read port that transistor stack 345 forms.It is the constant source electric current of I that drawing upwardly device 410 (Fig. 4 A) provides the value by 411 expressions of equivalent pullup device current source.Flow into the output of the read port pulldown stack 345 of selected unit 460 from the electric current I of equivalent pullup device current source 411.Enabled under the situation of feedback assembly 415 by the input control grid that continues to be connected to the supply of (for example) high-voltage level, electric current I flows out the output of first phase inverter 420 and flows into feedback assembly 415.Second equivalent current source, 485 indicator current I enter first phase inverter 420 at high level supply voltage node place.For the help to understanding is provided, (that is, in fact not being the part of sensor amplifier 440 circuit) voltage potential measurement device 499 of supposing monitors the output of first phase inverter 420, and indicates the output potential of first phase inverter 420 to be in more than the input current potential.The rising output potential of first phase inverter 420 is owing to be derived from the electric current of output place and produce and to pass the electric current of (resistive) feedback assembly 415 and cause on the phase inverter 420 from outputing to the voltage drop (V of input _In-V _OutFor negative) cause.Producing the remainder of indicating selected unit 460 from relative high voltage feed-in second phase inverter 430 of first phase inverter, 420 outputs and at the DOUT node exports according to the low level of content.Therefore, sensor amplifier 440 is the transimpedance amplifiers of direction of current flow that read out in the input of sensor amplifier 440.

Referring to Fig. 5, in the notion feedback diagram 500 of the feedback behavior in the first order of the sensor amplifier 440 of Fig. 4 A, the first phase inverter transfer characteristic 505 and 515 cascades of the second phase inverter transfer characteristic.In the first order of sensor amplifier 440, the output of first phase inverter 420 is connected to feedback assembly 415.The output of feedback assembly 415 is connected to the input of first phase inverter 420.Form the graphic depiction of feedback characteristic by the cascade of two examples 505,515 of phase inverter transfer characteristic.

In the first phase inverter transfer characteristic 505, general phase inverter transfer curve 510 is about The place intersects with equipotential line.The second phase inverter transfer characteristic 515 is turn clockwise 90 ° and flip verticals of the same general phase inverter transfer curve 510 of the first phase inverter transfer characteristic 515.The output signal of first phase inverter 420 (Fig. 4 A) becomes the input signal of first phase inverter 420 after passing feedback assembly 415.On figure, watch the V of the first phase inverter transfer characteristic 505 _OutAxle is aimed at the input shaft of the second phase inverter transfer characteristic 515, and described input shaft for clarity sake is marked as V _InFB, wherein upwards describe the current potential that increases.

Because changing, the input voltage of the sensor amplifier 440 that drawing upwardly device 410 causes is marked as Δ V _PUThe input voltage change of the first order is marked as Δ V _OutAnd because the anti-phase character of the first order and along V _OutAxially change down.The corresponding Δ V that newly is input as from feedback assembly 415 to first phase inverter 420 _InFB, its same change downwards.Since the cause of the gain of the first order, Δ V _InFBValue than Δ V _PUValue much bigger.Δ V in the second phase inverter transfer characteristic 515 _InFBThe current potential and the Δ V of downward change _PUUpwards (axle as shown) change on the contrary, and have relatively large value.Therefore, Δ V _InFBRemoved the trend of the increase of the current potential that causes by drawing upwardly device 410 in sensor amplifier 440 inputs.Amount of gain in the first order also is the indicator of intensity of the precharge capability of sensor amplifier 440.

Referring to Fig. 6, in amplification characteristic Figure 60 0 corresponding to the sensor amplifier 440 of Fig. 4 A, the first phase inverter transfer characteristic 605 and 615 cascades of the second phase inverter transfer characteristic.The first phase inverter transfer curve 510 (repeating with Fig. 5) is approaching

The place intersects with equipotential line.Reading bit line range of signal Δ V along the horizontal ordinate of the first phase inverter transfer characteristic 605 _RBLCorresponding to bigger first inverter signal output Δ V _Out1The second phase inverter transfer curve 620 is approaching The place intersects with equipotential line.By noticing that employed physical layout design rule is mated the first phase inverter transfer curve 510 and the second phase inverter transfer curve 620 in the making of first and second phase inverters 420,430.

First inverter signal output Δ V _Out1Be the second phase inverter input signal Δ V _In2Ordinate with the second phase inverter transfer characteristic 615.The amplification characteristic of second phase inverter 430 is through being designated as along the sensor amplifier signal output Δ V of the horizontal ordinate of the second phase inverter transfer characteristic 615 _DOUTReading bit line range of signal Δ V _RBLLess relatively value can be created in sensor amplifier signal output Δ V _DOUTIn on current potential, cross over the variation of approximate boundaries to bounds.

Referring to Fig. 7, in exemplary embodimentsan example memory system block scheme 700, memory cell array 770 is connected to sensor amplifier 440 by reading bit line multiplexer 405.To read the address and be provided to reading bit line multiplexer 405 reading address input RA place.Provided read the address by reading bit line multiplexer 405 use with select reading bit line (RBL1 ..., RBLn) in single one.Read when enabling signal RD_EN when reading bit line multiplexer 405 receives, will select reading bit line (RBL1 ..., RBLn) in single one and power path is provided to the output of reading bit line multiplexer 405.The output of reading bit line multiplexer 405 is connected to the input of sensor amplifier 440 (Fig. 4 A).Controller 775 is connected to memory cell array 770 to be provided for word line and to read the control signal that word line is selected.

Referring to Fig. 8, in the example logic sequential chart of the accumulator system of Fig. 7, address V is read in reception after the rising of clock signal clk changes just _RAApply balanced precharge enable signal EQ_EN at the control signal input EQ place of sensor amplifier 440 (Fig. 4 A) and read the round-robin standard component as the typical case.Precharge enable signal EQ_EN starts the feedback assembly 415 of the input and output of electric coupling first phase inverter 420 in the sensor amplifier 440.Sensor amplifier input voltage V _{SA_in}Be maintained at high-voltage level by drawing upwardly device 410, till feedback assembly 415 is activated.Under the situation that feedback assembly 415 is activated, sensor amplifier input voltage V _{SA_in}Change the pre-charge voltage current potential that is similar to centre between mains voltage level and the ground connection into from high-voltage level.Because the cause of passing the conducting path of feedback assembly 415 attempts keeping V at first phase inverter 420 _OUT=V _INThe phase inverter operating conditions time (as discussed previously), precharge transition takes place.

Be applied to reading of reading bit line multiplexer 405 (Fig. 4 A) enable reading of input RD enable signal RD_EN selected reading bit line (RBL1, RBL2 ..., RBLn) and sensor amplifier 440 between conducting path is provided.Enable signal RD_EN, read bitline voltage V by applying to read _RBLTo change the precharge voltage level that produces in the input of sensor amplifier 440 into.Therefore, read bitline voltage V _RBLAlso present the voltage potential in the middle of being similar between mains voltage level and the ground connection.When reaching precharge voltage level, sensor amplifier 440 prepare to read along with selected reading bit line (RBL1, RBL2 ..., RBLn) memory cell of associated memory cells row.Feedback assembly is enabled sensor amplifier 440 first order sensing circuits equally selected reading bit line is carried out precharge.With being applied to the read port that the selection signal access of reading word line RWL (Fig. 3 A) is used for one or more memory cells.When will read the address put on reading bit line multiplexer 405 read address input RA the time, select reading bit line (RBL1 ..., RBLn) in single one.By will read word line selection signal RWL_SEL be applied to read word line RWL and be applied to reading bit line multiplexer 405 read address V _RAEnable from the memory cell to the sensor amplifier 440 single read path.Sensor amplifier 440 with reading bit line (RBL1 ..., RBLn) in selected one be pre-charged to approaching

Level.Only to selected reading bit line (RBL1 ..., RBLn) carry out precharge, and then eliminate selected reading bit line (RBL1 ..., RBLn) on the waste electric charge and reduce power consumption.

Controller 775 (Fig. 7) uses and reads address V _RADetermine to read the selection of word line RWL (Fig. 3 A).Read word line selection signal RWL_SEL and produce and put on memory cell array 770 by controller 775.Read word line selection signal RWL_SEL and be applied to selected reading word line RWL and be input to transistor stack 345 read ports.The read port output of word-select memory unit is connected to reading bit line RBL.If storage zero in selected unit, read port draws reading bit line RBL into low so, thereby produces low level reading bit line signal V _RBL, perhaps the content of elected order unit is that read port will be kept opening or electric tri-state condition with respect to reading bit line RBL for the moment.The data content of elected order unit be a period of time, owing to the cause of drawing upwardly device 410 produces high level reading bit line signal V _RBL

The conducting path that passes reading bit line multiplexer 405 (Fig. 4 A) between sensor amplifier 440 and the reading bit line RBL means sensor amplifier input voltage V _{SA_in}To follow reading bit line signal V _RBL First phase inverter 420 and second phase inverter 430 are connected in series in the sensor amplifier 440 and produce follows sensor amplifier input voltage V _{SA_in}Data output signal V _DOUTBy after the propagation delay of first and second phase inverters 420,430, produce data output signal V at data output node DOUT place _DOUT

The present invention has the many additional advantage that are better than prior art that those skilled in the art will realize that.In the present invention, the read port that is formed by pull-down stack of transistors is connected to the memory cell latch loop with less single device input load.Compared with prior art, it is continuous that read port is electrically connected, and therefore can be owing to electric switch the data content of interrupt storage unit.The access device that field effect transistor in the transmission gate configuration of continuous connection features of the present invention and prior art forms forms contrast.In the prior art, the transmission grid type connects the great change of the electric capacity cause being coupled to memory cell during switch.Therefore, the management of the voltage potential on the bit line that is connected by transmission grid access device is crucial for the data content of avoiding upsetting the unit in the prior art.Strict precharge scheme is required to cause by prior art neutrality line voltage management.It is this key that read port of the present invention has been avoided.

In addition, the read port that connects as single device of the present invention is electrically connected and is called as single-ended read port.The contrast scheme of prior art is incorporated into differential read ports, and it requires two devices and memory cell latch loop, second reading bitline and drop-down and pull up transistor to pile up and be electrically connected.Compare with the memory cell array of constructing with single-ended read port of the present invention, conventional differential read ports requires much more area to be used for memory cell array.

Memory cell read schemes of the present invention will only be selected and the single reading bit line of precharge at every turn.Compare with the art methods of batch precharge reading bit line, single bit-line pre-charge has significantly reduced each quantity of power that circulates and consumed of read operation.The single reading bit line that the present invention also will select is precharged as the voltage potential of the intermediate value between about voltage source level and the ground connection.For

Approximate precharge voltage level reduced required time and the quantity of power of pre-charging stage of finishing read operation.Time of saving and quantity of power and requirement are pre-charged to fully or contrast near the prior art scheme formation of mains voltage level completely.For require to be pre-charged to be used for the difference reading bit line and be used for all reading bit line concerning the conventional scheme of complete mains voltage level, described contrast even bigger.

Sensor amplifier of the present invention and pre-charge circuit are by only being precharged as single reading bit line

Level and the power consumption in the read operation is minimized.Be used to realize that the Voltage Feedback member of pre-charge level is terse; It neither needs extra self-timing circuit, extra dedicated control circuit, does not also need the control signal routing.Read port utilization of the present invention has the single-end circuit of the low load of memory cell latch loop during reading.With read circuit based on transmission grid internuncial routine and compare, single-ended method has been saved area and can not have been disturbed the data level of being stored during read operation.

Although oneself has described the present invention according to specific embodiment substantially, those skilled in the art will realize that also available alternative method realizes some circuit component.For instance, although bumper member is shown as the CMOS phase inverter, bumper member also can be embodied as operational amplifier.Although feedback means has been depicted as the NMOS FET that grid is linked high level control voltage, the those skilled in the art will readily appreciate that PMOSFET or junction field effect transistor that the control grid is linked low level control voltage also will realize identical result.Although will on to draw component representation be the PMOS FET that grid is connected to earthing potential, the those skilled in the art will dream up easily by resistor make with reach similar results on draw member.Be depicted as NMOS transmission grid although will write member, the those skilled in the art will expect providing the PMOS transmission grid of equivalent capability easily.

Claims (10)

1. memory cell in accumulator system, it comprises:

First and second phase inverters, to form memory cell latch loop, described memory cell latch loop has true output and complementary output to described first and second phase inverters through cross-couplings;

First writes inbound port, and described first writes the described true output that inbound port is configured to be coupled to described memory cell latch loop, and described first writes inbound port is coupled to first bit line and word line;

Second writes inbound port, and described second writes the described complementary output that inbound port is configured to be coupled to described memory cell latch loop, and described second writes inbound port is coupled to second bit line and described word line; And

First read port, described first read port is configured to be coupled to single reading bit line, word line is read in the described complementary output and first that described first read port is coupled to described memory cell latch loop, and described first read port is a transistor stack.

2. memory cell according to claim 1, wherein second read port is configured to be coupled to the second single reading bit line, and word line is read in the described complementary output and second that described second read port is coupled to described memory cell latch loop.

3. memory cell according to claim 2, wherein said second read port is a transistor stack, and described transistor stack has second input and the output that is configured to be coupled to the described second single reading bit line of being coupled to second first input of reading word line, being coupled to the described complementary output of described memory cell latch loop.

4. memory cell according to claim 1, described first read port that wherein is coupled to described complementary output has special-purpose single device as second input of being coupled to described memory cell latch loop, and described second input has constant input load.

5. memory cell according to claim 1, wherein said each that write in the inbound port are to have in described true output or described complementary output place to be coupled to the transistor stack of the diffusion output of described memory cell latch loop.

6. sensor amplifier in accumulator system, it comprises:

First phase inverter, described first phase inverter are configured to read the signal that is received by described sensor amplifier and produce pre-charge voltage on bit line, and described bit line is configured to be coupled to described sensor amplifier;

Feedback assembly, described feedback assembly are coupling between the output of the input of described first phase inverter and described first phase inverter, and described feedback assembly is configured to described pre-charge voltage is sent to the input of described first phase inverter;

Drawing upwardly device, described drawing upwardly device are coupling between the output of the input of described first phase inverter and power level voltage source; And

Second phase inverter, described second phase inverter is coupled to the described output of described first phase inverter and is configured to and receives first output signal and produce second output signal from described first phase inverter, described second output signal is the output signal of described sensor amplifier, and described second output signal is the amplified version of described first output signal.

7. sensor amplifier according to claim 6, the pre-charge voltage of wherein said generation are in the level in the middle of being similar between power level voltage and the ground connection.

8. sensor amplifier according to claim 6, the voltage of wherein said first phase inverter are input to the voltage that voltage output transfer characteristic approximates described second phase inverter greatly and are input to voltage output transfer characteristic.

9. sensor amplifier according to claim 6 is wherein enabled described feedback assembly continuously so that the value of the access time of memory cell minimizes.

10. accumulator system, it comprises:

Memory cell array, described memory cell array is the matrix of memory cells that is organized into by row and row, in the described memory cell each all can be write inbound port and read port access by a pair of, each row of described memory cell by bit line to the reading bit line coupled in common;

Row decoder, described row decoder is coupled to each in each and the described read port of said write port centering, the child group that described row decoder is configured to receive address, memory location and child group that the said write port is right and described read port be coupled to corresponding to the bit line separately of address, described memory location to reading bit line separately;

Column decoder, described column decoder are coupled to each of said write port centering in the described memory cell array, and are configured to write described in each single memory cell columns of access in the memory cell write operation the right son group of inbound port;

The reading bit line multiplexer, described reading bit line multiplexer is coupled to the described read port of described memory cell array, and is configured to each son group of selecting corresponding to the described read port of single memory cell columns in the memory cell read operation;

Sensor amplifier, described sensor amplifier is coupled to described reading bit line multiplexer and is configured to from word-select memory unit reads data content, and described sensor amplifier further is configured to single one in the described reading bit line be carried out precharge in read operation at every turn; And

Controll block, described controll block are coupled to described row decoder, described column decoder, described reading bit line multiplexer and described sensor amplifier, and be configured to read with write operation in produce control signal.

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