CN104505114A - Double writing port latch register unit MOS (metal oxide semiconductor) circuit used for construction of storage array - Google Patents
Double writing port latch register unit MOS (metal oxide semiconductor) circuit used for construction of storage array Download PDFInfo
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- CN104505114A CN104505114A CN201410686592.7A CN201410686592A CN104505114A CN 104505114 A CN104505114 A CN 104505114A CN 201410686592 A CN201410686592 A CN 201410686592A CN 104505114 A CN104505114 A CN 104505114A
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Abstract
The invention relates to a double writing port latch register unit MOS (metal oxide semiconductor) circuit used for construction of a storage array, the double writing port latch register unit MOS circuit includes a data write-in circuit and a data readout circuit, the data write-in circuit is used for external data write in and storage; and the data readout circuit is used for storage node data readout. The double writing port latch register unit MOS circuit uses a static CMOS (complementary metal oxide semiconductor), can complete the function of two times of data write and one time of data readout without the need for an external circuit, avoids the problems of doubled logic quantity and area caused by use of the standard cell library latch register unit for construction, and avoids the problems of power consumption rising and stability reduction caused by use of a bit location priming strategy, a line or an iso-dynamic readout circuit.
Description
Technical field
The present invention relates to a kind of MOS circuit, particularly relate to and a kind ofly write a mouthful latch unit MOS circuit for building the two of storage array.
Background technology
Storage array is made up of a large amount of storage unit, and each storage unit can deposit a two-value data, usual memory cell arrangement become N capable × M column matrix formation.It is that multiple disk is formed an array, be used as single disk to use, data are stored in different disks in the mode of segmentation (striping) by it, during access data, the action together of associative disk in array, significantly lower the access time of data, have better space availability ratio simultaneously.Along with the development of integrated circuit technique and technique, also more and more higher to the requirement of storage array design, high reliability, high density, low-power consumption have become the development trend of storage array.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind ofly writes a mouthful latch unit MOS circuit for building the two of storage array, has the advantages that area is little, low in energy consumption, reliability is high.
The technical solution adopted for the present invention to solve the technical problems is: provide a kind of and write a mouthful latch unit MOS circuit for building the two of storage array, comprise data write circuit and data reading circuit, described data write circuit, for write and the storage of external data; Described data reading circuit, for the reading of memory node data.
Described data write circuit comprises the first transfer tube and the second transfer tube, described first transfer tube is connected with the first data signal end respectively with the grid of the second transfer tube, described first transfer tube is connected with the second data signal end respectively with the source electrode of the second transfer tube, and described first transfer tube is all connected with forward data memory node with the drain electrode of the second transfer tube; The drain electrode of described first transfer tube is also connected with reverse data memory node by the first phase inverter, and the drain electrode of the second transfer tube is also connected with reverse data memory node by the second phase inverter; The grid of described first transfer tube is also connected with the grid of first time trombone slide, and the source electrode of described first transfer tube is also connected with the grid of second time trombone slide; The grid of described second transfer tube is also connected with the grid of the 3rd time trombone slide, and the source electrode of described second transfer tube is also connected with the grid of the 4th time trombone slide; The source electrode of described first time trombone slide is connected with the drain electrode of second time trombone slide, and the drain electrode of described first time trombone slide is connected with reverse data memory node, the source ground of described second time trombone slide; The source electrode of described 3rd time trombone slide is connected with the drain electrode of the 4th time trombone slide, and the drain electrode of described 3rd time trombone slide is connected with reverse data memory node, the source ground of described 4th time trombone slide; Described first data signal end and the second data signal end can not effectively simultaneously.
Described data reading circuit is made up of the 3rd phase inverter, and the input end of described 3rd phase inverter is connected with reverse data memory node; Described 3rd phase inverter is made up of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor.
Beneficial effect
Owing to have employed above-mentioned technical scheme, the present invention compared with prior art, there is following advantage and good effect: the present invention uses static CMOS, complete two of data without the need to peripheral circuit to write one and read function, avoid and to cause amount of logic and the double problem of area because using standard cell lib latch (LATCH) unit to build, it also avoid because of use bit location (bitcell) preliminary filling, line or etc. dynamic sensing circuit and cause power consumption to rise, the problem of bad stability.
Accompanying drawing explanation
Fig. 1 is of the present invention pair and writes a mouthful circuit diagram for LATCH unit MOS circuit;
Fig. 2 is the circuit diagram of standard cell lib LATCH unit MOS circuit;
Fig. 3 is the circuit diagram realizing the circuit of function of the present invention with standard cell lib LATCH unit.
Embodiment
Below in conjunction with specific embodiment, set forth the present invention further.Should be understood that these embodiments are only not used in for illustration of the present invention to limit the scope of the invention.In addition should be understood that those skilled in the art can make various changes or modifications the present invention, and these equivalent form of values fall within the application's appended claims limited range equally after the content of having read the present invention's instruction.
Embodiments of the present invention relate to a kind ofly writes a mouthful latch unit MOS circuit for building the two of storage array, as shown in Figure 1, comprises data write circuit and data reading circuit, described data write circuit, for write and the storage of external data; Described data reading circuit, for the reading of memory node data.This circuit uses static CMOS, directly realizes data write read out function, can complete two of data write one and read function without the need to peripheral circuit.
Write data circuit comprises two transfer tubes, four lower trombone slides and a phase inverter pair.Wherein M0/M1 is transfer tube, M8/M9/M10/M11 is lower trombone slide, M2/M3 and M4/M5 forms phase inverter pair, concrete annexation is as follows: described data write circuit comprises the first transfer tube M0 and the second transfer tube M1, described first transfer tube M0 is connected with the first data signal end G1/G0 respectively with the grid of the second transfer tube M1, described first transfer tube M0 is connected with the second data signal end D1/D0 respectively with the source electrode of the second transfer tube M2, and described first transfer tube M0 is all connected with forward data memory node NT with the drain electrode of the second transfer tube M1; The drain electrode of described first transfer tube M0 is also connected with reverse data memory node NC by the first phase inverter (being made up of with metal-oxide-semiconductor M5 metal-oxide-semiconductor M4), and the drain electrode of the second transfer tube M1 is also connected with reverse data memory node NC by the second phase inverter (being made up of with metal-oxide-semiconductor M3 metal-oxide-semiconductor M2); The grid of described first transfer tube M0 is also connected with the grid of first time trombone slide M10, and the source electrode of described first transfer tube M0 is also connected with the grid of second time trombone slide M11; The grid of described second transfer tube M1 is also connected with the grid of the 3rd time trombone slide M8, and the source electrode of described second transfer tube M1 is also connected with the grid of the 4th time trombone slide M9; The source electrode of described first time trombone slide M10 is connected with the drain electrode of second time trombone slide M11, and the drain electrode of described first time trombone slide M10 is connected with reverse data memory node NC, the source ground of described second time trombone slide M11; The source electrode of described 3rd time trombone slide M8 is connected with the drain electrode of the 4th time trombone slide M9, and the drain electrode of described 3rd time trombone slide M8 is connected with reverse data memory node NC, the source ground of described 4th time trombone slide M9; Described first data signal end G1/G0 and the second data signal end D1/D0 can not effectively simultaneously, and two groups of signals are necessary for one-hot signal, can not effectively simultaneously.Wherein, transfer tube and drop-down pipe are used for the write of data, and when enable signal G1/G0 is 1, transfer tube conducting, data-signal D1/D0 is written to memory node.Forward data memory node NT is stored in forward data, and reverse data memory node NC is stored in reverse data.
Described data reading circuit is made up of the 3rd phase inverter (being made up of metal-oxide-semiconductor M6 and metal-oxide-semiconductor M7), the input end of described 3rd phase inverter is connected with reverse data memory node, directly can read from reverse data memory node NC, read forward data by the 3rd phase inverter.
As shown in Figure 2, this figure is standard cell lib LATCH unit MOS circuit, only comprises a write port and a read port.As shown in Figure 3, this figure is the circuit adopting standard cell lib LATCH unit to realize function of the present invention in prior art.If use standard cell lib LATCH unit to realize functional circuit of the present invention, need two cell library LATCH unit and one or logic gate, as can be seen here, its amount of logic and area all need double compared with the present invention.
Adopt bit location MOS circuit also can realize function of the present invention, but need peripheral preliminary filling, line or etc. dynamic circuit to complete the entirety read-write of array, reliability is relatively low, and amount of logic and area also can rise thereupon.
Be not difficult to find, the present invention uses static CMOS, complete two of data without the need to peripheral circuit to write one and read function, avoid and to cause amount of logic and the double problem of area because using standard cell lib latch (LATCH) unit to build, it also avoid because of use bit location (bitcell) preliminary filling, line or etc. dynamic sensing circuit and cause power consumption to rise, the problem of bad stability.
Claims (3)
1. writing a mouthful latch unit MOS circuit for building the two of storage array, comprising data write circuit and data reading circuit, it is characterized in that, described data write circuit, for write and the storage of external data; Described data reading circuit, for the reading of memory node data.
2. according to claim 1ly write a mouthful latch unit MOS circuit for building the two of storage array, it is characterized in that, described data write circuit comprises the first transfer tube (M0) and the second transfer tube (M1), described first transfer tube (M0) is connected with the first data signal end respectively with the grid of the second transfer tube (M1), described first transfer tube (M0) is connected with the second data signal end respectively with the source electrode of the second transfer tube (M1), described first transfer tube (M0) is all connected with forward data memory node (NT) with the drain electrode of the second transfer tube (M1), the drain electrode of described first transfer tube (M0) is also connected with reverse data memory node (NC) by the first phase inverter, and the drain electrode of the second transfer tube (M1) is also connected with reverse data memory node (NC) by the second phase inverter, the grid of described first transfer tube (M0) is also connected with the grid of first time trombone slide (M10), and the source electrode of described first transfer tube (M0) is also connected with the grid of second time trombone slide (M11), the grid of described second transfer tube (M1) is also connected with the grid of the 3rd time trombone slide (M8), and the source electrode of described second transfer tube (M1) is also connected with the grid of the 4th time trombone slide (M9), the source electrode of described first time trombone slide (M10) is connected with the drain electrode of second time trombone slide (M11), the drain electrode of described first time trombone slide (M11) is connected with reverse data memory node (NC), the source ground of described second time trombone slide (M11), the source electrode of described 3rd time trombone slide (M8) is connected with the drain electrode of the 4th time trombone slide (M9), the drain electrode of described 3rd time trombone slide (M8) is connected with reverse data memory node (NC), the source ground of described 4th time trombone slide (M9), described first data signal end and the second data signal end can not effectively simultaneously.
3. according to claim 1ly write a mouthful latch unit MOS circuit for building the two of storage array, it is characterized in that, described data reading circuit is made up of the 3rd phase inverter, and the input end of described 3rd phase inverter is connected with reverse data memory node; Described 3rd phase inverter is made up of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410686592.7A CN104505114A (en) | 2014-11-25 | 2014-11-25 | Double writing port latch register unit MOS (metal oxide semiconductor) circuit used for construction of storage array |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410686592.7A CN104505114A (en) | 2014-11-25 | 2014-11-25 | Double writing port latch register unit MOS (metal oxide semiconductor) circuit used for construction of storage array |
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| CN104505114A true CN104505114A (en) | 2015-04-08 |
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| CN201410686592.7A Pending CN104505114A (en) | 2014-11-25 | 2014-11-25 | Double writing port latch register unit MOS (metal oxide semiconductor) circuit used for construction of storage array |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101203919A (en) * | 2005-03-04 | 2008-06-18 | 爱特梅尔公司 | Fast read port for register file |
| CN102243888A (en) * | 2010-05-13 | 2011-11-16 | 黄效华 | Storage cell with balance load of multi-port register |
| US20130170289A1 (en) * | 2011-12-29 | 2013-07-04 | Stmicroelectronics Pvt. Ltd. | Low voltage write time enhanced sram cell and circuit extensions |
-
2014
- 2014-11-25 CN CN201410686592.7A patent/CN104505114A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101203919A (en) * | 2005-03-04 | 2008-06-18 | 爱特梅尔公司 | Fast read port for register file |
| CN102243888A (en) * | 2010-05-13 | 2011-11-16 | 黄效华 | Storage cell with balance load of multi-port register |
| US20130170289A1 (en) * | 2011-12-29 | 2013-07-04 | Stmicroelectronics Pvt. Ltd. | Low voltage write time enhanced sram cell and circuit extensions |
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