CN101202242A

CN101202242A - Technological process for making shallow ridges isolation structure

Info

Publication number: CN101202242A
Application number: CNA2006101195623A
Authority: CN
Inventors: 雷明
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-12-13
Filing date: 2006-12-13
Publication date: 2008-06-18
Anticipated expiration: 2026-12-13
Also published as: CN100524690C

Abstract

The invention discloses a processing method for producing shallow groove isolating structures, comprising following steps: the first step, a silicon substrate being put in; the second step, an initial oxide layer; the third step, the deposition of a nitride silicon layer; the forth step, the lithography of shallow grooves; the fifth step, the etching of the nitride silicon layer; the sixth step, the etching of the shallow grooves; the seventh step, the oxidation of the lateral walls of the shallow grooves; the eighth step, the filling and the deposition of the oxidation layer of the shallow grooves; the ninth step, the grinding of chemical mechanicals; the tenth step, the wet etching of the nitride silicon layer and the initial oxide layer, and the two steps of the deposition of polysilicon and the etching of the lateral wall of the polysilicon are added between the fifth and the sixth steps, on the basis of the present technological process, the invention adds the two steps of the deposition of polysilicon and the etching of the lateral wall of the polysilicon before the step of the etching of the shallow grooves, so that the method of the lateral wall of the polysilicon can be used for forming the shallow groove isolating structures, and the requirement that edge of the shallow grooves can be round in shallow groove isolating process can be satisfied, and the problem that the transistor gate oxide layer becomes thin on the edges of the shallow grooves can be solved.

Description

Make the process of shallow groove isolation structure

Technical field

The present invention relates to the semiconductor integrated circuit technique technical field, especially a kind of process of making shallow groove isolation structure of semiconductor integrated circuit technique technical field.

Background technology

In the modem semi-conductor devices manufacturing process, device isolation is an important research project.The shallow-trench isolation technology has been widely used in the following integrated circuit technology of 0.25um, and shallow groove isolation structure is compared the carrying out local oxide isolation structure, has to occupy the less advantage of silicon area, thereby has improved the integrated level of device in the unit silicon area.

But shallow grooved-isolation technique control has certain difficult point, and one of them is exactly need effectively control and take corresponding technological measure to the depth of groove at shallow slot edge.The process of the making shallow groove isolation structure of existing technology may further comprise the steps: the first step, silicon substrate input; Second step, initial oxide layer; The 3rd step, the silicon nitride layer deposit; The 4th step, the shallow slot photoetching; The 5th step, the silicon nitride layer etching; The 6th step, the shallow slot etching; The 7th step, the oxidation of shallow slot side wall; In the 8th step, the shallow trench oxidation layer is filled deposit; The 9th step, cmp; The tenth step, silicon nitride layer and initial oxide layer wet etching.

The groove that existing technology forms may cause following at least three kinds of problems: the first, and as shown in Figure 8, the transistor grid oxide layer is in the 10 places attenuation of shallow slot edge groove; The second, residual polycrystalline silicon; The 3rd, silicon nitride film is residual.If what the technology controlling and process requirement of shallow slot edge change circle was done in addition is bad, can cause causing problems such as element leakage because of the silicon crystal lattice defective that thermal stress produces.

Summary of the invention

Technical problem to be solved by this invention provides a kind of process of making shallow groove isolation structure, satisfies the requirement of change circle in shallow slot edge in the shallow grooved-isolation technique, and solves the problem of the transistor grid oxide layer of existence at the shallow slot edge thinning effectively.

For solving the problems of the technologies described above, the technical scheme that process adopted that the present invention makes shallow groove isolation structure is may further comprise the steps: at first carry out the silicon substrate input.Secondly, initial oxide layer.On initial oxide layer, carry out the silicon nitride layer deposit then.Carry out the shallow slot photoetching on this basis.Again silicon nitride layer is carried out dry etching.Carry out the polysilicon layer deposit then.And the polysilicon layer of deposit carried out the polysilicon side wall etching.Carry out the shallow slot etching again, etch shallow slot.The side wall of the shallow slot that etching is obtained carries out oxidation.Again the shallow trench oxidation layer is filled deposit.Then the shallow trench oxidation layer is carried out cmp.Adopt wet etching method that silicon nitride layer and initial oxide layer are carried out etching at last.

The present invention makes the process of shallow groove isolation structure, on the basis of existing technological process, polysilicon deposit and polysilicon side wall etching two step process before the shallow slot etch step, have been increased, utilize the method for polysilicon side wall to form shallow groove isolation structure, can satisfy the requirement of change circle in shallow slot edge in the shallow grooved-isolation technique, and solve the problem of the transistor grid oxide layer of existence effectively at the shallow slot edge thinning.

Description of drawings

The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:

Fig. 1 is the inventive method flow chart;

Fig. 2 to Fig. 7 is an embodiment of the invention schematic diagram;

Fig. 8 is existing technological effect figure.

1 is silicon substrate in the Reference numeral, and 2 is initial oxide layer, and 3 is silicon nitride layer, and 4 is polysilicon layer, and 5 is polysilicon side wall, and 6 is shallow slot, and 7 is the shallow slot edge, and 8 is shallow trench oxidation layer packed layer, and 9 is shallow slot filling oxide layer edge, and 10 is the shallow slot edge groove.

Embodiment

Please extremely shown in Figure 7 referring to Fig. 1, the present invention includes following steps: at first, carry out the silicon substrate input, form silicon substrate 1.Then, initial oxide layer on silicon substrate 1 forms initial oxide layer 2.Then above initial oxide layer 2, carry out the silicon nitride layer deposit.Carry out the shallow slot photoetching on this basis.Again silicon nitride layer is carried out etching, can adopt dry etching method that silicon nitride layer is carried out etching, obtain silicon nitride layer 3.Then carry out the deposit of polysilicon layer on silicon nitride layer 3, form polysilicon layer 4 on silicon nitride layer 3, the polysilicon layer thickness of institute's deposit is 50 dust to 800 dusts.Then polysilicon layer 4 is carried out etching, form polysilicon side wall 5, can adopt dry etching that polysilicon layer is carried out etching, and the width of the polysilicon side wall that obtains of etching is 50 dust to 800 dusts.Etching forms shallow slot 6, be the both sides, plane in the middle of the shallow slot 6 and have the gradient, and the edge of shallow slot 6 is exposed to outside the masking layer of silicon nitride layer 3.Carry out the oxidation of shallow slot side wall again, make shallow slot edge 7 become circle.Carry out the deposit of shallow trench oxidation layer packed layer 8 then.Again the shallow trench oxidation layer is carried out cmp.Adopt wet etching method that silicon nitride layer 3 and initial oxide layer 2 are carried out etching at last, the shallow slot edge has been sheltered at the shallow slot filling oxide layer edge 9 of formation.

The present invention has increased polysilicon deposit and polysilicon side wall etching two step process before the shallow slot etch step on the basis of existing technological process, utilize the method for polysilicon side wall to form shallow groove isolation structure.The present invention can satisfy the requirement of change circle in shallow slot edge in the shallow grooved-isolation technique, reduces the silicon crystal lattice defective that produces because of thermal stress and causes problems such as element leakage.The present invention has simultaneously solved the transistor grid oxide layer that exists effectively in problems such as shallow slot edge thinning, residual polycrystalline silicon and silicon nitride film are residual, can improve performance of semiconductor device.

Claims

1. process of making shallow groove isolation structure may further comprise the steps:

The first step, the silicon substrate input;

Second step, initial oxide layer;

The 3rd step, the silicon nitride layer deposit;

The 4th step, the shallow slot photoetching;

The 5th step, the silicon nitride layer dry etching;

The 6th step, the shallow slot etching;

The 7th step, the oxidation of shallow slot side wall;

In the 8th step, the shallow trench oxidation layer is filled deposit;

The 9th step, the mechanical lapping of shallow trench oxidation stratification;

The tenth step, silicon nitride layer and initial oxide layer wet etching,

It is characterized in that, between the 5th step and the 6th step, add two steps successively: the polysilicon layer deposit; The polysilicon side wall etching.

2., the process as right 1 described making shallow groove isolation structure is characterized in that, the shallow slot that etching forms in described the 6th step is the shallow slot that the both sides, plane have the gradient for middle, and the edge of shallow slot is exposed to outside the masking layer of silicon nitride layer.

3. as the process of right 1 described making shallow groove isolation structure, it is characterized in that the thickness of polysilicon layer is 50 dust to 800 dusts in the polysilicon layer depositing step.

4. as the process of right 1 described making shallow groove isolation structure, it is characterized in that, adopt dry etching method to etch polysilicon side wall in the polysilicon side wall etch step.

5. as the process of right 1 or 4 described making shallow groove isolation structures, it is characterized in that lateral wall width is 50 dust to 800 dusts in the polysilicon side wall etch step.