CN101192568A - Integrate circuit 'metal-insulator-metal' capacitor structure and its manufacture method - Google Patents
Integrate circuit 'metal-insulator-metal' capacitor structure and its manufacture method Download PDFInfo
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Abstract
The invention relates to a capacitor structure of 'metal-insulator-metal' in an integrated circuit, and a manufacturing method thereof. The structure from the bottom to the top includes bottom electrode metal, an MIM insulation medium, top electrode metal, an insulation medium and upper layer interconnection metal and is characterized in that: a lower layer interconnection metal is arranged below the bottom electrode metal; the bottom electrode metal is assigned in the shape of grid or strip, the side surface of the bottom electrode metal is lined with a lateral-wall metal layer and the upper side surface of the lateral-wall metal layer smoothly transits to an upper surface of the bottom electrode metal through an arc surface; and the top electrode metal covers all the bottom electrodes from the top to the bottom and the MIM insulation medium with consistent thickness is uniformly filled between the top electrodes and the bottom electrodes. By adopting the invention, about more than half of an occupied area on a chip of an MIM capacitor is saved and two technical issues of edge leakage and decrease of break-down voltage caused by edge acumination of the lateral-wall horizontal plane of the bottom electrodes are effectively solved.
Description
Technical field
The present invention relates to the capacitor arrangement in the large scale integrated circuit, relate in particular to the capacitor of a kind of " metal-insulator-metal type " configuration and the manufacture method of this capacitor, belong to integrated circuit (IC) chip and make processing technique field.
Background technology
The capacitor of " metal one insulator one metal " (Metal-Insulator-Metal, abbreviation MIM) configuration is the device commonly used of large scale integrated circuit, particularly is used in the RFCMOS integrated circuit.
MIM capacitor has multiple configuration, parallel-plate " metal one insulator one metal " capacitor is the most common a kind of, as U.S. Pat 6342734, US5406447, US6894364, US6940114, and document such as Chinese patent CN200310102992, CN200410100720, CN200310122877 discloses.Fig. 1 a is the basic structure of parallel-plate MIM capacitor in the integrated circuit, it only has " metal one insulator one metal " single layer structure, and a plurality of through holes 104～109 of etching in the dielectric material between capacitor two metal electrode boards and upper layer interconnects metal level, so that draw two electrodes of capacitor.Its processing procedure is: deposition includes the three-decker of bottom metal layers 101, insulator layer 102 and intermediate metal layer 103 respectively, then with little shadow of tradition and etching technique, this intermediate metal layer 103 of etching and insulator 102 are made pattern, wherein also can only partially-etched this insulating barrier 102; Then, again with little shadow of tradition and etching technique, this bottom metal layers 101 of etching is to make pattern; Subsequently, deposit an inter-metal medium material 111 again and carry out cmp (CMP), subsequently, in this intermetallic dielectric material 111, a plurality of through holes 104～109 of etching; At last, deposit and make pattern, to form respectively via metal interconnecting 104,105,106,107,108 and 109 and the metal layer at top 110 that connects of bottom metal layers 101 and intermediate metal layer 103.
Along with the progress of integrated circuit technique, integrated level is improving constantly, and chip area constantly dwindles, and requires " metal one insulator one metal " capacitor chip area occupied to reduce.For guaranteeing the required capacitance of circuit design, the approach that reduces the capacitor chip area occupied has three: the one, with intermetallic dielectric thickness attenuate; The 2nd, the material of employing high-k (k), for example Ta
2O
5The 3rd, the structure of capacitor is improved innovation.Yet, intermetallic dielectric thickness attenuate requires the capacitor top electrode metal etch can not cross etching MIM medium, this is because the capacitor edge electric field strength is higher, if it is more to cross etching MIM medium during the etching top electrode, leakage current passes the metal spacer medium than MIM mass of medium difference easily, also can cause the resistance to sparking of capacitor to descend.Adopt high-k Ta
2O
5Method need to increase: the processing procedure time that extra deposition tool, the insulation making step of avoiding cross pollution and new material are integrated and personnel's investment, and the introducing of high dielectric constant material cause the problem of Leakage Current density easily.Therefore, the industrial applications of these two approach has bigger limitation.
As for the 3rd approach; retrieve according to the applicant; representativeness report about the MIM capacitor architecture advances has at present: the method that US6977198 and CN200310122877 adopt parallel plate capacitor to pile up increases capacitance; US6423996 and US6717193 (or CN02820001) propose to utilize the metal side wall to increase the method for electric capacity; US6069051 good medium of first deposit performance before the depositing metal spacer medium is protected the edge, but respectively pluses and minuses is arranged.
The advantage of the method that US6977198 employing parallel plate capacitor piles up is, capacitance can increase and is twice on chip area much at one, but there are three shortcomings: 1. must increase one deck mask blank, 2. also increased by a track media on the manufacturing step with metal deposit and photoetching and metal etch, 3. the capacitor edge length doubles, and the potential electric leakage in edge increases the weight of.CN200310122877 is made in the US6977198 parallel-plate structure on two layers or multilayer interconnecting metal, and then in parallel, has three above-mentioned shortcomings too.
US6717193 (or CN02820001) makes finger-shaped or pectination (Finger) with top electrode metal and bottom electrode metal, utilizes bottom electrode metal side wall and side-wall electrode metal 112 to constitute the sidewall MIM capacitor to increase capacitance, shown in Fig. 1 b.Its advantage is Finger of every increase, just increases by two sidewall capacitors, as long as distance is less than half of bottom electrode height between the Finger, total capacitance will increase; Shortcoming is: 1. edge length increases along with the Finger number and increases considerably, the potential leaky in edge increases the weight of, 2. because upper/lower electrode all is the Finger shape, lithography alignment requires the Finger width can not be too narrow, can not etch maximum bottom electrode grooves and obtain maximum sidewall capacitance in certain area.
The US6423996 patent is also mentioned and is utilized the metal side wall to increase electric capacity, shown in Fig. 1 c, but shortcoming is the horizontal plane edge too sharp-pointed (Sharp) of the bottom electrode sidewall after the PROCESS FOR TREATMENT, causes that easily electric field concentrates and point discharge, and capacitor breakdown voltage descends; And the applicant does not propose how at utmost to utilize sidewall capacitance.
Summary of the invention
First purpose of the present invention provides " metal-insulator-metal type " capacitor arrangement in a kind of integrated circuit, the chip area footprints that is intended to save capacitor, and effectively solve capacitor edge current leakage and two technical barriers of point discharge.
Second purpose of the present invention provides the manufacture method of above-mentioned " metal-insulator-metal type " capacitor arrangement.
For realizing first purpose of the present invention, " metal-insulator-metal type " capacitor arrangement in a kind of integrated circuit, comprise the bottom electrode metal from bottom to top successively, top electrode metal and upper layer interconnects metal, between bottom electrode metal and the top electrode metal, and between top electrode metal and the upper layer interconnects metal, all be filled with dielectric, between bottom electrode metal and the upper layer interconnects metal, and between top electrode metal and the upper layer interconnects metal, realize being electrically connected by the last through hole of correspondence, make bottom electrode metal and top electrode metal on the upper layer interconnects metal, form the corresponding electrode exit respectively, it is characterized in that: described bottom electrode metal is latticed and/or strip is arranged, the side surface of its vertical direction is lined with the side-wall metallic layer, this side-wall metallic layer and bottom electrode metal constitute the bottom electrode of capacitor jointly, and, seamlessly transit with arc surface between the upper surface of the upper end of the side surface of described side-wall metallic layer and bottom electrode metal; Correspondingly, the top electrode metal covers bottom electrode from top to bottom, inside, gap between the side surface of the upper surface of the lower surface of top electrode metal and side surface and bottom electrode metal and side-wall metallic layer evenly is filled with dielectric, and the thickness of this dielectric is more well-balanced unanimity on all directions.
Further, " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, the height of described side-wall metallic layer in the vertical direction is more than or equal to the vertical thickness of bottom electrode metal.
Further, " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, below the bottom electrode metal, be provided with the lower interconnection metal, also be filled with insulating medium layer between bottom electrode metal and the lower interconnection metal, inside at this insulating medium layer is provided with lower through-hole, realizes being electrically connected by this lower through-hole between bottom electrode metal and the lower interconnection metal.
Further, " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, described side-wall metallic layer is Ti (50～150A)/TiN (50～300A) metal composite layers, or the Ti of 100～300A or TiN or Ta or TaN or Ta/TaN metal level.
Further, " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, the dielectric of evenly filling between the inner surface of described bottom electrode and top electrode metal is SiO
2, SixNy, SiOxNy, HfO
2, ZrO
2, Al
2O
3, Ta
2O
5Or SiO
2/ SixNy compound medium layer.
Further, " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, described bottom electrode metal is the layer interconnecting metal second from the bottom of integrated circuit, the vertical thickness of bottom electrode metal is 3～7 μ m, and its material is Al, or the Ti/TiN-Al-Ti/TiN complex metal layer, the thickness of Ti is 50～150A in the described complex metal layer, and the thickness of TiN is 50～300A.
Again further, " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, described top electrode metal is that thickness is the Ti of 300～4000A or the composite bed of TiN or Ti/TiN composite bed or Ti/TiN and W or Al.
For realizing second purpose of the present invention, the manufacture method of " metal-insulator-metal type " capacitor arrangement in the integrated circuit, comprise dielectric between MIM medium, top electrode metal and the upper layer interconnects metal between bottom electrode metal, top electrode metal, upper layer interconnects metal, bottom electrode metal and the top electrode metal and the operation that is provided with that goes up through hole, it is characterized in that: at first, after the deposit of bottom electrode metal, according to the illumination domain to its etching, constitute the bottom electrode metal of latticed and/or strip, make it to increase the side surface of vertical direction; The upper surface of the bottom electrode after etching and side surface deposit the skim metal then, after this sheet metal deposit is finished, adopt reactive ion anisotropy method that it is eat-back, make this sheet metal form the side-wall metallic layer in the vertical side of bottom electrode metal, should be integrated by newly-increased side-wall metallic layer and bottom electrode metal, the common bottom electrode that constitutes capacitor, and, seamlessly transit with arc surface between the upper surface of the upper end of the side surface of side-wall metallic layer and bottom electrode metal; Follow deposit MIM medium and top electrode metal again, process etch processes after the deposit of top electrode metal, and then deposit one deck dielectric, the surface of this dielectric is through the metal of deposit upper layer interconnects again after the smooth processing; Adopt general through hole of integrated circuit industry and craft of metal dealing at last, draw two electrodes up and down of capacitor with capacitor upper layer interconnects metal and last through hole.
Further, the manufacture method of " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, after described bottom electrode metal is etched, increase a step bottom electrode metal below next-door neighbour dielectric etching vertically again, the surface deposition of bottom electrode metal after etching and dielectric and eat-back sheet metal then makes the height of the side-wall metallic layer in the vertical direction that form greater than the vertical thickness of bottom electrode metal.
One go on foot ground again, the manufacture method of " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein, before deposit bottom electrode metal, set in advance the dielectric between lower interconnection metal and lower interconnection metal and the bottom electrode, and lower through-hole is set, and then deposit bottom electrode metal level in this dielectric layer inside.
Further, the manufacture method of " metal-insulator-metal type " capacitor arrangement in the above-mentioned integrated circuit, wherein:
Chemical gas-phase deposition method is adopted in the deposit of described sidewall sheet metal, perhaps adopts organic metal oxide chemistry gas-phase deposition method, perhaps adopts the atomic layer chemical vapour deposition method;
Described MIM dielectric layer is the SiO that adopts the plasma-reinforced chemical vapor deposition method to form
2, SixNy, SiOxNy or SiO
2/ SixNy compound medium layer, or the HfO that adopts the atomic layer chemical vapour deposition method to form
2, ZrO
2, Al
2O
3, Ta
2O
5Deng dielectric layer of high dielectric constant;
Chemical gas-phase deposition method is adopted in the deposit of described top electrode metal, perhaps adopts organic metal oxide chemistry gas-phase deposition method, perhaps adopts the physical vapor deposition method.
Outstanding substantive distinguishing features of the present invention and marked improvement are mainly reflected in:
(1) the present invention is from improving the integrated circuit chip area utilance, utilize metal sidewall to increase the effective capacitance surface density value of MIM configuration capacitor, be designed to latticed bottom electrode or strip, bottom electrode metal live width and distance size are as far as possible little in the design rule scope, make can obtain maximum metal sidewall utilance under certain design area;
(2) in the process treatment process of the present invention, after to the bottom electrode metal etch, can further increase medium between bottom electrode metal and the lower interconnection metal in the etching of vertical direction, finish above-mentioned steps and carry out the sheet metal deposition later on again one time, the metal that is deposited can be Ti, TiN, Ta metal level, or Ta/TaN, Ti/TiN composite bed, thereby in the newly-increased one deck side wall layer of the sidewall of bottom electrode metal.Should newly-increased side wall layer pass through etch-back process again, the junction of the upper end of its vertical plane and bottom electrode metal is processed to be very smooth fillet surface, like this, it is over half not only to make the chip area footprints of capacitor save, and efficiently solves bottom electrode sidewall horizontal face edge and sharply easily cause dielectric breakdown voltage to reduce problem;
(3) bottom electrode of MIM capacitor of the present invention adopts the lower interconnection metal level to draw, the top electrode of capacitor covers all bottom electrodes, because two distance between electrodes have overcome the shortcoming of existing in prior technology capacitor edge current leakage greater than traditional parallel-plate structure about near this structure capacitive device edge.
Description of drawings
Fig. 1 a, 1b, 1c are the cross-section structures of three kinds of MIM capacitor of prior art;
Fig. 2 a is a kind of light shield domain schematic diagram of the present invention;
Fig. 2 b is an another kind of light shield domain schematic diagram of the present invention;
Fig. 2 c is latticed bottom electrode layout;
Fig. 2 d is a strip bottom electrode layout;
Fig. 2 e is through the style shape bottom electrode pattern after the PROCESS FOR TREATMENT;
Fig. 2 f is through the strip bottom electrode pattern after the PROCESS FOR TREATMENT;
Fig. 3 is a kind of cross-section structure of MIM capacitor of the present invention;
Fig. 4 is the another kind of cross-section structure of MIM capacitor of the present invention;
Fig. 5 is the side-wall metallic of MIM capacitor of the present invention and the partial structurtes schematic diagram of horizontal plane metal corner junction;
Fig. 6 a～Fig. 6 g is the main manufacture process schematic diagram of MIM capacitor cross-section structure shown in Figure 4.
More than the implication of Reference numeral in the middle of each figure be:
101-bottom electrode metal, 102-insulator, 103-top electrode metal, 104～109-through hole, 110-upper layer interconnects metal, 111-dielectric material, 112-side-wall electrode metal;
X01-lower interconnection metal, the x02-lower through-hole, x02a-connects the lower through-hole of lower interconnection metal and bottom electrode, x02b-connects the lower through-hole of lower interconnection metal and bottom electrode interconnecting metal, x03a-bottom electrode metal, x03b-bottom electrode interconnecting metal, x04-top electrode metal, the last through hole of x05-, x05a-connects the last through hole of upper layer interconnects metal and top electrode metal, and x05b-connects the last through hole of upper layer interconnects metal and bottom electrode interconnecting metal, x06-upper layer interconnects metal, x06a-top electrode metal is at the exit of upper layer interconnects metal, and x06b-bottom electrode metal is at the exit of upper layer interconnects metal, and x is 2 or 3 in the above Reference numeral;
Upper epidermis metal when 303c-bottom electrode metal adopts composition metal, following top layer metal when 303d-bottom electrode metal adopts composition metal, medium between 307-lower interconnection metal and the bottom electrode metal, 308-bottom electrode side-wall metallic layer, the 309-MIM medium, the medium between 310-top electrode metal and the upper layer interconnects metal.
The main terminological interpretation of this paper is as follows:
MIM medium: refer to the medium between the MIM capacitor upper/lower electrode;
Bottom electrode metal: refer to the metal level that MIM medium lower electrodes is used;
The bottom electrode interconnecting metal: be the interconnection line in the integrated circuit, the upper and lower electrode metal of technology is together One deck, but keep apart with the capacitor lower electrode metal after the etching, in the capacitor of the present invention with lower through-hole, Upper through hole, upper layer interconnects metal and lower interconnection metal connect, and draw capacitor lower electrode;
Top electrode metal: refer to the metal level that MIM medium overlying electrode is used;
Lower interconnection metal: the interconnecting metal that refers to the nearest one deck below the bottom electrode;
Lower through-hole: refer to connect lower interconnection metal and bottom electrode metal or lower interconnection metal and lower The through hole of electrode interconnection metal;
Upper layer interconnects metal: the interconnecting metal that refers to the nearest one deck above the top electrode;
Upper through hole: refer to connect upper layer interconnects metal and top electrode metal or upper layer interconnects metal and lower The through hole of electrode interconnection metal.
Embodiment
More fully describe technical solution of the present invention hereinafter with reference to accompanying drawing, wherein show exemplary embodiments of the present invention.But the present invention can implement with many different modes, and the embodiment that should not be regarded as being limited to here to be proposed.On the contrary, provide these embodiment can make technical solution of the present invention more thoroughly, more comprehensively open, and will pass on protection scope of the present invention to those skilled in the art fully.In the accompanying drawings, for clarity, relevant size and dimension may be carried out amplification.
Shown in Fig. 2 a～Fig. 2 f, the present invention is designed to latticed (Fig. 2 a, 2c, 2e) or strip (Fig. 2 b, 2d, 2f) with capacitor lower electrode 203a, the live width of bottom electrode metal 203a and distance size are as far as possible little within the design rule scope, so that can obtain maximum sidewall utilance under certain design area.Bottom electrode 203a is connected with lower interconnection metal 201 by lower through-hole 202a, and lower interconnection metal 201 is drawn from upper layer interconnects metal 206b through corresponding interconnected metal 203b of lower through-hole 202b, bottom electrode and last through hole 205b again.Correspondingly, top electrode metal 204 is directed to upper layer interconnects metal 206a by the last through hole 205a of correspondence.As can be seen from the figure, top electrode 204 of the present invention covers all bottom electrode metal 203a, and this is the shortcoming for the capacitor edge current leakage of great majority invention existence before can overcoming.
Fig. 3, Fig. 4 are two kinds of cross-section structures of MIM capacitor of the present invention.Among Fig. 3, be successively from bottom to top: medium 310, upper layer interconnects metal 306 between the medium 307 between lower interconnection metal 301, lower interconnection metal and the bottom electrode metal, bottom electrode metal 303a and bottom electrode interconnecting metal 303b, top electrode metal 304, top electrode metal and the upper layer interconnects metal.Be provided with lower through-hole 302a in medium 307 inside, be used for being electrically connected between lower interconnection metal 301 and the bottom electrode metal 303a.And be provided with through hole 305a in medium 310 inside, and be used for being electrically connected between top electrode metal 304 and the upper layer interconnects metal 306a, form the exit 306a of top electrode metal at the upper layer interconnects metal; Simultaneously, medium 310 and medium 307 inside also be respectively equipped with special on through hole 305b and lower through-hole 302a/302b, by bottom electrode interconnecting metal 303b and lower interconnection metal 301 bottom electrode 303a is caused upper layer interconnects metal 306b.It is side-wall metallic layers 308 that bottom electrode 303a has two sides, evenly is filled with MIM medium 309 between the upper surface of the surface of side-wall metallic layer 308 and bottom electrode 303a and the top electrode metal 304.Structure and Fig. 3 of Fig. 4 are similar, and difference is that side-wall metallic layer 308 vertically extends downwards, and part enters 307 dielectric layers, and its thickness has surpassed the thickness of bottom electrode metal 303a.The common feature of Fig. 3 and Fig. 4 is, is between the upper end of surperficial smoother, especially this side surface of side-wall metallic layer 308 and the upper surface of bottom electrode to seamlessly transit, as shown in Figure 5.
Be example to form Fig. 4 structure below, its main technique treatment step is described in detail in detail.
Shown in Fig. 6 a～6g, after the manufacturing process of MIM capacitor is carried out semiconductor device and through hole and interconnection below the following interconnecting metal layer from the surface of semiconductor (perhaps epitaxial semiconductor on other material).At first, carry out down interconnecting metal 301 and interconnect dielectric layer 307 between the metal level 303 of usefulness of interconnecting metal and bottom electrode and bottom electrode down according to the conventional cmos processing step, in dielectric layer 307 inside lower through-hole 302 is set, then deposit bottom electrode and bottom electrode the interconnection usefulness metal level 303, shown in Fig. 6 a.Usually, metal level 303 is the layer interconnecting metal second from the bottom of CMOS integrated circuit often, and this layer metal is generally Al or Ti/TiN-Al-Ti/TiN complex metal layer, and the gross thickness of metal level is 3～7 μ m, and Ti thickness is 50～150A (dust, 10
-8Centimetre), TiN thickness is 50～300A, what illustrate among the figure is the Ti/TiN-Al-Ti/TiN complex metal layer.
Then, form bottom electrode metal 303a and bottom electrode interconnecting metal 303b according to the etch metal layers of light shield domain shown in Fig. 2 a or the 2b 303.Increase by step medium 307 etching vertically then, for example adopt reactive ion anisotropy method, should make the thickness H of medium 307 of lower interconnection metal 301 tops in principle greater than 500A.This step process is an options, if etching media 307 not will form mim structure shown in Figure 3.Finish after above-mentioned two etching processes, cross sectional shape is shown in Fig. 6 b.
On the basis of Fig. 6 b, at the surface deposition skim metal 308 of bottom electrode 303a and bottom electrode interconnecting metal 303b and medium 307, shown in Fig. 6 c.This newly-increased one deck metal level 308 can be Ti (50～150A)/TiN (50～300A) metal composite layers, also can be Ti or TIN or Ta or TaN or the Ta/TaN layer of 100～300A, its deposition process adopts the good chemical gas-phase deposition method (CVD) of step coverage energy, perhaps organic metal oxide chemistry gas-phase deposition method (MOCVD) and atomic layer chemical vapour deposition method (ALCVD).
Adopt reactive ion anisotropy method to eat-back the sheet metal 308 of (etchback) front deposit, between with bottom electrode metal 303a and bottom electrode interconnecting metal 303b, between the bottom electrode metal 303a, the Ti/TiN etching between the bottom electrode interconnecting metal 303b and capacitor lower electrode 303a top is clean, shown in Fig. 6 d.After this step process processing, newly-increased metal level 308 is integrated with bottom electrode metal 303a, formation has the bottom electrode of two sidewalls, and, it is very smooth that the top edge of its side wall layer 308 becomes, and Ti/TiN metal level 303c on the side about Al and the Al and the interface of 303d also obtain smooth reparation.Deposit MIM medium 309 can make thickness more even, shown in Fig. 5 and 6e on this basis.By contrast, if do not adopt the deposit sheet metal to add etch back process the bottom electrode edge is not carried out smooth treatment (as background technology US642399), capacitor is when deposit MIM medium, the dielectric thickness at edge is inhomogeneous, and the bottom electrode metal edge is very sharp-pointed, the two or any factor among both can cause that all edge electric field strength increases, and have increased the electric leakage of capacitor, have reduced the resistance to sparking energy of capacitor.The present invention carries out the bottom electrode edge after the smooth treatment, and the thickness of MIM dielectric deposition is more even, and power line also disperses, and near the electric field strength the edge reduces, and the anti-breakdown characteristics of capacitor is effectively improved.
Fig. 6 c, 6d, 6e are the keys of manufacturing technology among the present invention, and it has increased side-wall metallic layer 308 newly, and have formed smooth bottom electrode metal side.If medium 307 is etched, the bottom electrode sidewall area will further be increased, and promptly capacitance obtains to increase.When deposit MIM medium 309, can adopt plasma-reinforced chemical vapor deposition method (PECVD) to form SiO
2, SixNy, SiOxNy or SiO
2/ SixNy compound medium layer also can adopt atomic layer chemical vapour deposition method (ALCVD) to form HfO
2, ZrO
2, Al
2O
3, Ta
2O
5Deng high dielectric constant.
Next carry out the deposit of capacitor top electrode metal 304 again, shown in Fig. 6 f.It is fixed that the thickness of top electrode metal 304 is selected to come according to the minimum range of gap between the capacitor lower electrode and bottom electrode interconnecting metal.Be less clearance before top electrode metal 304 fills up in principle, and it is enough big to guarantee to stay behind the top electrode metal etch space of silicon chip surface, so that it is full to allow thereafter medium 310 fill, shown in Fig. 6 g.Perhaps select thin top electrode metal 304, make after its deposit bigger in the gap that silicon chip surface stays so that the medium 310 after guaranteeing can be with gapped filling up.The thickness of top electrode metal 304 is generally 300～4000A, and material can be selected Ti, TiN or Ti/TiN composite bed for use when thin, can use the composite bed of Ti/TiN and W or Al when thicker.Deposition process adopts chemical gas-phase deposition method (CVD) or adopts organic metal oxide chemistry gas-phase deposition method (MOCVD), for Al material available physical vapour deposition (PVD).
After 304 deposits of top electrode metal are finished through etch processes, and then the dielectric 310 between deposit top electrode 304 and the upper layer interconnects metal 306, and the surface of medium 310 is carried out smooth, shown in Fig. 6 g.Can adopt good high-density plasma CVD (Chemical Vapor Deposition) method (HDPCVD) of fillibility or plasma-reinforced chemical vapor deposition method (PECVD) deposit SiO during operation
2, SiOxFy or medium with low dielectric constant deposit 310 dielectric layers such as Core, Blank-diamond, use chemical mechanical polishing method (CMP) flat surface then; Perhaps with revolving figure method (spin-on) deposit SiO
2Or medium with low dielectric constant such as Silk, with as dielectric 310.
At last, adopt general through hole and the smithcraft of IC, two electrodes up and down with capacitor upper layer interconnects metal 306 and last through hole 305a and 305b draw capacitor form cross-section structure shown in Figure 4.The IC common processes is also adopted in other passivation layer and PAD perforate, and this paper does not give unnecessary details.
Shown in as indicated above and Fig. 6 b, when the medium between metal level 303 and the lower interconnection metal 301 307 was carried out the etching of vertical direction, the dielectric thickness of lower interconnection metal 301 tops should be greater than 500A.This step etching has increased sidewall area and sidewall capacitance, and keeping certain thickness is for the suppression capacitor edge current leakage.It is estimated (seeing for details hereinafter), for 0.15～0.35 μ m CMOS technology, the medium etching of every increase 3000A thickness can make the effective capacitance surface density increase by 0.5～1 times.This step improvement project is an options, the structure when not selecting as shown in Figure 3, when for example 0.18 μ mCMOS technology was not selected the improvement of this step process, the effective capacitance surface density of capacitor also was twice above than increasing of parallel-plate structure, can increase more than 1.5 times after the selection.But, selecting this step process one is that the later inter-metal medium deposit fillibility of requirement is good; The 2nd, distance increases between bottom electrode side-wall metallic and the lower interconnection metal.Certainly, also can not increase extra mask blank and etching, only increase the etching of MIM zone medium 307.
The bottom electrode of MIM capacitor of the present invention adopts the lower interconnection metal level to draw, the top electrode of capacitor covers all bottom electrodes, the upper/lower electrode Edge Distance is thickness and the MIM medium sum that the medium etching of bottom electrode below stays, and does not exist the described MIM capacitor of background technology to be subjected to the shortcoming of edge current leakage restriction.Turn back to analyze US6717193, its Finger structure capacitive device has also increased the capacitor edge length when increasing sidewall capacitance, Finger of every increase or two side electric capacity, the capacitor edge length increases by four times of finger length altogether, and potential edge current leakage is comparatively serious.In other words, cross etching when adopting the structure of US6717193 must increase the MIM dielectric thickness and reduce the top electrode etching, could guarantee capacitor resistance to sparking can and low electric leakage, relatively contradiction is, increase MIM thickness must will reduce capacitance again.This contrast further shows, the MIM thickness limits problem that technical solution of the present invention has solved the potential electric leakage problem in capacitor edge well and brought.
In addition, the bottom electrode lithography layout of MIM capacitor of the present invention is designed to latticed or strip, and bottom electrode metal live width and distance size are as far as possible little in the design rule scope, so that can obtain maximum sidewalls under certain design area.If do not select medium etching after the bottom electrode etching on the technology for use, the big I of bottom electrode metal live width and distance designs according to the design rule minimum value.If for selecting medium etching after the bottom electrode etching on more increase effective capacitance density technologies for use, the bottom electrode metal distance can design according to the design rule minimum value so, live width then should be slightly larger than the lower through-hole size, so that the bottom electrode metal covers lower through-hole after guaranteeing PROCESS FOR TREATMENT.By contrast, the upper/lower electrode of US6717193 structure is all used the Finger shape, and lithography alignment requirement Finger width can not be too narrow, that is to say that can not dig out maximum bottom electrode grooves in certain area obtains maximum sidewall capacitance.
During concrete enforcement, the limit of the vertical direction of metal sidewall generally can the form right angle shape in the technical process of the present invention, all be usually become circular-arc, shown in Fig. 2 e, 2f.Deposit MIM medium can be more even on this basis, guaranteed that MIM capacitor has anti-preferably breakdown capability.If circular shape is undesirable, can optimize the etching shape by regulating methods such as bottom electrode metal etching process or adjusting bottom electrode light shield domain OPC treatment process, to guarantee that having good resistance to sparking can obtain maximum sidewall capacitance under the prerequisite.Can regulate etch process when in addition, etching forms the bottom electrode metal makes and helps bottom electrode metal slight inclination (cross section is shape in echelon) the present invention and specifically implement.
Below the increase multiple of MIM capacitor capacitance of the present invention is estimated---
Capacitor of the present invention is compared with the plane-parallel capacitor that is produced on planarization surface, has comprised the sidewall capacitance that metal sidewall causes, electric capacity significant surface density is improved.The metal live width of hypothetical trellis shape bottom electrode is w, and distance is s between the metal, and metal thickness is h, and then the ratio a of the capacitance of capacitor of the present invention and parallel-plate is:
When electrode design was latticed shown in Fig. 2 c in fact instantly, square space can become the shape shown in the 2e after the PROCESS FOR TREATMENT, and promptly four right angles can become arcuation, and sidewall area is littler than above-mentioned formula result of calculation like this.Suppose when the most serious that for circular, above-mentioned formula will become:
Similarly, if bottom electrode adopts strip, the capacitance of capacitor and the ratio of parallel-plate are:
For 0.15～0.35 μ m aluminium interconnection process, general second from the bottom layer metal thickness h is 1.5～2 times of its minimum design rule size, and w and s are more little, above a value of three kinds of situations just big more.When w=s=minimum design rule size, a value is maximum.When table 1 calculates one group of CMOS technology that adopts typical case 0.15～0.35 μ m and design rule, capacitor of the present invention and capacity of parallel plate capacitor ratio.When being designed to when latticed, actual value should be between square net and circular grid value corresponding; When adopting strip, also between between the two.By table 1 as seen, for 0.15～0.35 μ m technology, capacitor area occupied of the present invention can be saved over half than parallel-plate structure capacitor, the highest area of economizing about 75%.
Claims (13)
1. " metal-insulator-metal type " capacitor arrangement in the integrated circuit, comprise the bottom electrode metal from bottom to top successively, top electrode metal and upper layer interconnects metal, between bottom electrode metal and the top electrode metal, and between top electrode metal and the upper layer interconnects metal, all be filled with dielectric, between bottom electrode metal and the upper layer interconnects metal, and between top electrode metal and the upper layer interconnects metal, realize being electrically connected by the last through hole of correspondence, make bottom electrode metal and top electrode metal on the upper layer interconnects metal, form the corresponding electrode exit respectively, it is characterized in that: described bottom electrode metal is latticed and/or strip is arranged, the side surface of its vertical direction is lined with the side-wall metallic layer, this side-wall metallic layer and bottom electrode metal constitute the bottom electrode of capacitor jointly, and, seamlessly transit with arc surface between the upper surface of the upper end of the side surface of described side-wall metallic layer and bottom electrode metal; Correspondingly, the top electrode metal covers bottom electrode from top to bottom, inside, gap between the side surface of the upper surface of the lower surface of top electrode metal and side surface and bottom electrode metal and side-wall metallic layer evenly is filled with dielectric, and the thickness of this dielectric is well-balanced unanimity on all directions.
2. " metal-insulator-metal type " capacitor arrangement in the integrated circuit according to claim 1 is characterized in that: the height of described side-wall metallic layer in the vertical direction is more than or equal to the vertical thickness of bottom electrode metal.
3. " metal-insulator-metal type " capacitor arrangement in the integrated circuit according to claim 1, it is characterized in that: below the bottom electrode metal, be provided with the lower interconnection metal, also be filled with insulating medium layer between bottom electrode metal and the lower interconnection metal, inside at this insulating medium layer is provided with lower through-hole, realizes being electrically connected by this lower through-hole between bottom electrode metal and the lower interconnection metal.
4. according to " metal-insulator-metal type " capacitor arrangement in claim 1 or the 2 or 3 described integrated circuits, it is characterized in that: described side-wall metallic layer is Ti (50～150A)/TiN (50～300A) metal composite layers, or the Ti of 100～300A or TiN or Ta or TaN or Ta/TaN metal level.
5. according to " metal-insulator-metal type " capacitor arrangement in claim 1 or the 2 or 3 described integrated circuits, it is characterized in that: the dielectric of evenly filling between the inner surface of described bottom electrode and top electrode metal is SiO
2, SixNy, SiOxNy, HfO
2, ZrO
2, Al
2O
3, Ta
2O
5Or SiO
2/ SixNy compound medium layer.
6. according to " metal-insulator-metal type " capacitor arrangement in claim 1 or the 2 or 3 described integrated circuits, it is characterized in that: described bottom electrode metal is the layer interconnecting metal second from the bottom of integrated circuit, the vertical thickness of bottom electrode metal is 3～7 μ m, its material is Al, or Ti/TiN-Al-Ti/TiN complex metal layer, the thickness of Ti is 50～150A in the described complex metal layer, and the thickness of TiN is 50～300A.
7. according to " metal-insulator-metal type " capacitor arrangement in claim 1 or the 2 or 3 described integrated circuits, it is characterized in that: described top electrode metal is that thickness is the Ti of 300～4000A or the composite bed of TiN or Ti/TiN composite bed or Ti/TiN and W or Al.
8. the manufacture method of " metal-insulator-metal type " capacitor arrangement in the integrated circuit, comprise dielectric between MIM medium, top electrode metal and the upper layer interconnects metal between bottom electrode metal, top electrode metal, upper layer interconnects metal, bottom electrode metal and the top electrode metal and the operation that is provided with that goes up through hole, it is characterized in that: at first, after the deposit of bottom electrode metal, according to the illumination domain to its etching, constitute the bottom electrode metal of latticed and/or strip, make it to increase the side surface of vertical direction; The upper surface of the bottom electrode after etching and side surface deposit the skim metal then, after this sheet metal deposit is finished, adopt reactive ion anisotropy method that it is eat-back, make this sheet metal form the side-wall metallic layer in the vertical side of bottom electrode metal, should be integrated by newly-increased side-wall metallic layer and bottom electrode metal, the common bottom electrode that constitutes capacitor, and, seamlessly transit with arc surface between the upper surface of the upper end of the side surface of side-wall metallic layer and bottom electrode metal; Follow deposit MIM medium and top electrode metal again, process etch processes after the deposit of top electrode metal, and then deposit one deck dielectric, the surface of this dielectric is through the metal of deposit upper layer interconnects again after the smooth processing; Adopt general through hole of integrated circuit industry and craft of metal dealing at last, draw two electrodes up and down of capacitor with capacitor upper layer interconnects metal and last through hole.
9. the manufacture method of " metal-insulator-metal type " capacitor arrangement in the integrated circuit according to claim 8, it is characterized in that: after described bottom electrode metal is etched, increase a step bottom electrode metal below next-door neighbour dielectric etching vertically again, the surface deposition of bottom electrode metal after etching and dielectric and eat-back sheet metal then makes the height of the side-wall metallic layer in the vertical direction that form greater than the vertical thickness of bottom electrode metal.
10. the manufacture method of " metal-insulator-metal type " capacitor arrangement in the integrated circuit according to claim 8, it is characterized in that: before deposit bottom electrode metal, set in advance the dielectric between lower interconnection metal and lower interconnection metal and the bottom electrode, and lower through-hole is set, and then deposit bottom electrode metal level in this dielectric layer inside.
11. the manufacture method of " metal-insulator-metal type " capacitor arrangement according to Claim 8 or in the 9 or 10 described integrated circuits, it is characterized in that: chemical gas-phase deposition method is adopted in the deposit of described sidewall sheet metal, perhaps adopt organic metal oxide chemistry gas-phase deposition method, perhaps adopt the atomic layer chemical vapour deposition method.
12. the manufacture method of " metal-insulator-metal type " capacitor arrangement according to Claim 8 or in the 9 or 10 described integrated circuits is characterized in that: described MIM dielectric layer is the SiO that adopts the plasma-reinforced chemical vapor deposition method to form
2, SixNy, SiOxNy or SiO
2/ SixNy compound medium layer, or the HfO that adopts the atomic layer chemical vapour deposition method to form
2, ZrO
2, Al
2O
3, Ta
2O
5Dielectric layer of high dielectric constant.
13. the manufacture method of " metal-insulator-metal type " capacitor arrangement according to Claim 8 or in the 9 or 10 described integrated circuits, it is characterized in that: chemical gas-phase deposition method is adopted in the deposit of described top electrode metal, perhaps adopt organic metal oxide chemistry gas-phase deposition method, perhaps adopt the physical vapor deposition method.
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