CN101924019B - Preparation method of metal capacitor in semiconductor device - Google Patents
Preparation method of metal capacitor in semiconductor device Download PDFInfo
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- CN101924019B CN101924019B CN2009100574077A CN200910057407A CN101924019B CN 101924019 B CN101924019 B CN 101924019B CN 2009100574077 A CN2009100574077 A CN 2009100574077A CN 200910057407 A CN200910057407 A CN 200910057407A CN 101924019 B CN101924019 B CN 101924019B
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Abstract
The invention discloses a preparation method of a metal capacitor in a semiconductor device. The preparation of the metal capacitor is integrated in the subsequent process of the semiconductor device. After finishing the preparation of contact through holes of the metal capacitor by the conventional process, the method comprises the following steps of: (1) coating antireflection materials on the whole silicon slice to fill the contact through holes, and then repeatedly carving the antireflection materials residual to the contact through holes until the bottoms of the contact through holes reserve the antireflection materials with the preset thickness; (2) defining contact holes with larger diameters than those of the contact through holes above the contact through holes on an interlayer membrane by adopting a photoetching process, and then etching the exposed interlayer membrane to the antireflection materials to form the contact holes; and (3) depositing top-layer metal on the whole silicon slice, fully filling the deposited top-layer metal in the contact holes and the contact through holes, and finally imaging the top-layer metal by utilizing the photoetching process and an etching process, wherein the top-layer metal has a preset thickness on the interlayer membrane. In the method, the high-quality metal capacitor is obtained by etching larger upper-polar plate contact holes to fill wiring metal comprising Al and the like.
Description
Technical field
The present invention relates to a kind of preparation method of metal capacitance, particularly a kind of in semiconductor device the preparation method of metal capacitance.
Background technology
The metal capacitance that is made up of metal-dielectric-metal all has important use at memory circuitry in analog circuit and the radio circuit.In order to improve circuit level; Existing many relevant work have been done optimization to metal capacitance; The dielectric that has high-k like utilization is made the dielectric of metal capacitance, or with the dielectric layer thickness attenuate, maybe will carry out electric capacity and carry out parallel connection on unit are, to obtain maximum capacitance.In practical application; Especially in radio circuit is used; For the capacitor element that obtains high Q value
to obtain low energy loss; Resistance to the last bottom crown (comprising relevant line) of metal capacitance also has requirement (resistance value that wherein goes up bottom crown is more little, and the Q value of the metal capacitance that it constituted is just big more).And in the aluminium postchannel process of reality; Usually the bottom crown of electric capacity adopts the AlCu distribution, and thickness is generally at the 4000-6000 dust, and top crown generally adopts metal TIN, tungsten or Ta; Thickness is generally at the 800-1500 dust, and the resistance of top crown is bigger more than 10 times than the resistance of bottom crown like this.In order to obtain lower top crown resistance, also be employed in preparation through hole as much as possible on the top crown, in through hole, fill the tungsten plug to reduce the resistance of throughhole portions.
Technological process is generally:
1) first deposit is as the material (generally can be integrated into the lower metal line in the metal interconnected technology) of bottom crown; Graphical this layer material forms as the part of bottom crown with as the part of metal connecting line; Follow the dielectric insulating film in the depositing metal electric capacity on bottom crown; Deposit then graphically forms top crown as the material of top crown, afterwards film between illuvium; And the interlayer film after the deposit carried out the cmp leveling, in the interlayer film, form the contact through hole of top crown and bottom crown and other contact through hole through a photoetching and etching technics at last;
2) deposition tungsten to be filling contact through hole, and adopts cmp leveling silicon chip surface, obtains the tungsten plug;
3) deposit top-level metallic on the interlayer film;
4) adopt photoetching and etching technics to accomplish the graphical of top-level metallic, finally form metal capacitor structure as shown in Figure 1, wherein on top crown, prepared a plurality of tungsten plugs.Fig. 1 is for only having provided the structural representation of metal capacitance part, and wherein 11 is the bottom crown of metal capacitance, and 12 is the lower metal line in the semiconductor device interconnection process; 2 is the dielectric of metal capacitance, and 3 is the top crown of metal capacitance, and 4 is the tungsten plug of metal capacitance; 5 is the interlayer film; 61 for connecting the top-level metallic of top crown, and 62 for connecting the top-level metallic of bottom crown, and 63 for connecting the top-level metallic of lower metal line.
Summary of the invention
The technical problem that the present invention will solve provides the preparation method of metal capacitance in a kind of semiconductor device, and it can provide the metal capacitance of high Q value.
For solving the problems of the technologies described above; The preparation method of metal capacitance in the semiconductor device of the present invention; The preparation of this metal capacitance is integrated in the postchannel process of semiconductor device, after the contact through hole preparation of accomplishing metal capacitance according to old process, comprises the steps:
1) on whole silicon wafer, is coated with antireflection material to fill contact through hole, then anti-carves the antireflection material of antireflection material to contact through hole bottom residue one predetermined thickness;
2) adopt photoetching process, on contact through hole on the interlayer film, define the contact hole of diameter greater than contact through hole, the interlayer film that exposes of etching forms contact hole to antireflection material afterwards;
3) deposit top-level metallic on whole silicon wafer makes top-level metallic complete filling contact hole and contact through hole after deposit is accomplished, and on the interlayer film, has preset thickness, utilizes photoetching and etching technics to make top-level metallic graphical at last.
The present invention also provides the preparation method of metal capacitance in the another kind of semiconductor device, and the preparation of metal capacitance is integrated in the postchannel process of semiconductor device, after accomplishing the interlayer film on the metal capacitance according to the technology of routine, comprises the steps:
1) utilize photoetching and etching technics in the interlayer film, to form the contact through hole of metal capacitance top crown and the contact through hole of lower metal line; Wherein the height of the contact through hole of top crown and diameter ratio is between the 0.2-1.0, and the contact through hole size of lower metal line is identical with common process;
2) the deposition tungsten metal makes the contact through hole of its complete filling lower metal line on silicon chip; The tungsten on the said interlayer film is removed in leveling afterwards; In the contact through hole of lower metal line, forming the tungsten plug, wherein is partially filled in the contact through hole of metal capacitance top crown;
3) deposit top-level metallic makes the contact through hole of top-level metallic complete filling metal capacitance top crown, and on the interlayer film, has preset thickness, utilizes photoetching and etching technics to make top-level metallic graphical at last.
Among the preparation method of metal capacitance of the present invention; Replace by interconnecting metal the metal capacitance in original technology contact tungsten plug is all or part of; And, solved the problem of the filling capacity of interconnecting metal through strengthening the diameter of contact hole, because of Al (2.9 * 10 as interconnecting metal
-8Ω .m) or the resistance of Cu and both alloys all than tungsten (5.3 * 10
-8Ω .m) little, reduce parasitic resistance with this, make the Q value of prepared metal capacitance obtain improving.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is for adopting the cross section structure sketch map of the metal capacitance that has prepared now;
Fig. 2 be with a kind of preparation flow corresponding metal electric capacity of the present invention in the cross section structure sketch map of each step;
Fig. 3 is preparation method's schematic flow sheet one of metal capacitance in the semiconductor device of the present invention;
Fig. 4 be with another kind of preparation flow corresponding metal electric capacity of the present invention in the cross section structure sketch map of each step;
Fig. 5 is preparation method's schematic flow sheet two of metal capacitance in the semiconductor device of the present invention.
Embodiment
The preparation method of metal capacitance in the semiconductor device of the present invention; The preparation of this metal capacitance is integrated in the postchannel process of semiconductor device, after the contact through hole preparation of accomplishing said metal capacitance according to old process, (sees Fig. 2 a, comprises the bottom crown 11 of metal capacitance; The dielectric 2 of metal capacitance; The top crown 3 of metal capacitance, interlayer film 5 and contact through hole 41), comprise the steps (see figure 3):
1) on whole silicon wafer, is coated with antireflection material 7 (also claiming BARC) to fill contact through hole 41 (seeing Fig. 2 b), then anti-carves the antireflection material (seeing Fig. 2 c) of antireflection material to contact through hole bottom residue one predetermined thickness, anti-carve and to adopt dry etch process;
2) adopt photoetching process; On contact through hole on the interlayer film, define the contact hole (or claim contact groove) of diameter greater than said contact through hole; With can guarantee that follow-up interconnecting metal can this contact hole of complete filling (see Fig. 2 d, promptly after the photoetching photoresist 8 to cover be not the interlayer film 5 of contact hole position), the interlayer film that exposes of etching is to antireflection material afterwards; Form contact hole 42, remove photoresist 8 and antireflection material 7 (seeing Fig. 2 f) afterwards;
3) deposit top-level metallic on whole silicon wafer; Top-level metallic complete filling after deposit is accomplished is arranged in the contact hole and the contact through hole of interlayer film 5; And on the interlayer film, has preset thickness; Utilize photoetching and etching technics to make top-level metallic graphical at last, form to connect the top-level metallic 61 of top crown, the top-level metallic 62 that connects bottom crown be connected semiconductor device in the top-level metallic 63 (seeing Fig. 2 g) of lower metal line.
The thickness that anti-carves back contact through hole bottom anti-reflective material in the above-mentioned steps one can be set at and the diameter ratio of contact through hole is between the 0.2-1.0.And the height of the prepared contact hole of step 2 and the ratio of diameter are between the 0.2-1.0, and promptly above-mentioned ratio can guarantee that the subsequent interconnect metal can fill contact through hole and contact hole preferably.Top-level metallic can be selected common interconnecting metal for use, is the AlCu and the TiN of deposit successively, AlSiCu and TiN, AlCu, Ti and TiN; AlSiCu, Ti and TiN, Ti, AlCu and TiN, Ti, AlSiCu and TiN; TiN, AlCu, Ti and TiN, TiN and AlSiCu, Ti, TiN, AlCu and TiN; Ti, TiN, AlSiCu and TiN, Ti, TiN, AlCu, Ti and TiN, or Ti, TiN, AlSiCu, Ti and TiN.
The present invention also provides the preparation method of metal capacitance in the another kind of semiconductor device, and it comprises the steps (see figure 5) for after the interlayer film of accomplishing according to the technology of routine on the said metal capacitance:
1) utilize photoetching and etching technics in the interlayer film, to form the contact through hole 43 of metal capacitance top crown, the contact through hole of lower metal line and the contact through hole of bottom crown; Wherein the height of the contact through hole of top crown and diameter ratio is between the 0.2-1.0; And the contact through hole size of the contact through hole of lower metal line and bottom crown is identical with common process; At this moment the hole that connects the metal capacitance top crown is up and down consistent, and this hole requirement size is bigger than its elsewhere, generally can accomplish 2-3 μ m;
2) the deposition tungsten metal makes the contact through hole of its complete filling lower metal line and the contact through hole of bottom crown on silicon chip; The tungsten on the interlayer film is removed in leveling afterwards; In the contact through hole of the contact through hole of lower metal line and bottom crown, form the tungsten plug; And because of the contact through hole of metal capacitance top crown than big many of the contact through hole of bottom crown and lower metal line, so in the contact through hole of top crown, (see Fig. 4 a) for partially filled;
3) deposit top-level metallic; Make the contact through hole of the said metal capacitance top crown of said top-level metallic complete filling; And on said interlayer film, has preset thickness; Utilize photoetching and etching technics to make said top-level metallic graphical at last; Form to connect top crown top-level metallic 61, connect the top-level metallic 62 and the top-level metallic that is connected lower floor's line 63 (seeing Fig. 4 b) of bottom crown, wherein the border of the contact through hole it under will be covered in the border of top-level metallic 61, be preferably the border of top-level metallic and under it border difference of contact through hole more than or equal to 0.15 μ m.Top-level metallic in this method is identical with top-level metallic in the said method, optional common interconnecting metal.
The preorder step is in the conventional metal capacitance preparation: deposit lower interconnection metal on the substrate that forms predetermined structure; Utilize photoetching and etching technics to make said lower interconnection metal patternization, form lower metal line part 12 and as the bottom crown part 11 of said metal capacitance; The insulating medium layer of depositing metal electric capacity, photoetching and etching form the dielectric layer 2 of metal capacitance; The formation of metal capacitance top crown 3; The deposit of interlayer film 5; Adopt photoetching and etching technics in the interlayer film, to prepare contact through hole; The deposition tungsten metal is to fill contact through hole, and last CMP leveling obtains tungsten plug 4.Contact hole among the present invention and contact through hole can be square, also can be strip.
With 0.18 μ m radio frequency technology is example, and the thickness of its top-level metallic is 2.8 μ m, and the he design rules specify minimum metal live width of top-level metallic is 2.6 μ m; Inferior top-level metallic (being lower metal) thickness is 5200 dusts, and the he design rules specify minimum metal live width of inferior top-level metallic is 0.28 μ m; Dielectric thickness 300 dusts; Top crown thickness 1000 dusts; Interlayer film thickness 14000 dusts.
Existing capacitance structure is because the depth-width ratio of through hole is about 5, and the metal that utilizes the AL sputter can not be met requirement covers, and therefore must adopt tungsten plug technology.
Press implementation method 1 of the present invention:
1) at the lower electrode figure; The dielectric insulating film deposit; Upper electrode deposit and graphical, after deposit of interlayer film and the cmp completion with the planarization of interlayer film thereof, the hole-above-mentioned flow process through a photoetching-etching formation contact upper electrode is identical with existing technology earlier.
2) anti-carve through being coated with BARC (antireflection material) and BARC thereof, at the bottom of the hole, form certain thickness BARC.The BARC residual thickness is about the 500-2800 dust, and the ratio of bore dia is between 0.2-1.0.
3) obtain contacting the hole of top-level metallic through another time photoetching and etching, the size in its hole equals 2.3 μ m, and the ratio of the height in hole and diameter is less than 0.6.
4) through the deposit of metal sputtering completion top-level metallic, for the hole of depth-width ratio about 0.6,300-400 ℃ middle temperature Al sputtering technology generally just can meet the demands, and better if desired Al coverage rate can adopt 400-500 ℃ high temperature AL sputtering technology.
5) accomplish the graphical of top-level metallic through metal lithographic-etching.
By implementation method 2 of the present invention: utilize the size of metal capacitance big characteristics-for example minimum is 3 μ m * 3 μ m; To this electric capacity take big clear size of opening for example 2.7 μ m (being different from other regional through holes 0.28 μ m) thus the thickness of tungsten in the through hole is lowered, big portion is replaced by Al.
Claims (4)
1. the preparation method of metal capacitance in the semiconductor device, the preparation of said metal capacitance is integrated in the postchannel process of semiconductor device, after the contact through hole preparation of accomplishing said metal capacitance according to old process, it is characterized in that, comprises the steps:
1) on whole silicon wafer, is coated with antireflection material to fill said contact through hole, then anti-carves the antireflection material of said antireflection material to said contact through hole bottom residue one predetermined thickness;
2) adopt photoetching process, on contact through hole on the interlayer film, define the contact hole of diameter greater than said contact through hole, interlayer film to the said antireflection material that exposes of etching forms contact hole afterwards;
3) deposit top-level metallic on whole silicon wafer makes said contact hole of said top-level metallic complete filling and contact through hole after deposit is accomplished, and on said interlayer film, has preset thickness, utilizes photoetching and etching technics to make said top-level metallic graphical at last.
Said top-level metallic is the AlCu and the TiN of deposit successively, AlSiCu and TiN, AlCu, Ti and TiN; AlSiCu, Ti and TiN, Ti, AlCu and TiN, Ti, AlSiCu and TiN; TiN, AlCu, Ti and TiN, TiN and AlSiCu, Ti, TiN, AlCu and TiN; Ti, TiN, AlSiCu and TiN, Ti, TiN, AlCu, Ti and TiN, or Ti, TiN, AlSiCu, Ti and TiN.
2. according to the preparation method of metal capacitance in the described semiconductor device of claim 1, it is characterized in that: the diameter ratio of the residual thickness of contact through hole bottom anti-reflective material and said contact through hole is between the 0.2-1.0 after said the anti-carving in the said step 1).
3. according to the preparation method of metal capacitance in claim 1 or the 2 described semiconductor device, it is characterized in that: said step 2) ratio of the height of prepared contact hole and diameter is between the 0.2-1.0.
4. the preparation method of metal capacitance in the semiconductor device, the preparation of said metal capacitance is integrated in the postchannel process of semiconductor device, after the interlayer film of accomplishing according to the technology of routine on the said metal capacitance, it is characterized in that, comprises the steps:
1) utilize photoetching and etching technics in said interlayer film, to form the contact through hole of said metal capacitance top crown and the contact through hole of lower metal line; The height of the contact through hole of wherein said top crown and diameter ratio are between the 0.2-1.0, and the contact through hole size of said lower metal line is identical with common process;
2) the deposition tungsten metal makes the contact through hole of the said lower metal line of its complete filling on silicon chip; The tungsten on the said interlayer film is removed in leveling afterwards; In the contact through hole of said lower metal line, forming the tungsten plug, is partially filled in the contact through hole of wherein said metal capacitance top crown;
3) deposit top-level metallic makes the contact through hole of the said metal capacitance top crown of said top-level metallic complete filling, and on said interlayer film, has preset thickness, utilizes photoetching and etching technics to make said top-level metallic graphical at last.
Said top-level metallic is the AlCu and the TiN of deposit successively, AlSiCu and TiN, AlCu, Ti and TiN; AlSiCu, Ti and TiN, Ti, AlCu and TiN, Ti, AlSiCu and TiN; TiN, AlCu, Ti and TiN, TiN and AlSiCu, Ti, TiN, AlCu and TiN; Ti, TiN, AlSiCu and TiN, Ti, TiN, AlCu, Ti and TiN, or Ti, TiN, AlSiCu, Ti and TiN.
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| CN2009100574077A CN101924019B (en) | 2009-06-11 | 2009-06-11 | Preparation method of metal capacitor in semiconductor device |
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|---|---|---|---|
| CN2009100574077A CN101924019B (en) | 2009-06-11 | 2009-06-11 | Preparation method of metal capacitor in semiconductor device |
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| CN101924019B true CN101924019B (en) | 2012-02-15 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239010B1 (en) * | 1999-07-02 | 2001-05-29 | United Microelectronics Corp. | Method for manually manufacturing capacitor |
| CN1641858A (en) * | 2004-01-13 | 2005-07-20 | 上海华虹Nec电子有限公司 | Method for magnifying silicon slide unit area metal-dielectric-metal capacitance |
| CN101192568A (en) * | 2006-11-24 | 2008-06-04 | 和舰科技(苏州)有限公司 | Integrate circuit 'metal-insulator-metal' capacitor structure and its manufacture method |
| CN101217129A (en) * | 2007-12-28 | 2008-07-09 | 上海集成电路研发中心有限公司 | A formation method of interlayer capacitor |
-
2009
- 2009-06-11 CN CN2009100574077A patent/CN101924019B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239010B1 (en) * | 1999-07-02 | 2001-05-29 | United Microelectronics Corp. | Method for manually manufacturing capacitor |
| CN1641858A (en) * | 2004-01-13 | 2005-07-20 | 上海华虹Nec电子有限公司 | Method for magnifying silicon slide unit area metal-dielectric-metal capacitance |
| CN101192568A (en) * | 2006-11-24 | 2008-06-04 | 和舰科技(苏州)有限公司 | Integrate circuit 'metal-insulator-metal' capacitor structure and its manufacture method |
| CN101217129A (en) * | 2007-12-28 | 2008-07-09 | 上海集成电路研发中心有限公司 | A formation method of interlayer capacitor |
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