CN101192522A - Grids and method of manufacture - Google Patents
Grids and method of manufacture Download PDFInfo
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- CN101192522A CN101192522A CNA2006101188117A CN200610118811A CN101192522A CN 101192522 A CN101192522 A CN 101192522A CN A2006101188117 A CNA2006101188117 A CN A2006101188117A CN 200610118811 A CN200610118811 A CN 200610118811A CN 101192522 A CN101192522 A CN 101192522A
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Abstract
The invention relates to a method for manufacturing a grid. The method includes the following steps: a fundus of a semiconductor is provided; a first dielectric layer is generated on the fundus of the semiconductor; at least one second dielectric layer is generated on the first dielectric layer; a groove is generated between the first dielectric layer and the second dielectric layer, and the bottom of the groove exposes the surface of the fundus; the second dielectric layer is removed; an conductive layer is generated both in the groove of the first dielectric layer and on the first dielectric layer; an optical resist layer is reelingly coated on the conductive layer, and a graphic presentation is carried out to generate a grid graph which is arranged above the groove of the first dielectric layer; the conductive layer and the first dielectric layer which are not covered by the grid graph are removed in a corrosion way. The method can control the generated linewidth on the bottom of the grid more accurately.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of bottom has the grid (notched gate) and the manufacture method thereof of groove.
Background technology
Along with the development of semiconductor fabrication process, the integrated level of semiconductor device is more and more higher, and size is more and more littler, and this needs the live width in the semiconductor fabrication process to do littler and littler.Usually, the size of the grid in the semiconductor device is represented the technology level of this process for fabrication of semiconductor device, reducing grating of semiconductor element at first needs to improve the resolution of photoetching process, for example adopt short wavelength's light source and advanced mask plate correction technique, but this needs very big economy and time cost.Existing a kind of method that reduces the live width of grid is on the basis of the grid that photoetching process defines, adopt the method for selective etch to form groove in the gate bottom of described formation, reduce the bottom live width of grid with this, thereby reduce the width of the conducting channel below the grid, improve response speed.The patent No. be US6875668B2 U.S. Patent Publication a kind of bottom that forms have the method for the grid of groove.Fig. 1 to Fig. 6 is the generalized section of each step corresponding structure of the method for described U.S. Patent Publication.
As shown in Figure 1, at first provide semi-conductive substrate 100, on described Semiconductor substrate 100, form oxide layer 102 successively, polysilicon layer 104, hard mask layer 106.Described hard mask layer 106 is silicon nitrides.
Spin coating photoresist layer and graphical on described hard mask layer 106, form photoresist figure 108 as shown in Figure 2, with described photoresist figure 108 is resist, the described hard mask layer 106 of etching forms hard mask pattern 106a, and the described polysilicon layer 104 of etching, form polysilicon layer 104a after the etching, and reserve part polysilicon layer 103.
Remove described photoresist figure 108, then as shown in Figure 3, on described polycrystal layer 104a sidewall, polysilicon layer 103 and described hard mask pattern 106a, form a dielectric layer 110.Then, as shown in Figure 4, the graphical and described dielectric layer 110 of etching makes 110 parts that keep described polysilicon layer 104a sidewall of dielectric layer to form sidewall dielectric layer 112.
As shown in Figure 5, with described hard mask pattern 106a, sidewall dielectric layer 112 is as protective layer, and the described polysilicon layer 103 of wet etching forms groove 114 below described sidewall dielectric layer 112.
As shown in Figure 6, remove described hard mask pattern 106a and sidewall dielectric layer 112, have the grid 115 of groove 114 below the formation.The gate bottom that forms has groove, makes the gate bottom that forms have less live width.
Above-mentioned formation bottom has the polycrystalline silicon material of method bottom wet etching of the grid 115 of groove 114, forms groove 114, reduces the live width of grid 115 bottoms.But wayward etch rate and etching terminal in wet etching can't accurately be controlled groove 114 degree of depth in the horizontal direction and the height of vertical direction of formation, thereby can't accurately control the live width of bottom of the grid 115 of formation.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of grid and manufacture method thereof, to solve the problem of the bottom live width that has the grid that accurately to control formation in the grid production method now.
For achieving the above object, the manufacture method of a kind of grid provided by the invention comprises: the semiconductor substrate is provided; On the described semiconductor-based end, form first dielectric layer; On described first dielectric layer, form one second dielectric layer at least; Form groove in described second dielectric layer and first dielectric layer, described channel bottom exposes described substrate surface; Remove described second dielectric layer; In the groove of described first dielectric layer and on described first dielectric layer, form conductive layer; Spin coating photoresist layer and graphical forms gate patterns on described conductive layer, and described gate patterns is positioned at the top of the groove of described first dielectric layer; Remove the conductive layer and first dielectric layer that is not covered by described gate patterns by etching.
Formation thickness is 5 to 100nm first dielectric layer on the described semiconductor-based end.
Described first dielectric layer is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound.Described second dielectric layer is a kind of or its combination in silicon nitride, silica, carborundum, the polysilicon.The formation method of described first dielectric layer and second dielectric layer is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), the ald.
The step that forms groove in described second dielectric layer and first dielectric layer is as follows: spin coating photoresist layer and graphical on described second dielectric layer forms channel patterns; With described photoresist layer with channel patterns is mask, and described second dielectric layer of dry etching and first dielectric layer are to exposing described substrate surface; Remove described photoresist layer.
Described conductive layer is a kind of in the combination, metal of polysilicon, polysilicon and metal silicide.
Described polysilicon is a doped polycrystalline silicon.
Accordingly, the present invention also provides a kind of grid structure, comprising: the semiconductor-based end; The suprabasil column conductive layer of described semiconductor; Wherein, be inlaid with dielectric layer in described column conductive layer bottom, described dielectric layer bottom contacted with the described semiconductor-based end.
Described column conductive layer is a kind of in polysilicon, metal, polysilicon and the metal silicide stack architecture.Described dielectric layer is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound.Be formed with the side wall protection layer at the described column conductive layer and the dielectric layer outside.
Compared with prior art, the present invention has the following advantages:
The present invention at first forms the height that first dielectric layer has defined the bottom groove of the grid that will form on the semiconductor-based end, because depositing operation can accurately be controlled the thickness of deposition, thereby the height of groove is controlled.On described first dielectric layer, form second dielectric layer then, and in described first dielectric layer and second dielectric layer, form groove, it is roomy to utilize dry etching to form groove top aperture lines, the little characteristics of bottom live width, reach the purpose that in described first dielectric layer, forms small wire wide slot, overcome the restriction of photoetching resolution, and height that can be by adjusting described second dielectric layer and the etching technics parameter live width that is controlled at the groove in first dielectric layer, the width of the groove in described first dielectric layer is the live width of the bottom of grid, and visible the inventive method can more accurately be controlled the live width of bottom of the grid of formation.Simultaneously, the stack architecture and the etching that form first dielectric layer and second dielectric layer on the described semiconductor-based end form groove, have also avoided direct first dielectric layer at thinner thickness directly to form the difficult problem of groove.Can better control the height and the degree of depth of the groove of the bottom live width of grid of formation and gate bottom by the inventive method, the grid electrical parameter of formation is stable, unanimity, reliability height.
Description of drawings
Fig. 1 to Fig. 6 is existing a kind of generalized section of each step corresponding structure of method that the bottom has the grid of groove that forms;
Fig. 7 forms the flow chart of embodiment of method that the bottom has the grid of groove for the present invention;
Fig. 8 to Figure 18 forms the generalized section of each step corresponding structure of embodiment of the method for grid for the present invention;
Figure 19 has the generalized section of structure of embodiment of the grid of groove for the present invention bottom.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 7 forms the flow chart of embodiment of method that the bottom has the grid of groove for the present invention.
As shown in Figure 7, at first, provide semiconductor substrate (S100).The described semiconductor-based end is a kind of during silicon on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier, SiGe composition, arsenicization are sowed.In the described semiconductor-based end, mix N type impurity or p type impurity to form the conducting channel of device.Described semiconductor-based basal surface has a thin oxide layer, and described thickness of oxide layer is 1 to 100nm, and the formation method of described oxide layer is high-temperature thermal oxidation or deposition.This oxide layer is the grid oxygen of the grid of follow-up formation.
On the oxide layer at the described semiconductor-based end, form first dielectric layer (S200).Described first dielectric layer is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound, and its thickness is 5 to 100nm.First dielectric layer described in the present embodiment is a silicon nitride, and the method for its formation is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald, and the thickness of this silicon nitride layer has determined the height of groove of the gate bottom of follow-up formation.
On described first dielectric layer, form one second dielectric layer (S300) at least.Described second dielectric layer is a kind of in silicon nitride, silica, carborundum, the polysilicon or its combination, and the method for its formation is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald.Second dielectric layer described in the present embodiment is the combination of oxide layer and silicon nitride layer.It is as follows that it forms step, at first forms an oxide layer on described first dielectric layer, and the method for its formation is deposition, and this thickness of oxide layer is thinner, is about 1 to 200nm; Form a silicon nitride layer then on described oxide layer, the thickness of described silicon nitride layer determines according to process conditions.Owing to need form groove in described first dielectric layer and second dielectric layer in subsequent technique, the thickness of the silicon nitride layer in described second dielectric layer can determine the width of the channel bottom that forms.Oxide layer in described second dielectric layer is as the stop layer of removing the silicon nitride layer in described second dielectric layer in the subsequent technique.
Form groove in described first dielectric layer and second dielectric layer, described channel bottom exposes described substrate surface (S400).Its key step is as follows, spin coating photoresist layer on described second dielectric layer at first, and in described photoresist layer, form channel patterns by exposure imaging; With described photoresist layer with channel patterns is mask, and described second dielectric layer of dry etching and first dielectric layer are to exposing described substrate surface; Remove described photoresist layer.The etching gas of described dry etching is a fluoro-gas, as can being CF4, and C3F8, NF3, C2F6, CHF3, C4F8, SiF4's is a kind of, can mix gas Ar in addition, He, a kind of or combination among N2, the O2 is as diluent gas, to increase the uniformity of etching.The groove that forms by the adjustment to the etching technics parameter can have the different lateral inclination angle.Owing to defined the width at the top of the groove that forms by photoetching, can obtain the different bottom width of groove by adjustment to the sidewall draft angles of the groove that forms, the width of this bottom is the bottom width of formation grid in the subsequent technique.Because when dry etching forms groove, the side wall profile of the groove that forms generally all has an inclination angle with respect to vertical direction, promptly the section of the structure of the groove of Xing Chenging is generally trapezoidally, and the top open part opening live width of groove is bigger, and the bottom live width of groove is less.The profile inclination angle of trenched side-wall is big more, or the degree of depth of groove is dark more, the open top live width of the groove that forms and the difference of bottom live width are just big more, the present invention has utilized this characteristic of dry etching to reach the purpose that forms less trench bottom width just, the thickness by adjusting second dielectric layer and the technological parameter of etching can obtain the littler live width of live width of the figure that defines than photoetching process.This has also reduced the requirement to photoetching process resolution.
Remove described second dielectric layer (S500).Second dielectric layer described in the present embodiment is the stack architecture of silicon nitride layer and silicon oxide layer, can remove described silicon nitride layer and oxide layer successively by the wet etching of high selectivity.For example, at first fall silicon nitride layer in described second dielectric layer, remove oxide layer in described second dielectric layer by hydrogen fluoride then by phosphoric acid corrosion.Simultaneously, in the wet etching process,, can at first in described groove, fill sacrifice layer for avoiding wet etching to the substrate of channel bottom or the influence of first dielectric layer, for example, photoresist or antireflection material.As the separator of the silicon nitride layer in first dielectric layer and second dielectric layer, make wet etching remove described second dielectric layer becomes possibility to oxide layer in described second dielectric layer in this step process, and can not cause damage to the described first dielectric layer surface.After removing described second dielectric layer, in first dielectric layer, kept the groove of little live width, then the groove in described first dielectric layer surface and described first dielectric layer has been cleaned.
In the groove of described first dielectric layer and on described first dielectric layer, form conductive layer (S600).Described conductive layer is a kind of in the combination, metal of polysilicon, polysilicon and metal silicide.The method that forms described conductive layer be physical vapour deposition (PVD), chemical vapour deposition (CVD), ald or electroplate in a kind of.Conductive layer described in the present embodiment is a polysilicon.Described polysilicon layer is mixed,, form doped polycrystalline silicon to change its resistivity.
Spin coating photoresist and the graphical gate patterns that forms on described conductive layer, described gate patterns is positioned at the top position (S700) of the groove of described first dielectric layer.
Remove the polysilicon layer and first dielectric layer that is not covered by etching, form the grid structure (S800) that the bottom is inlaid with first dielectric layer by described gate patterns.The present invention at first forms the height that first dielectric layer has defined the bottom groove of the grid that will form on the semiconductor-based end, because depositing operation can accurately be controlled the thickness of first dielectric layer of deposition, thereby the height of groove is controlled.On described first dielectric layer, form second dielectric layer then, and in described first dielectric layer and second dielectric layer, form groove, utilize dry etching to form the characteristics that groove top aperture lines is roomy, the bottom live width is little, reach the purpose that in described first dielectric layer, forms small wire wide slot, overcome the restriction of photoetching resolution, and height that can be by adjusting described second dielectric layer and the etching technics parameter live width that is controlled at the groove in first dielectric layer.Simultaneously, on the described semiconductor-based end, form the stack architecture of first dielectric layer and second dielectric layer and form groove, also avoided directly in first dielectric layer of thinner thickness, directly forming the difficult problem of groove.Remove described second dielectric layer, the groove in described first dielectric layer has promptly defined the live width of the bottom of the grid that forms in the subsequent technique.Can better control the height and the degree of depth of the groove of the bottom live width of grid of formation and gate bottom by the inventive method, the grid electrical parameter of formation is stable, unanimity, reliability height.
Engaging profile below is described in detail the method that the present invention forms grid.Fig. 8 to Figure 18 forms the generalized section of each step corresponding structure of embodiment of the method for grid for the present invention.
As shown in Figure 8, at first, provide semiconductor substrate 200.A kind of for during silicon, SiGe composition, arsenicization are sowed on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier of the described semiconductor-based end 200.In the described semiconductor-based end 200, mix the conducting channel that N type impurity or p type impurity form device.Surface, the described semiconductor-based ends 200 has first oxide layer 202, and the thickness of described first oxide layer 202 is 1 to 100nm, and the formation method of described first oxide layer 202 is high-temperature thermal oxidation or deposition.This first oxide layer 202 is the gate oxide of the grid of follow-up formation.
As shown in Figure 9, form first dielectric layer 204 on described oxide layer 202, described first dielectric layer 204 is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound, and its thickness is 5 to 100nm.First dielectric layer 204 is a silicon nitride described in the present embodiment, and the method for its formation is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD) or the ald, and the thickness of this silicon nitride layer has determined the height of groove of the gate bottom of follow-up formation.On described first dielectric layer 204, form second oxide layer 206 and silicon nitride layer 208.Its step is at first forming second oxide layer 206 on described first dielectric layer 204, the method for its formation is deposition, and the thinner thickness of this second oxide layer 206 is about 1 to 200nm; Form a silicon nitride layer 208 then on described second oxide layer 206, the thickness of described silicon nitride layer 208 determines according to process conditions.Need form groove in described first dielectric layer 204, second oxide layer 206 and silicon nitride layer 208 in subsequent technique, the thickness that described silicon nitride is 208 layers can determine the width of the channel bottom that forms.Described second oxide layer 208 is as the stop layer of removing 208 layers of described silicon nitrides in the subsequent technique.
As shown in figure 10, spin coating first photoresist layer 210 and form channel patterns 211 on described silicon nitride layer 208.
As shown in figure 11, by dry etching the channel patterns 211 in described first photoresist layer 210 is transferred to formation groove 212 in described silicon nitride layer 208, second oxide layer 206 and first dielectric layer 204, the surface that described first oxide layer 202 is exposed in described groove 212 bottoms.The etching gas of described dry etching is a fluoro-gas, as can being CF4, and C3F8, NF3, C2F6, CHF3, C4F8, SiF4's is a kind of, can mix gas Ar in addition, He, a kind of or combination among N2, the O2 is as diluent gas, to increase the uniformity of etching.Sidewall by groove 212 that the adjustment of etching technics parameter is formed can have different inclination angle.Owing to defined the width at the top of the groove 212 that forms by photoetching, can obtain the different bottom width of groove 212 by adjustment to the sidewall draft angles of the groove 212 that forms, the width of this bottom is the bottom width of formation grid in the subsequent technique.Because when dry etching formed groove, the side wall profile of the groove of formation generally all had an inclination angle with respect to vertical direction, promptly the section of the structure of the groove of Xing Chenging is generally trapezoidally, and the top open part live width of groove is bigger, and the bottom live width of groove is less.The inclination angle of trenched side-wall is big more, or the degree of depth of groove is dark more, and the open top live width of the groove of formation and the difference of bottom live width are just big more.The present invention has utilized this characteristic of dry etching to reach the purpose that forms less groove 212 bottom widths just, the thickness by adjusting silicon nitride layer 208 and the technological parameter of etching can obtain the littler live width of live width of the groove figure 211 that defines than photoetching process.This has also reduced the requirement to photoetching process resolution.
As shown in figure 12, remove described photoresist layer 210.
As shown in figure 13, remove the described silicon nitride layer 208 and second oxide layer 206.Remove the described silicon nitride layer 208 and second oxide layer 206 successively by the wet etching of high selectivity in the present embodiment, for example, at first fall described silicon nitride layer 208, remove described second oxide layer 206 by hydrogen fluoride corrosion then by phosphoric acid corrosion.Simultaneously, in the wet etching process, for avoiding can at first in described groove 212, filling sacrifice layer to suprabasil first oxide layer 202 of groove 212 bottoms and the influence of first dielectric layer 204, for example, photoresist or antireflection material.Described second oxide layer 206 as the separator of silicon nitride in first dielectric layer 204 and silicon nitride layer 208, makes wet etching can not cause damage to described first dielectric layer 204 surfaces in this step process.After removing the described silicon nitride layer 208 and second oxide layer 206, in first dielectric layer 204, kept groove 212, the groove 212 in described first dielectric layer, 204 surfaces and described first dielectric layer 204 has been cleaned.
As shown in figure 14, form conductive layer 214 in the groove 212 in described first dielectric layer 204 and on described first dielectric layer 204.A kind of in the combination that described conductive layer 214 is polysilicon, polysilicon and metal silicide, the metal.The method that forms described conductive layer 214 be physical vapour deposition (PVD), chemical vapour deposition (CVD), ald or electroplate in a kind of.Conductive layer described in the present embodiment 214 is a polysilicon.Described polysilicon layer is mixed, change its resistivity.
As shown in figure 15, spin coating second photoresist layer and the graphical gate patterns 216 that forms on described conductive layer 214, described gate patterns 216 is positioned at the top of the groove 212 of described first dielectric layer 204.
As shown in figure 16, remove the conductive layer 214 and first dielectric layer 204 that is not covered, form the grid 214a that the bottom is inlaid with the first dielectric layer 204a by described gate patterns 216 by etching.As shown in figure 17, remove described gate patterns 216.As shown in figure 18, form the side wall protective layer of silicon nitride 218 and silica 220 at described grid 214a sidewall.The present invention at first forms the height that first dielectric layer 204 has defined the bottom groove of the grid that will form on the semiconductor-based end 200, because depositing operation can accurately be controlled the thickness of first dielectric layer 204 of deposition, thereby the height of groove is controlled.On described first dielectric layer 204, form second oxide layer 206 and silicon nitride layer 208 then, and form described groove 212, utilize dry etching to form the characteristics that groove top aperture lines is roomy, the bottom live width is little, reach the purpose that in described first dielectric layer 204, forms small wire wide slot, overcome the restriction of photoetching resolution, and height that can be by adjusting described silicon nitride layer 208 and the etching technics parameter live width that is controlled at the groove in first dielectric layer 204.In addition, on the described semiconductor-based end 200, form the stack architecture of first dielectric layer 204, second oxide layer 206 and silicon nitride layer 208 and form groove 212, also avoided directly on first dielectric layer 204 of thinner thickness, directly forming the difficult problem of groove.Remove the described silicon nitride layer 208 and second oxide layer 206, the groove 212 in described first dielectric layer 204 has promptly defined the live width of the bottom of the grid that forms in the subsequent technique.Can better control the height and the degree of depth of the groove of the bottom live width of grid of formation and gate bottom by the inventive method, the grid electrical parameter of formation is stable, unanimity, reliability height.
Corresponding the present invention also provides a kind of grid structure.Figure 19 is the generalized section of the embodiment of grid structure of the present invention.As shown in figure 19, the semiconductor-based end 200, comprise a gate oxide 202, is formed with the conductive layer 214a of column on described gate oxide 202, and described column conductive layer 214a is a kind of in polysilicon, metal or polysilicon and the metal silicide stack architecture.The conductive layer of column described in present embodiment 214a is a polysilicon.Be inlaid with dielectric layer 204a in described column conductive layer 214a bottom, described dielectric layer 204a is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound.The 204a of dielectric layer described in the present embodiment is a silicon nitride.Described dielectric layer 204a bottom contacts with described gate oxide 202.Outside described column conductive layer 214a and dielectric layer 204a, be formed with the side wall protection layer that silicon nitride layer 218 and silicon oxide layer 220 are formed.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the manufacture method of a grid comprises:
The semiconductor substrate is provided;
On the described semiconductor-based end, form first dielectric layer;
On described first dielectric layer, form one second dielectric layer at least;
Form groove in described second dielectric layer and first dielectric layer, described channel bottom exposes described substrate surface;
Remove described second dielectric layer;
In the groove of described first dielectric layer and on described first dielectric layer, form conductive layer;
Spin coating photoresist layer and graphical forms gate patterns on described conductive layer, and described gate patterns is positioned at the top of the groove of described first dielectric layer;
Remove the conductive layer and first dielectric layer that is not covered by described gate patterns by etching.
2. the manufacture method of grid as claimed in claim 1 is characterized in that: form thickness and be 5 to 100nm first dielectric layer on the described semiconductor-based end.
3. the manufacture method of grid as claimed in claim 1 or 2 is characterized in that: described first dielectric layer is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound.
4. the manufacture method of grid as claimed in claim 1, it is characterized in that: described second dielectric layer is a kind of or its combination in silicon nitride, silica, carborundum, the polysilicon.
5. the manufacture method of grid as claimed in claim 1 is characterized in that: the formation method of described first dielectric layer and second dielectric layer is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), the ald.
6. the manufacture method of grid as claimed in claim 1 is characterized in that: the step that forms groove in described second dielectric layer and first dielectric layer is as follows:
Spin coating photoresist layer and graphical forms channel patterns on described second dielectric layer;
With described photoresist layer with channel patterns is mask, and described second dielectric layer of dry etching and first dielectric layer are to exposing described substrate surface;
Remove described photoresist layer.
7. the manufacture method of grid as claimed in claim 1 is characterized in that: described conductive layer is a kind of in the combination, metal of polysilicon, polysilicon and metal silicide.
8. the manufacture method of grid as claimed in claim 7, it is characterized in that: described polysilicon is a doped polycrystalline silicon.
9. grid structure comprises:
The semiconductor-based end;
The suprabasil column conductive layer of described semiconductor;
Wherein, be inlaid with dielectric layer in described column conductive layer bottom, described dielectric layer bottom contacted with the described semiconductor-based end.
10. grid structure as claimed in claim 9 is characterized in that: described column conductive layer is a kind of in polysilicon, metal, polysilicon and the metal silicide stack architecture.
11. grid structure as claimed in claim 9 is characterized in that: described dielectric layer is a kind of in silicon nitride, carborundum, the silication of carbon nitrogen and thing, carbon oxygen silicon compound, the nitrogen-oxygen-silicon compound.
12. grid structure as claimed in claim 9 is characterized in that: be formed with the side wall protection layer at the described column conductive layer and the dielectric layer outside.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101188117A CN100539031C (en) | 2006-11-28 | 2006-11-28 | Grid and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101188117A CN100539031C (en) | 2006-11-28 | 2006-11-28 | Grid and manufacture method thereof |
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| CN101192522A true CN101192522A (en) | 2008-06-04 |
| CN100539031C CN100539031C (en) | 2009-09-09 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412133A (en) * | 2011-11-07 | 2012-04-11 | 上海华虹Nec电子有限公司 | Technological method for forming radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN102956461A (en) * | 2011-08-30 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Forming method of grid electrode |
| CN105575892A (en) * | 2015-12-17 | 2016-05-11 | 武汉高芯科技有限公司 | Technical method of infrared detector indium bump |
| CN103107065B (en) * | 2011-11-15 | 2017-04-05 | 黄辉 | A kind of preparation method of the nano-wire devices based on nano thread ordered arrangement |
| CN113451344A (en) * | 2021-07-01 | 2021-09-28 | 武汉新芯集成电路制造有限公司 | Backside illuminated image sensor and method of manufacturing the same |
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2006
- 2006-11-28 CN CNB2006101188117A patent/CN100539031C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956461A (en) * | 2011-08-30 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Forming method of grid electrode |
| CN102956461B (en) * | 2011-08-30 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of grid electrode |
| CN102412133A (en) * | 2011-11-07 | 2012-04-11 | 上海华虹Nec电子有限公司 | Technological method for forming radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN102412133B (en) * | 2011-11-07 | 2013-10-23 | 上海华虹Nec电子有限公司 | Technological method for forming radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) |
| CN103107065B (en) * | 2011-11-15 | 2017-04-05 | 黄辉 | A kind of preparation method of the nano-wire devices based on nano thread ordered arrangement |
| CN105575892A (en) * | 2015-12-17 | 2016-05-11 | 武汉高芯科技有限公司 | Technical method of infrared detector indium bump |
| CN105575892B (en) * | 2015-12-17 | 2018-04-03 | 武汉高芯科技有限公司 | A kind of process of infrared detector indium post |
| CN113451344A (en) * | 2021-07-01 | 2021-09-28 | 武汉新芯集成电路制造有限公司 | Backside illuminated image sensor and method of manufacturing the same |
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| Publication number | Publication date |
|---|---|
| CN100539031C (en) | 2009-09-09 |
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