CN101188430A - A frequency deviation pre-compensation device and method for broadband code division multiple address user device - Google Patents
A frequency deviation pre-compensation device and method for broadband code division multiple address user device Download PDFInfo
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Abstract
The invention provides a frequency deviation pre-compensating device and a method thereof. The frequency deviation pre-compensating device includes a sine cosine module, a Booth encoding module, a partial product module, a compressor array module, and an adder module which are serially connected in turn. The sine cosine module is used for calculating the sine value and the cosine value of the rotation angle; the Booth encoding module is used for conducting Booth encoding on the sine value and the cosine value; the partial product module is used for converting the inputted I/Q date into partial products according to the result of the Booth encoding; the compressor array module is used for compressing the partial products; the adder module is used for summing and outputting the compressed partial products. Adopting the device and the method of the invention can save resource, increase the speed, lessen the area, and lower the power dissipation.
Description
Technical field
The present invention relates to Wideband Code Division Multiple Access (WCDMA) (Wideband Code Division Multiple Access is hereinafter to be referred as the WCDMA) communications field, and be particularly related to the apparatus and method of a kind of WCDMA subscriber equipment (UserEquipment is hereinafter to be referred as UE) frequency deviation pre-compensation.
Background technology
In any communication system, physical device frequency drift long-term or short-term itself makes the crystal oscillator frequency of receiver and the crystal oscillator frequency of transmitter have certain deviation, if this frequency departure is not taken measures to be eliminated and is incorporated in the communication system, will inevitably bring influence to communication quality.And in mobile communication, because UE moves the Doppler frequency deviation that causes and also can be retained in the baseband signal by mixing and filtering.We are collectively referred to as frequency deviation with above-mentioned two kinds of frequency departures, and it has the process of a quantitative change to qualitative change to the influence of base band signal process: if frequency deviation is very little, it is also very little to the influence of signal processing results; Frequency deviation is big more, and its influence is also big more; When frequency deviation surpassed a certain value, the phase place aliasing can appear in signal, and directly cause can't the correct decision data content.There is this problem too in WCDMA communication system as the main standard of 3G (Third Generation) Moblie.Therefore, in WCDMAUE, should there be specific device to proofread and correct frequency deviation, make UE and base station can keep the synchronous of certain precision, this generally is by automatic frequency control (Automatic Frequency Control, be called for short AFC) realize: slot synchronization obtained at Cell searching, behind frame synchronization and the main scrambler number to Common Pilot Channel (Common Pilot Channel, hereinafter to be referred as CPICH) descrambling and de-spreading, CPICH symbol after the demodulation is done fast fourier transform to frequency domain, extract frequency departure information according to energy spectrometer then, frequency deviation information is sent into voltage controlled oscillator (voltage controlledoscillator after low pass filter is level and smooth, hereinafter to be referred as VOC), VOC adjusts the output signal frequency of oscillator according to the signal voltage size of input.Simultaneously, also has frequency offset compensation element, according to Common Pilot Channel (CommonPilot Channel, hereinafter to be referred as CPICH) the frequency offset estimating value, to Primary Common Pilot Channel (PrimaryCommon Pilot Channel, hereinafter to be referred as P-CPICH) and Primary Common Control Physical Channel (Primary Common Control Physical Channel is hereinafter to be referred as P-CCPCH) carry out compensate of frequency deviation.
But, the prerequisite of this way is the main scrambler number that the cell search unit of UE has obtained correct slot synchronization, frame synchronization and sub-district, and the baseband signal of cell search process is not eliminated the influence of frequency deviation before this, thereby is difficult to guarantee that the correct demodulation of CPICH obtains frequency offset estimating more accurately.Particularly power on the initial stage at UE, the initial frequency deviation of UE local oscillator clock source and base station side is very big, has a strong impact on receptivity.Simultaneously, in order to improve the performance of Cell searching, usually the baseband signal that receives is carried out oversampling, the sampling rate that input signal is increased can convert more precise time closeness to; For the influence that reduces to decline, improve reliability, cell search process all needs to carry out the judgement of multi-slot cumulative mean usually in each step.Under the situation of high frequency deviation, the low-density of time slot causes significant timing offset between the processing time, has also caused respectively to go on foot the peak skew, because the expansion of correct peak value is on a plurality of positions, promptly so-called " aliasing effect ", this is more remarkable when oversampled data flows.Because each step of Cell searching is not to handle in same time slot, the actual peak location when timing slip will cause next step to begin departs from the reference timing that back provides, and causes other more serious errors.Therefore, though UE has AFC device and special compensate of frequency deviation process, but it needs Cell searching that frequency deviation information is provided, and cell search process is carried out before this, if input signal is left intact, will influence the Performance And Reliability of Cell searching, thereby have influence on other modules of UE, as Multipath searching and receiver module, when UE starts shooting, enter very long search network process probably, even lose synchronously with the base station.
Summary of the invention
The objective of the invention is to propose a kind of WCDMA UE carried out frequency deviation pre-compensation before cell search process apparatus and method,, save resource, and accelerate search speed to improve the reliability of Cell searching.
In view of above-mentioned purpose, the invention provides a kind of WCDMA UE frequency deviation pre-compensation device, comprise the sine and cosine module that is linked in sequence successively, this coding module of cloth, the partial product module, compressor reducer array module and adder Module, above-mentioned sine and cosine module is used to calculate the sine value and the cosine value of the anglec of rotation; This coding module of above-mentioned cloth is used for above-mentioned sine value and cosine value are carried out this coding of cloth; Above-mentioned partial product module is used for according to the result of above-mentioned this coding of cloth the I/Q data of importing being converted to partial product; The said compressor array module is used to compress above-mentioned partial product; Above-mentioned adder Module is used for summation of the partial product after the compression and output.
Wherein, above-mentioned sine and cosine module comprises interconnective address generator and programmable read only memory at least, the address signal of directioin parameter that above-mentioned address generator basis has disposed and parameter generation sampling period real-time change also exports above-mentioned programmable read only memory to, above-mentioned programmable read only memory is according to above-mentioned address signal addressing, read a sine value and a cosine value of storage in advance at the rising edge of each sampling clock, and export it to above-mentioned cloth this coding module.
This coding module of above-mentioned cloth comprises a plurality of booth encoders and the complementer that is connected with a booth encoder at least, above-mentioned complementer is negated to the sine value of above-mentioned sine and cosine module output and is exported the result of sine value opposite number to booth encoder, above-mentioned a plurality of booth encoder offset of sinusoidal value opposite number, sine value and cosine value respectively carries out this coding of cloth, and exports the result to the partial product module.
Above-mentioned partial product module comprises that at least a plurality of independent parts amass maker, be used for will input the I/Q data be converted to partial product and export compressor reducer to.
The said compressor array module comprises the compressor reducer array of being made up of a plurality of compressor reducers at least.
The multistage arrangement of said compressor array is used for data are repeatedly compressed.
Above-mentioned adder Module comprises a plurality of adders and a plurality of register at least, and above-mentioned adder is to the summed result of compressor reducer array module output, and the above-mentioned summed result of register pair is handled and output.
The present invention also provides a kind of WCDMA UE frequency deviation pre-compensation method, may further comprise the steps:
Step 2, in the sine and cosine module, utilize Digital Signal Processing (the Digital SignalProcessing of UE, hereinafter to be referred as DSP) the above-mentioned directioin parameter of component configuration and the address signal of parameter generation sampling period real-time change, utilize above-mentioned address signal to carry out addressing, obtain a plurality of sine values and cosine value and carry out quantification treatment, storage computation result also exports it to cloth this coding module;
Step 3 is carried out this coding of cloth and is exported the partial product module to the aforementioned calculation result in this coding module of cloth;
The compressor reducer array module is amassed and exported to step 4 according to this coding of above-mentioned cloth with the I/Q data generating portion of input in the partial product module;
Step 5, in the compressor reducer array module with the compression of above-mentioned partial product and export adder Module to;
The phase place rotation of carrying out onesize and direction in the time of N sampling period to received signal compensates, parameter sampling period of phase place rotation draws according to the relational expression 2 π/k=2 π Δ f (N/sc) of frequency deviation and phase shift, wherein k is an I/Q complex plane segments, Δ f is a frequency departure, c is the spreading rate of WCDMA, s is the oversampling rate of baseband signal, and N is parameter sampling period; Simultaneously, if Δ f for just, directioin parameter is 1, if Δ f for negative, directioin parameter is 0.
In the partial product compression process, can repeatedly compress above-mentioned partial product.
Utilize WCDMA UE frequency deviation pre-compensation method provided by the invention, can carry out the phase place rotation compensation to the baseband signal piecewise approximation ground that cell search unit receives, can carry out positive and negative compensation, and can be by selecting segments at compensation precision with take a good balance point is arranged between the resource.Wherein, sine value and cosine value adopt look-up table to calculate in advance and quantize storage, compare with real-time Calculation Method, have the resource of saving, fireballing advantage.WCDMA UE frequency deviation pre-compensation device provided by the invention utilizes booth encoder and 4-2 compressor reducer, multiplication and addition and subtraction is unified with taking advantage of the structure that adds combination to realize, by the logic reach of negating, shared booth encoder, methods such as generation precompensation partial product reach the beneficial effect that reduces area, reduces power consumption.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.For the person of ordinary skill in the field, from detailed description of the invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.
Description of drawings
Fig. 1 is the block diagram of WCDMA UE cell search unit to the processing procedure of baseband signal;
Fig. 2 is the general structure block diagram of compensate of frequency deviation device of the present invention;
Fig. 3 is the internal circuit diagram of the compensate of frequency deviation device of a preferred embodiment of the present invention;
Fig. 4 is the sine value after the quantification of a preferred embodiment of the present invention and the schematic diagram of cosine value.
Embodiment
Be described in further detail below in conjunction with the apparatus and method of the drawings and specific embodiments a kind of WCDMA UE frequency deviation pre-compensation of the present invention.
Fig. 1 represents the processing procedure of WCDMA UE cell search unit to baseband signal, and frequency deviation pre-compensation device of the present invention is used for signal is made frequency deviation pre-compensation 105.After signal receives from antenna 100, through the frequency band gating in the Analog Baseband 101, power amplifier, become baseband signal after a series of processing such as down-conversion and intermediate frequency demodulation, become digital baseband signal through low-pass filtering 102 and modulus (AD) conversion 103 then, then it is carried out oversampling 104, carry out compensate of frequency deviation 105 by the I/Q data of frequency deviation pre-compensation device of the present invention after to oversampling, data after the compensation are offered cell search unit carry out Cell searching 111, it comprises slot synchronization 106, frame synchronization 107, main scrambler surveys 108, CPICH, CCPCH descrambling and de-spreading 109, the BCH decoding, frequency offset estimating, compensate of frequency deviation, channel estimating, tasks such as channel compensation 110.
Fig. 2 is the general structure block diagram of compensate of frequency deviation device of the present invention.Frequency deviation pre-compensation device of the present invention can comprise sine and cosine module 201, this coding module 202 of cloth, partial product module 203, compressor reducer array module 204, adder Module 205 etc.
Described sine and cosine module 201 is used to calculate the sine value and the cosine value of the anglec of rotation.
This coding module 202 of described cloth is used for above-mentioned sine value and cosine value are carried out this coding of cloth.
Described partial product module 203 is used for according to the result of this coding of cloth the I/Q data of importing being converted to partial product, wherein can comprise symbol compensation constant.
Described compressor reducer array module 204, it is long-pending to be used for compression section.
Described adder Module 205 is used for the summation of the partial product after the compression, and the I/Q data behind the output compensate of frequency deviation.
Fig. 3 is the internal circuit diagram of the compensate of frequency deviation device of a preferred embodiment of the present invention.
Described sine and cosine module 201 is made up of an address generator 211 and a programmable read only memory 221.Can comprise two counters in the address generator, first counter is according to parameter N sampling period of DSP component configuration, and carrying out with N under the effect of sampling clock is the saturation count of mould; Second counter is equally under the effect of sampling clock, is the saturation count of k as mould at first counter meter during to N, wherein k is an I/Q complex plane isodisperse, k is a positive integer, in this embodiment, supposing k=32, is that 0 o'clock work increases 1 counting at directioin parameter, is that 1 o'clock work subtracts 1 counting at directioin parameter; The count value of second counter is the address signal of real-time change then, exports programmable read only memory to.Programmable read only memory is used to deposit the sine value and the cosine value of 32 phase place correspondences, its bit wide is 12, the degree of depth is 32, Gao Liuwei deposits sine value, deposit cosine value for low six, address signal with address generator output carries out addressing, reads a sine value and a cosine value at each sampling clock rising edge.
Sine and cosine module 201 be ready to the anglec of rotation just/cosine value after, obtain signal real part and imaginary part behind the frequency deviation pre-compensation, common way is directly with 4 parallel monocycle multipliers and an adder, a subtracter constructing apparatus.The invention provides a kind of compensate of frequency deviation device, adopt this coding module 202 of cloth, partial product module 203, compressor reducer array module 204 and adder Module 205 structures to take advantage of the circuit that adds combination, help reducing hardware resource.
This coding module 202 of described cloth is made up of a complementer 212 and three booth encoders 222,232 and 242.Described three booth encoders 222,232 and 242 are the booth encoder of output " negate ", " adding 1 ", " taking advantage of 1 ", " taking advantage of 2 " four index signals.In order to convert subtraction to addition, complementer 212 is used for the sine value of sine and cosine module 201 outputs is asked opposite number, and the result exports booth encoder 222 to; The opposite number of booth encoder 1222 offset of sinusoidal values carries out this coding of cloth, and the result exports partial product maker 223 to; Can be advanced to this coding module 202 of cloth to the logic of negating of subtraction like this, avoid the subtraction of more bit wide.Booth encoder 232 offset of sinusoidal values are carried out this coding of cloth, and the result exports partial product maker 233 to; 242 pairs of cosine values of booth encoder carry out this coding of cloth, and the result exports partial product maker 213 and partial product maker 243 to.
Described partial product module 203 is made up of four partial product makers 213,223,233 and 243.Partial product maker 213 is according to this coding of cloth of cosine value and the I of input
nData generate four partial products, export 4-2 compressor reducer 214 to; Partial product maker 223 generates four partial products according to this coding of cloth of sine value opposite number and the Q data of input, exports 4-2 compressor reducer 224 to; Partial product maker 233 generates four partial products according to this coding of cloth of sine value and the I data of input, exports 4-2 compressor reducer 234 to; Partial product maker 243 generates four partial products according to this coding of cloth of cosine value and the Q data of input, exports 4-2 compressor reducer 244 to.Described partial product maker 213 is at first indicated according to " negate ", " taking advantage of 1 ", " taking advantage of 2 " of connected booth encoder 243 outputs, is 8 input data I by bit wide
nGenerate 3 bit wides and be 9 partial product A, B, C, then A, B, C are transformed: with the sign bit negate of A, B, C, 0 to 14 of high-order expansion, low level mends 0, generates 3 bit wides and be 14 partial product; The sign extended of A, B, C is then synthesized the 4th partial product V with " adding 1 " indicated value of this coding of cloth, also can become vectorial V,
V＝<101011000，X2，0，X1，0，X0>，
These 4 partial products output to the 4-2 compressor reducer 214 of its connection.Described partial product maker 223, partial product maker 233, partial product maker 243 produce the process of 4 partial products and partial product maker 1 respectively to produce the process of four partial products similar, do not repeat them here.
Described compressor reducer array module 204, form by two-stage 4-2 compressor reducer array, wherein 4-2 compressor reducer 214,4-2 compressor reducer 224,4-2 compressor reducer 234 and 4-2 compressor reducer 244 are formed first order array, and 4-2 compressor reducer 254 and 4-2 compressor reducer 264 are formed second level array.First order array exports 8 partial products of 16 partial product boil down tos of partial product module output to second level array; Second level array exports 4 partial products of 8 partial product boil down tos of first order array output to adder Module 205.
Described adder Module is made up of adder 215, adder 225 and register 235, register 245.Described adder can be complement adder, and certainly, it also can be the adder of other any suitable forms.Wherein, adder 215 is used for two partial products of 4-2 compressor reducer 254 outputs are sued for peace, and register 235 is clipped low 5 with the result of adder 215, postpones one and claps back output; Adder 225 is used for two partial products of 4-2 compressor reducer 264 output are sued for peace, and register 245 postpones one and claps back output after the result of adder 225 is clipped low 5; Register 235 output is a kind of compensate of frequency deviation device of the present invention the I data that receive is carried out x as a result behind the compensate of frequency deviation
n, register 245 is output as the Q data that receive is carried out y as a result behind the compensate of frequency deviation
n
The principle of frequency deviation pre-compensation method of the present invention is as follows: establishing frequency departure is Δ f, and then its phase deviation that brings is 2 π Δ ft, multiply by factor e to the received signal
-j2 π Δ ftThen can play the compensate of frequency deviation effect.Equally, for the digital baseband signal of WCDMA UE, the sampled signal of doing behind the frequency deviation pre-compensation is: x
n+ iy
n=(I
n+ iQ
n) * e
-j2 π Δ f (n/sc),
Wherein c is the spreading rate of WCDMA, and s is the oversampling rate of baseband signal, and 0≤n≤N is the i/q signal distributed points in time after sampling.
For a certain initial frequency deviation, being reflected in time domain is that phase shift changes between 0～2 π in time, if directly calculate with aforementioned formula, may need to calculate the sine value and the cosine value of all angles of 0～2 π, on circuit, be difficult to realize that required complex multiplier also will take very big hardware resource.For this reason, the method that the present invention adopts a kind of piecewise approximation phase place rotation and tables look-up, so-called piecewise approximation phase place rotation, be that the I/Q complex plane is divided into the k section, phase shift approximately equal in each section, be fixed as 2 π/k, by 2 π/k=2 π Δ fnT as can be known, n sampling period T time in signal all carry out the purpose that opposite spin 2 π/k can reach compensate of frequency deviation, like this no matter how many frequency deviation Δ f is, all only need carry out the positive and negative rotation of 2 π/k and multiple thereof, just do the duration difference of same rotation, thus simplification device.The number k of segmentation can not be excessive, can cause that like that the hardware resources such as table of storage are excessive, calculates too frequently to cause power consumption to increase; Can not be too small, and cause the precision that compensates not enough, even cause inappropriate compensation.We have chosen 32 sections and have carried out the phase place rotation compensation in this embodiment.Compensate of frequency deviation device of the present invention is only realized the precompensation at initial frequency deviation, and frequency offset estimating and compensate of frequency deviation after finishing as for Cell searching need comparison complex calculations such as division, are finished by the DSP parts among the UE.
A preferred embodiment of the present invention that WCDAM UE baseband signal is carried out the step of frequency deviation pre-compensation 105 is as follows:
The first step, the I/Q complex plane is divided into the k section, k is a positive integer, in this embodiment, suppose k=32, directioin parameter and the real-time calculated address signal of parameter sampling period by the DSP component configuration of utilizing UE, utilize this address signal to carry out addressing, read a sine value and a cosine value from each sampling clock rising edge, finally obtain the sine value sin (Δ θ) and the cosine value cos (Δ θ) of k the anglec of rotation, and this k sine value and cosine value are carried out 6 quantifications, wherein, above-mentioned sine value and cosine value, and the sine value after quantizing and cosine value are as shown in Figure 4, sine value after the quantification and cosine value are deposited in the programmable read only memory 221.
In second step, foregoing sampled signal formula is splitted into real part and imaginary part, that is:
x
n＝I
n*cos(Δf)-Q
n*sin(Δf)
y
n＝I
n*sin(Δf)+Q
n*cos(Δf)
By the calculating of above two formulas, obtain the signal real part x behind the compensate of frequency deviation
nWith imaginary part y
n
Operation in the above-mentioned first step can be realized by sine and cosine module 201.In the first step, (0≤n≤N) frequency deviation of individual sample point is Δ f to n, because the spreading rate c of WCDMA is 3.84M, the oversampling rate s of Cai Yonging is 4 in this embodiment, relational expression 2 π/32=2 π Δ f (N/sc) by frequency deviation and phase shift, draw received signal and be parameter N sampling period of same rotation=480/ Δ f, wherein, Δ f is that unit is the frequency deviation of kHz, provide simultaneously the directioin parameter of phase place rotation according to the frequency deviation direction, if frequency deviation for just, directioin parameter is 1, if frequency deviation is for negative, directioin parameter is 0.This process can UE the DSP parts realize, directly accept by sine and cosine module 201 the DSP configuration the phase place rotation directioin parameter and sampling period parameter get final product.
Consider identical multiplier is arranged in the multiplication, be cos (Δ θ) and sin (Δ θ), so a kind of frequency deviation pre-compensation method of the present invention adopts this coding module 202 of cloth, partial product module 203, compressor reducer array module 204 and adder Module 205 to unify to finish the calculating of above two formulas.Computational process may further comprise the steps:
The first step, to just reading from programmable read only memory 221, cosine value carries out this coding of cloth;
In second step, according to this coding of cloth, long-pending by I/Q data generating portion, it can be 16 or other suitable numbers, can comprise symbol compensation constant in the partial product, for example is 4;
In the 3rd step, with above-mentioned partial product, for example 4 symbols of 12 partial-product sums compensate constant with two-stage 4-2 compressor reducer array, and boil down to is a plurality of, for example is 4 vectors;
The 4th step, obtain the result of above-mentioned two formulas, by clip its method of low 5 offset align, cosine value carries out the influence of 6 quantifications, thereby obtains the I/Q data behind the compensate of frequency deviation.
The above-mentioned first step can be realized that second step can be realized that the 3rd step can be realized that the 4th step can be realized by adder Module 205 by compressor reducer array module 204 by partial product module 203 by this coding module 202 of cloth.Certainly, if necessary, more than each step also can realize by other module of any appropriate or the devices that can finish this function.
Certainly; the present invention also can have other embodiment; under the situation that does not deviate from spirit of the present invention and essence thereof; the person of ordinary skill in the field works as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (10)
1. Wideband Code Division Multiple Access (WCDMA) subscriber equipment frequency deviation pre-compensation device, it is characterized in that, comprise the sine and cosine module that is linked in sequence successively, this coding module of cloth, the partial product module, compressor reducer array module and adder Module, above-mentioned sine and cosine module is used to calculate the sine value and the cosine value of the anglec of rotation; This coding module of above-mentioned cloth is used for above-mentioned sine value and cosine value are carried out this coding of cloth; Above-mentioned partial product module is used for according to the result of above-mentioned this coding of cloth the I/Q data of importing being converted to partial product; The said compressor array module is used to compress above-mentioned partial product; Above-mentioned adder Module is used for summation of the partial product after the compression and output.
2. frequency deviation pre-compensation device according to claim 1, it is characterized in that, above-mentioned sine and cosine module comprises interconnective address generator and programmable read only memory at least, the address signal of directioin parameter that above-mentioned address generator basis has disposed and parameter generation sampling period real-time change also exports above-mentioned programmable read only memory to, above-mentioned programmable read only memory is according to above-mentioned address signal addressing, read a sine value and a cosine value of storage in advance at the rising edge of each sampling clock, and export it to above-mentioned cloth this coding module.
3. frequency deviation pre-compensation device according to claim 1 and 2, it is characterized in that, this coding module of above-mentioned cloth comprises a plurality of booth encoders and the complementer that is connected with a booth encoder at least, above-mentioned complementer is negated to the sine value of above-mentioned sine and cosine module output and is exported the result of sine value opposite number to booth encoder, above-mentioned a plurality of booth encoder offset of sinusoidal value opposite number, sine value and cosine value respectively carries out this coding of cloth, and exports the result to the partial product module.
4. frequency deviation pre-compensation device according to claim 3 is characterized in that, above-mentioned partial product module comprises that at least a plurality of independent parts amass maker, and the I/Q data of input are converted to partial product and export compressor reducer to.
5. frequency deviation pre-compensation device according to claim 1 is characterized in that, the said compressor array module comprises the compressor reducer array of being made up of a plurality of compressor reducers at least.
6. frequency deviation pre-compensation device according to claim 5 is characterized in that, the multistage arrangement of said compressor array is used for data are repeatedly compressed.
7. frequency deviation pre-compensation device according to claim 5, it is characterized in that, above-mentioned adder Module comprises a plurality of adders and a plurality of register at least, and above-mentioned adder is to the summed result of compressor reducer array module output, and the above-mentioned summed result of register pair is handled and output.
8. a Wideband Code Division Multiple Access (WCDMA) subscriber equipment frequency deviation pre-compensation method is characterized in that, may further comprise the steps:
Step 1 provides a kind of frequency deviation pre-compensation device as claimed in claim 1;
Step 2, in the sine and cosine module, utilize subscriber equipment the Digital Signal Processing component configuration the rotation of above-mentioned phase place directioin parameter and sampling period parameter generate the address signal of real-time change, utilize above-mentioned address signal to carry out addressing, obtain a plurality of sine values and cosine value and carry out quantification treatment, storage computation result also exports it to cloth this coding module;
Step 3 is carried out this coding of cloth and is exported the partial product module to the aforementioned calculation result in this coding module of cloth;
The compressor reducer array module is amassed and exported to step 4 according to this coding of above-mentioned cloth with the I/Q data generating portion of input in the partial product module;
Step 5, in the compressor reducer array module with the compression of above-mentioned partial product and export adder Module to;
Step 6 is sued for peace to above-mentioned partial product in adder Module, and carries out exporting after cut position postpones.
9. frequency deviation pre-compensation method according to claim 8, it is characterized in that, the phase place rotation of carrying out onesize and direction in the time of N sampling period to received signal compensates, parameter sampling period of phase place rotation draws according to the relational expression 2 π/k=2 π Δ f (N/sc) of frequency deviation and phase shift, wherein k is an I/Q complex plane segments, and Δ f is a frequency departure, and c is the spreading rate of Wideband Code Division Multiple Access (WCDMA), s is the oversampling rate of baseband signal, and N is parameter sampling period; Simultaneously, if Δ f for just, directioin parameter is 1, if Δ f for negative, directioin parameter is 0.
10. frequency deviation pre-compensation method according to claim 8 is characterized in that, in the partial product compression process, can repeatedly compress above-mentioned partial product.
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| CN102026277A (en) * | 2009-09-22 | 2011-04-20 | 中国移动通信集团公司 | Method, base station and user terminal for sending and receiving data |
| CN104702364A (en) * | 2013-12-10 | 2015-06-10 | 华为技术有限公司 | Clock frequency adjustment method and clock frequency adjustment device |
| CN105843106A (en) * | 2015-01-12 | 2016-08-10 | 深圳市中兴微电子技术有限公司 | Dedicated digital signal processor and device and method for achieving data interaction and conversion therefor |
| CN106161306A (en) * | 2016-07-05 | 2016-11-23 | 福州瑞芯微电子股份有限公司 | A kind of Fast Frequency Offset method of adjustment and device |
| CN106603454A (en) * | 2016-11-23 | 2017-04-26 | 深圳市国电科技通信有限公司 | GFSK digital double-channel demodulation method |
| CN107579941A (en) * | 2012-02-24 | 2018-01-12 | 美国国家仪器有限公司 | Measurement is detracted for the mechanism of I/Q detraction corrections and using the transmitter for offseting local oscillator |
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| KR0142943B1 (en) * | 1995-06-20 | 1998-08-01 | 김광호 | Cdma |
| CN100518157C (en) * | 2004-08-17 | 2009-07-22 | 中兴通讯股份有限公司 | Method and device for frequency deviation compensation of mobile communication system |
| US7486749B2 (en) * | 2004-12-22 | 2009-02-03 | Nokia Corporation | Determination of a code phase |
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| CN106161306A (en) * | 2016-07-05 | 2016-11-23 | 福州瑞芯微电子股份有限公司 | A kind of Fast Frequency Offset method of adjustment and device |
| CN106161306B (en) * | 2016-07-05 | 2019-02-01 | 福州瑞芯微电子股份有限公司 | A kind of Fast Frequency Offset method of adjustment and device |
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