CN104702364A - Clock frequency adjustment method and clock frequency adjustment device - Google Patents
Clock frequency adjustment method and clock frequency adjustment device Download PDFInfo
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- CN104702364A CN104702364A CN201310671523.4A CN201310671523A CN104702364A CN 104702364 A CN104702364 A CN 104702364A CN 201310671523 A CN201310671523 A CN 201310671523A CN 104702364 A CN104702364 A CN 104702364A
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Abstract
The invention discloses a clock frequency adjustment method and a clock frequency adjustment device. The clock frequency adjustment method includes: monitoring clock frequency of network equipment, wherein a processor of the network equipment comprises M GPIOs (general-purpose input and output) and used for adjusting the clock frequency of the network equipment, and M refers to an integer larger than 1; if the clock frequency of the network equipment is in negative-frequency deviation, controlling the M GPIOs to change input voltage of a voltage-controlled oscillator of the network equipment so as to adjust the clock frequency of the network equipment. The clock frequency adjustment method and the clock frequency adjustment device have the advantage that packet dropping probability of the network equipment in relative negative-frequency deviation can be decreased.
Description
Technical field
The embodiment of the present invention relates to the communication technology, particularly relates to a kind of clock frequency method of adjustment and device.
Background technology
In ethernet environment, each network equipment adopts local clock as the clock source of data acquisition and transmission usually.The local clock of the current network equipment uses crystal oscillator to realize; Most of crystal oscillator is the inclined reference clock of zero-frequency.But due to the impact of load capacitance, crystal oscillator may show as negative frequency deviation.When clock frequency between the network equipment of message transmission is asynchronous, there is frequency difference in the crystal oscillator that namely each network equipment of message transmission adopts, such as, when the clock frequency of a network equipment is greater than the clock frequency of another network equipment, the network equipment that clock frequency is less is in negative frequency deviation, and can cause the phenomenon that abandons.In prior art, General Requirements clock frequency difference can meet 802.3 protocol requirements, and namely clock difference on the frequency is within +/-50PPM.
Normally customize the crystal oscillator of compatible fixing positive frequency deviation 25PPM at present, then the artificial crystal oscillator with this fixing positive frequency deviation 25PPM replaces the crystal oscillator being in the network equipment of negative frequency deviation, causes human cost and equipment cost to increase like this.
Summary of the invention
The invention provides a kind of clock frequency method of adjustment and device, in order to reduce the packet loss phenomenon caused because the network equipment is in negative frequency deviation.
A first aspect of the present invention provides a kind of clock frequency method of adjustment, it is characterized in that, comprising:
The clock frequency of monitor network equipment, the processor of the described network equipment comprises M universal input and exports GPIO, for adjusting the clock frequency of the described network equipment, wherein M be more than or equal to 1 integer;
If the clock frequency of the described network equipment is in negative frequency deviation, then control the input voltage that a described M GPIO changes the voltage controlled oscillator of the described network equipment, to adjust the clock frequency of the described network equipment.
In conjunction with first aspect, may in implementation in the first of first aspect, described M be more than or equal to 2 integer;
Correspondingly, the input voltage that the described M of a described control GPIO changes the voltage controlled oscillator of the described network equipment comprises:
Obtain the message amount in the buffer memory of the port of the described network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of described port, and be less than the second buffer threshold, the GPIO controlled in a described M GPIO exports high level, in a described M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of described voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a described GPIO is in parallel with described first divider resistance by adjusting resistance.
May implementation in conjunction with the first of first aspect and first aspect, may in implementation at the second of first aspect, the clock frequency of described monitor network equipment comprises:
The buffer memory of the port of the described network equipment of real-time detection;
If there is message in the buffer memory of described port, then obtain the instantaneous delivery bandwidth of described port;
If the instantaneous delivery bandwidth of described port exceedes default port bandwidth threshold value, then judge that the clock frequency of the described network equipment is in negative frequency deviation.
In conjunction with the second possibility implementation of first aspect, in the third possibility implementation of first aspect, obtain the instantaneous delivery bandwidth of described port, comprising:
Obtain the reception packet counting value of described port when current period starts and the reception packet counting value at the end of current period;
According to described reception packet counting value when current period starts and described reception packet counting value at the end of current period, obtain the message amount that described port receives in current period, the message amount received in described current period equals described reception packet counting value at the end of current period and deducts the described reception packet counting value when current period starts;
According to the described message amount received in current period, obtain the instantaneous delivery bandwidth of described port, the instantaneous delivery bandwidth of described port equals the value of the described message amount received in current period divided by the duration gained of described current period.
In conjunction with the second possibility implementation of first aspect, in the 4th kind of possibility implementation of first aspect, also comprise:
If there is not message in the buffer memory of described port, judge whether the clock frequency of the described network equipment does overdeviation adjustment;
If the clock frequency of the described network equipment does overdeviation adjustment, the clock frequency of the described network equipment is returned to normal frequency.
Second aspect present invention provides a kind of clock frequency adjusting device, comprising:
Monitoring module, for the clock frequency of monitor network equipment, the processor of the described network equipment comprises M universal input and exports GPIO, for adjusting the clock frequency of the described network equipment, wherein M be more than or equal to 1 integer;
Adjusting module, if it is determined that be in negative frequency deviation for the clock frequency of the described network equipment, then controls the input voltage that a described M GPIO changes the voltage controlled oscillator of the described network equipment, to adjust the clock frequency of the described network equipment.
In conjunction with second aspect, may in implementation in the first of second aspect, described M be more than or equal to 2 integer;
Described adjusting module specifically for:
Obtain the message amount in the buffer memory of the port of the described network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of described port, and be less than the second buffer threshold, the GPIO controlled in a described M GPIO exports high level, in a described M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of described voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a described GPIO is in parallel with described first divider resistance by adjusting resistance.
May implementation in conjunction with the first of second aspect and second aspect, may in implementation at the second of second aspect, described monitoring module specifically for:
The buffer memory of the port of the described network equipment of real-time detection;
If there is message in the buffer memory of described port, then obtain the instantaneous delivery bandwidth of described port;
If the instantaneous delivery bandwidth of described port exceedes default port bandwidth threshold value, then judge that the clock frequency of the described network equipment is in negative frequency deviation.
The second in conjunction with second aspect may implementation, may in implementation at the third of second aspect, described monitoring module specifically for:
Obtain the reception packet counting value of described port when current period starts and the reception packet counting value at the end of current period;
According to described reception packet counting value when current period starts and described reception packet counting value at the end of current period, obtain the message amount that described port receives in current period, the message amount received in described current period equals described reception packet counting value at the end of current period and deducts the described reception packet counting value when current period starts;
According to the described message amount received in current period, obtain the instantaneous delivery bandwidth of described port, the instantaneous delivery bandwidth of described port equals the value of the described message amount received in current period divided by the duration gained of described current period.
The second in conjunction with second aspect may implementation, may in implementation at the 4th kind of second aspect, described monitoring module also for:
If there is not message in the buffer memory of described port, judge whether the clock frequency of the described network equipment does overdeviation adjustment;
Correspondingly, if described adjusting module also does overdeviation adjustment for the clock frequency of the described network equipment, the clock frequency of the described network equipment is returned to normal frequency.
By the flow bandwidth of the port of monitor network equipment, the present invention judges whether the clock frequency of the described network equipment exists negative frequency deviation, when there is negative frequency deviation in the clock frequency of the described network equipment, by changing the input voltage of the voltage controlled oscillator of the described network equipment, thus achieve the clock frequency of the dynamic conditioning network equipment, decrease the phenomenon of packet loss on the network equipment owing to being in relative negative frequency deviation.
Accompanying drawing explanation
The clock frequency method of adjustment flow chart that Fig. 1 provides for the embodiment of the present invention;
The flow chart of the monitoring clock frequency that Fig. 2 provides for the embodiment of the present invention;
The GPIO of the processor that Fig. 3 A provides for the embodiment of the present invention and the connection diagram of voltage controlled oscillator;
Another clock frequency method of adjustment flow chart that Fig. 3 B provides for the embodiment of the present invention;
The clock frequency adjusting device structural representation that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the network equipment that Fig. 5 provides for the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The clock frequency method of adjustment flow chart that Fig. 1 provides for the embodiment of the present invention, the crystal oscillator being applicable to the network equipment is voltage controlled oscillator, and method comprises the steps:
Step 101, the clock frequency of monitor network equipment.
Wherein, the processor of the network equipment comprises M GPIO(General Purpose Input Output, universal input export), for adjusting the clock frequency of the network equipment, wherein M be more than or equal to 1 integer.
Processor can be central processing unit (central processing unit is called for short CPU).
The so-called negative frequency deviation of the present embodiment is comparatively speaking, for example, when clock frequency between two network equipments carrying out message transmissions is asynchronous, the clock frequency that can there is a network equipment is greater than the situation of the clock frequency of another network equipment, now, the clock frequency of the network equipment that clock frequency is less is in negative frequency deviation.
As shown in Figure 2, this step 101 specifically can comprise the steps:
Step 201, whether the buffer memory detecting the port of this network equipment in real time exists message, if there is message in the buffer memory of port, performs step 202, otherwise, perform step 205.
In the present embodiment, the quantity being detected message in the buffer memory of the port of this network equipment by timer in real time learns in the buffer memory of the port of this network equipment whether there is message, when in the buffer memory of the port of this network equipment, the quantity of message is more than or equal to 1, message is there is in the buffer memory of the port of this network equipment, then perform step 202, when in the buffer memory of the port of this network equipment, the quantity of message is 0, message is there is not in the buffer memory of the port of this network equipment, then judge whether the clock frequency of this network equipment does overdeviation adjustment, when the clock frequency of this network equipment does overdeviation adjustment, clock frequency is returned to normal frequency, when the clock frequency of this network equipment does not do overdeviation adjustment, do not adjust clock frequency.
Step 202, obtains the instantaneous delivery bandwidth of port.
In the present embodiment, detected after there is message in the buffer memory of the port of this network equipment by step 201, obtaining the instantaneous delivery bandwidth of the port of this network equipment, can be specifically the instantaneous delivery bandwidth calculating the port of this network equipment according to the message amount of the port of this network equipment.
This step 202 specifically comprises the steps:
Obtain the reception packet counting value of this port when current period starts and the reception packet counting value at the end of current period;
According to the reception packet counting value when current period starts and the reception packet counting value at the end of current period, obtain the message amount that this port receives within the current cycle, the message amount received in the current period reception packet counting value equaled at the end of current period deducts the reception packet counting value when current period starts;
According to the message amount received in current period, obtain the instantaneous delivery bandwidth of port, the instantaneous delivery bandwidth of port equals the message amount that receives in the current period value divided by the duration gained of current period.
In the present embodiment, suppose that the reception packet counting value of the port of this network equipment before current period starts is P
1, the reception packet counting value at the end of current period is P
2, the message amount that the port of this network equipment receives in current period is P, then P=P
2-P
1, the reception packet counting value when message amount that namely port of this network equipment receives in current period equals this current end cycle deduct connect when this current period starts receive packet counting value.Suppose that the interval time of timer is T, that is, when the duration of current period is T, the instantaneous delivery bandwidth of the port of this network equipment is B, therefore, and B=(P
2-P
1) T, namely the instantaneous delivery bandwidth of the port of this network equipment message amount that equals to receive in this current period is divided by the value of the duration gained of current period, so just can be calculated the instantaneous delivery bandwidth of the port of this network equipment by message amount.
The technical scheme of the present embodiment, obtains the instantaneous delivery bandwidth of the port of this network equipment by the message amount detected in the buffer memory of the port of this network equipment.
Step 203, judges whether this instantaneous delivery bandwidth exceedes default port bandwidth thresholding, if so, performs step 204, otherwise, perform step 205.
Generally, the thresholding of this default port bandwidth can be arranged by User Defined.In the present embodiment, by the instantaneous delivery bandwidth B of port having obtained this network equipment in step 202, the instantaneous delivery bandwidth B of the port of this network equipment and the thresholding of default port bandwidth are compared, judge whether the instantaneous delivery bandwidth of this port exceedes the thresholding of default port bandwidth, if exceed, then perform step 204, if be no more than, then perform step 205.
Step 204, determines that the clock frequency of this network equipment is in negative frequency deviation.
Step 205, determines that the clock frequency of this network equipment is not in negative frequency deviation.
In the present embodiment, if judged that by step 203 the instantaneous delivery bandwidth of the port of this network equipment exceedes default port bandwidth thresholding, then determine that the clock frequency of this network equipment is in negative frequency deviation, if judged that by step 203 the instantaneous delivery bandwidth of the port of this network equipment does not exceed default port bandwidth thresholding, then determine that the clock frequency of this network equipment is not in negative frequency deviation.
Step 102, if the clock frequency of this network equipment is in negative frequency deviation, then control M GPIO changes the input voltage of the voltage controlled oscillator of this network equipment, to adjust the clock frequency of this network equipment.
In the present embodiment, the crystal oscillator of the network equipment is voltage controlled oscillator, and there is certain relation between the output frequency of voltage controlled oscillator and input voltage, the output frequency of usual voltage controlled oscillator increases with the increase of input voltage.Therefore, when judging that the clock frequency of this network equipment is in negative frequency deviation by step 101, by changing the input voltage of the voltage controlled oscillator of this network equipment, the object of the clock frequency of this network equipment of adjustment can be reached.
The technical scheme of the present embodiment, whether negative frequency deviation can be in by the clock frequency of timer monitor network equipment, in time being in negative frequency deviation, adjusted the clock frequency of this network equipment by the input voltage of the voltage controlled oscillator changing this network equipment, decrease be in relative negative frequency deviation the network equipment on the phenomenon of packet loss.
Further alternatively, M be more than or equal to 2 integer; Correspondingly, the input voltage of the voltage controlled oscillator of described control M the GPIO change network equipment comprises:
Obtain the message amount in the buffer memory of the port of the network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of port, and be less than the second buffer threshold, a GPIO in a control M GPIO exports high level, in M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a GPIO is in parallel with the first divider resistance by adjusting resistance.
In the embodiment of the present invention, the processor of the network equipment can comprise M GPIO(GeneralPurpose Input Output, universal input export), for carrying out multistage adjustment to the clock frequency of the network equipment, wherein M be more than or equal to 1 integer.
As M=1, namely represent that processor has a GPIO, a such as GPIO.Now, if the buffer memory message amount of the port of the network equipment is greater than the first buffer threshold, and when being less than the second buffer threshold, one GPIO can be set to export high level, if the buffer memory message amount of the port of the network equipment is less than the first buffer threshold, then a GPIO is set to input state.
The structural representation of the partial network devices that Fig. 3 A provides for the embodiment of the present invention, comprises two GPIO for the processor of this network equipment.As shown in Figure 3A, two GPIO of processor are respectively GPIO1 and GPIO2, and VDD is that the power pin of voltage controlled oscillator is (English: pin), GND is ground pin; Output is clock frequency output pin, clock signal (CLOCK); VCON is voltage control pin, is connected to supply power voltage VCC by the first divider resistance R, and by the second divider resistance R ' ground connection, the first divider resistance R and the second divider resistance R ' connects.With R=R '=4.7 ohm (Ω) in the present embodiment, R
1=R
2=10 Ω are that example is described.The resistance of certain R and R ' also can not wait, R
1and R
2resistance also can not wait, specifically can set according to actual needs, not limit in the present embodiment.
For example, initial time, when GPIO1 and GPIO2 is input state, when namely GPIO1 and GPIO2 is high-impedance state, R
1and R
2inoperative, represent the input voltage not changed the voltage controlled oscillator of this network equipment by GPIO1 and GPIO2, also namely the clock frequency of the network equipment is not adjusted.Now the voltage of voltage control pin VCON is
suppose that the output frequency of voltage controlled oscillator is 25MHz+/-100PPM, wherein, 25MHz is the frequency of desired output, and +/-100PPM is the error range of output frequency.
If the clock frequency next monitoring this network equipment is in negative frequency deviation, then control GPIO1 or GPIO2 exports high level, and such as GPIO1 exports high level, and GPIO2 is still input state.Suppose that the output voltage of GPIO1 is V
g, suppose, then the voltage of voltage control pin VCON raises
namely the voltage of voltage control pin VCON is
because the input voltage of voltage controlled oscillator is larger, output frequency is larger, and therefore the output frequency of voltage controlled oscillator is along with the voltage increased
increase, suppose to increase 25PPM, the output frequency of the voltage controlled oscillator like this after adjustment is (25MHz+25PPM) +/-100PPM.
If the clock frequency next monitoring this network equipment is still in negative frequency deviation, then when control GPIO1 and GPIO2 exports high level, then the voltage of voltage control pin VCON raises again
for
correspondingly, the output frequency of voltage controlled oscillator increases 25PPM again, and now, the output frequency of voltage controlled oscillator is (25MHz+50PPM) +/-100PPM.
On the basis of above-described embodiment, when the clock frequency of this network equipment is in negative frequency deviation, by controlling the output level of the GPIO of the processor of this network equipment, change the input voltage of the voltage controlled oscillator of this network equipment, the clock frequency of multistage this network equipment of adjustment.Concrete steps comprise: obtain the message amount in the buffer memory of the port of the network equipment; If message amount is greater than the first buffer threshold in the buffer memory of port, and be less than the second buffer threshold, a GPIO in a control M GPIO exports high level, in M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a GPIO is in parallel with the first divider resistance by adjusting resistance.In the present embodiment, the clock frequency difference of this network equipment after multistage adjustment can meet predeterminated frequency difference, such as, can meet 802.3 protocol requirements, and clock frequency difference is within +/-50PPM.This clock frequency difference refers to the difference of the clock frequency between the network equipment of multistage adjustment and an other network equipment.
Next, concrete composition graphs 3A is illustrated technical solution of the present invention.See Fig. 3 B, be the clock frequency method of adjustment flow chart that the embodiment of the present invention provides, method comprises:
Step 301, identifies the message amount in the buffer memory of the port of this network equipment.
Namely this step identifies that clock frequency is in the message amount in the buffer memory of the port of the network equipment of negative frequency deviation, and message amount is assumed to be p.
Step 302, identifies whether the quantity of message in the buffer memory of the port of this network equipment is greater than the first buffer threshold.
Buffer threshold is set, in the present embodiment for two-level cache thresholding, supposes that the first buffer threshold is p
1, the second buffer threshold is p
2, wherein, p
1<p
2.Whether the quantity p that identification clock frequency is in message in the buffer memory of the port of the network equipment of negative frequency deviation is greater than the first buffer threshold p
1, when being greater than the first buffer threshold p
1time, perform step 304, when being not more than the first buffer threshold p
1time, perform step 303.
Step 303, is set to input state entirely by GPIO;
It is pointed out that if in advance GPIO is all set to input state, so now step 303 is for keeping GPIO to be all input state.
In the buffer memory of the port of the network equipment, the quantity p of message is not more than the first buffer threshold p
1time, show that the clock frequency of this network equipment is in preset range, do not need to carry out frequency adjustment, then the GPIO making connection voltage-controlled oscillator voltage control pin VCON is input state entirely.
Step 304, identifies in the buffer memory of the port of this network equipment, whether message amount is greater than the second buffer threshold;
P when the buffer memory message amount p identifying the port of this network equipment is in step 302 greater than the first buffer threshold
1, this step identifies whether the buffer memory message amount p of the port of this network equipment is greater than the second buffer threshold p again
2, work as p>p
2time, perform step 306, as p≤p
2time, perform step 305.
Step 305, be set to by 1 GPIO export high level, all the other GPIO are set to input state;
When identifying p
1<p≤p
2, make 1 GPIO in the GPIO be connected with the voltage control pin VCON of voltage controlled oscillator export high level, all the other GPIO are input state.Such as, in Fig. 3 A, be set to by GPIO1 export high level, then GPIO2 keeps input state.
2 GPIO are set to export high level by step 306.
It will be understood by those skilled in the art that can according to the actual service condition setting progression of buffer threshold and the number of the GPIO in parallel with the voltage control pin of voltage controlled oscillator, and the present invention does not repeat them here.
The technical scheme of the present embodiment, the voltage control pin VCON of at least one GPIO and voltage controlled oscillator is being passed through on the signal wiring basis of resistor coupled in parallel, by setting the buffer threshold of message amount, identify the rank that the quantity of message in the buffer memory of the port of this network equipment reaches, the GPIO of corresponding number in the GPIO be connected with the voltage control pin VCON of voltage controlled oscillator is made to export high level, all the other are input state, reach the effect of multistage dynamic conditioning network equipment clock frequency, the phenomenon of packet loss on the network equipment being in relative negative frequency deviation can be reduced further.
The structural representation of the clock frequency adjusting device that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, described device comprises monitoring module 41 and adjusting module 42.
Wherein, monitoring module 41 is for monitoring the clock frequency of this network equipment, and the processor of the network equipment comprises M universal input and exports GPIO, for adjusting the clock frequency of the network equipment, wherein M be more than or equal to 1 integer; If adjusting module 42 is in negative frequency deviation for the clock frequency of this network equipment, then control M GPIO, changes the input voltage of the voltage controlled oscillator of this network equipment, to adjust the clock frequency of this network equipment.
Particularly, monitoring module 41 can work as the clock frequency monitoring the network equipment when being in negative frequency deviation, trigger adjusting module 42, or monitored results is sent to adjusting module 42 by frequency deviation monitoring module 41, when being in negative frequency deviation to make adjusting module 42 according to the clock frequency that monitored results identifies the network equipment, change the input voltage of the voltage controlled oscillator of this network equipment, adjust the clock frequency of this network equipment.
Alternatively, M be more than or equal to 2 integer, adjusting module 42 specifically for:
Obtain the message amount in the buffer memory of the port of the network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of port, and be less than the second buffer threshold, a GPIO in a control M GPIO exports high level, in M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a GPIO is in parallel with the first divider resistance by adjusting resistance.
Particularly, monitoring module 41 for:
The buffer memory of the port of real-time Sampling network equipment;
If there is message in the buffer memory of port, then obtain the instantaneous delivery bandwidth of port;
If the instantaneous delivery bandwidth of port exceedes default port bandwidth threshold value, then the clock frequency of decision network equipment is in negative frequency deviation.
More specifically, monitoring module 41 for:
Obtain the reception packet counting value of port when current period starts and the reception packet counting value at the end of current period;
According to the reception packet counting value when current period starts and the reception packet counting value at the end of current period, obtain the message amount that port receives in current period, the message amount received in the current period reception packet counting value equaled at the end of current period deducts the reception packet counting value when current period starts;
According to the message amount received in current period, obtain the instantaneous delivery bandwidth of port, the instantaneous delivery bandwidth of port equals the message amount that receives in the current period value divided by the duration gained of current period.
Wherein, monitoring module 41 also for:
If there is not message in the buffer memory of port, judge whether the clock frequency of the network equipment does overdeviation adjustment;
Correspondingly, if adjusting module also does overdeviation adjustment for the clock frequency of the network equipment, the clock frequency of the network equipment is returned to normal frequency; If the clock frequency of keeping equipment does not do overdeviation adjustment, then do not adjust clock frequency.
The technical scheme of the present embodiment, whether message is there is by the buffer memory that detects the port of this network equipment, when there is message, obtain the instantaneous delivery bandwidth of the port of this network equipment, and whether exceed default port bandwidth thresholding according to this instantaneous delivery bandwidth and judge whether the clock frequency of this network equipment is in negative frequency deviation, thus know whether this network equipment may exist the phenomenon of packet loss.
The technical scheme of the present embodiment, whether the clock frequency being monitored this network equipment by monitoring module 41 is in negative frequency deviation, the input voltage being in the voltage controlled oscillator of the network equipment of negative frequency deviation is changed again through adjusting module 42, adjust the clock frequency of this network equipment, decrease be in relative negative frequency deviation the network equipment on the phenomenon of packet loss.
On the basis of above-described embodiment, alternatively, this adjusting module 42, by controlling the output level of the GPIO of the CPU of this network equipment, changes the input voltage of the voltage controlled oscillator of this network equipment, the clock frequency of multistage this network equipment of adjustment.
Present invention also offers a kind of network equipment, as shown in Figure 5, comprising: at least one processor 601, and memory 602, also comprise voltage controlled oscillator 603; Memory 602, for depositing program.Particularly, program can comprise program code, and program code comprises computer-managed instruction.Described processor 601 can be connected by bus or other modes with described memory 602, to be connected by bus in Fig. 5.Connected mode between processor 601 and voltage controlled oscillator 603 specifically can reference diagram 3A, certainly can also have other connected mode, not limit in the present embodiment.
The program stored in processor 601 execute store 602, realizes the clock frequency method of adjustment that the embodiment of the present invention provides, comprising:
The clock frequency of monitor network equipment, the processor of the network equipment comprises M universal input and exports GPIO, for adjusting the clock frequency of the network equipment, wherein M be more than or equal to 1 integer;
If the clock frequency of the network equipment is in negative frequency deviation, then control M GPIO, changes the input voltage of the voltage controlled oscillator 603 of the network equipment, to adjust the clock frequency of the network equipment.
Alternatively, M be more than or equal to 2 integer, then a described control M GPIO, the input voltage of voltage controlled oscillator 603 changing the network equipment comprises:
Obtain the message amount in the buffer memory of the port of the network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of port, and be less than the second buffer threshold, a GPIO in a control M GPIO exports high level, in M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a GPIO is in parallel with the first divider resistance by adjusting resistance.
Alternatively, the clock frequency of described monitor network equipment, comprising:
The buffer memory of the port of real-time Sampling network equipment;
If there is message in the buffer memory of the port of the network equipment, then obtain the instantaneous delivery bandwidth of port;
If the instantaneous delivery bandwidth of port exceedes default port bandwidth threshold value, then the clock frequency of decision network equipment is in negative frequency deviation.
Alternatively, the instantaneous delivery bandwidth of described this port of acquisition, comprising:
Obtain the reception packet counting value of port when current period starts and the reception packet counting value at the end of current period;
According to the reception packet counting value when current period starts and the reception packet counting value at the end of current period, obtain the message amount that port receives in current period, the message amount received in the current period reception packet counting value equaled at the end of current period deducts the reception packet counting value when current period starts;
According to the message amount received in current period, obtain the instantaneous delivery bandwidth of port, the instantaneous delivery bandwidth of port equals the message amount that receives in the current period value divided by the duration gained of current period.
Alternatively, described clock frequency method of adjustment also comprises:
If there is not message in the buffer memory of port, judge whether the clock frequency of the network equipment does overdeviation adjustment;
If the clock frequency of the network equipment does overdeviation adjustment, the clock frequency of the network equipment is returned to normal frequency.
In the present embodiment, only describe the structure that the network equipment is related to the present invention, the described network equipment can also comprise other devices, does not limit this present invention.
The network equipment of the embodiment of the present invention, whether negative frequency deviation is in by the clock frequency monitoring this network equipment, again through changing the input voltage being in the voltage controlled oscillator of the network equipment of negative frequency deviation, adjust the clock frequency of this network equipment, decrease be in relative negative frequency deviation the network equipment on the phenomenon of packet loss.
It should be noted that: for aforesaid each embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not by the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in specification all belongs to preferred embodiment, and involved action and module might not be that the present invention is necessary.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that program command is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technical scheme and scope.
Claims (10)
1. a clock frequency method of adjustment, is characterized in that, comprising:
The clock frequency of monitor network equipment, the processor of the described network equipment comprises M universal input and exports GPIO, for adjusting the clock frequency of the described network equipment, wherein M be more than or equal to 1 integer;
If the clock frequency of the described network equipment is in negative frequency deviation, then control the input voltage that a described M GPIO changes the voltage controlled oscillator of the described network equipment, to adjust the clock frequency of the described network equipment.
2. method according to claim 1, is characterized in that, described M be more than or equal to 2 integer;
Correspondingly, the described M of a described control GPIO, the input voltage changing the voltage controlled oscillator of the described network equipment comprises:
Obtain the message amount in the buffer memory of the port of the described network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of described port, and be less than the second buffer threshold, the GPIO controlled in a described M GPIO exports high level, in a described M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of described voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a described GPIO is in parallel with described first divider resistance by adjusting resistance.
3. method according to claim 1 and 2, is characterized in that, the clock frequency of described monitor network equipment comprises:
The buffer memory of the port of the described network equipment of real-time detection;
If there is message in the buffer memory of described port, then obtain the instantaneous delivery bandwidth of described port;
If the instantaneous delivery bandwidth of described port exceedes default port bandwidth threshold value, then judge that the clock frequency of the described network equipment is in negative frequency deviation.
4. method according to claim 3, is characterized in that, obtains the instantaneous delivery bandwidth of described port, comprising:
Obtain the reception packet counting value of described port when current period starts and the reception packet counting value at the end of current period;
According to described reception packet counting value when current period starts and described reception packet counting value at the end of current period, obtain the message amount that described port receives in current period, the message amount received in described current period equals described reception packet counting value at the end of current period and deducts the described reception packet counting value when current period starts;
According to the described message amount received in current period, obtain the instantaneous delivery bandwidth of described port, the instantaneous delivery bandwidth of described port equals the value of the described message amount received in current period divided by the duration gained of described current period.
5. method according to claim 3, is characterized in that, also comprises:
If there is not message in the buffer memory of described port, judge whether the clock frequency of the described network equipment does overdeviation adjustment;
If the clock frequency of the described network equipment does overdeviation adjustment, the clock frequency of the described network equipment is returned to normal frequency.
6. a clock frequency adjusting device, is characterized in that, comprising:
Monitoring module, for the clock frequency of monitor network equipment, the processor of the described network equipment comprises M universal input and exports GPIO, for adjusting the clock frequency of the described network equipment, wherein M be more than or equal to 1 integer;
Adjusting module, if be in negative frequency deviation for the clock frequency of the described network equipment, then controls the input voltage that a described M GPIO changes the voltage controlled oscillator of the described network equipment, to adjust the clock frequency of the described network equipment.
7. device according to claim 6, is characterized in that, described M be more than or equal to 2 integer;
Described adjusting module specifically for:
Obtain the message amount in the buffer memory of the port of the described network equipment;
If message amount is greater than the first buffer threshold in the buffer memory of described port, and be less than the second buffer threshold, the GPIO controlled in a described M GPIO exports high level, in a described M GPIO, remaining GPIO is input state, wherein, the dividing potential drop pin of described voltage controlled oscillator is connected between the first divider resistance and the second divider resistance, and a described GPIO is in parallel with described first divider resistance by adjusting resistance.
8. the device according to claim 6 or 7, is characterized in that, described monitoring module specifically for:
The buffer memory of the port of the described network equipment of real-time detection;
If there is message in the buffer memory of described port, then obtain the instantaneous delivery bandwidth of described port;
If the instantaneous delivery bandwidth of described port exceedes default port bandwidth threshold value, then judge that the clock frequency of the described network equipment is in negative frequency deviation.
9. device according to claim 8, is characterized in that, described monitoring module specifically for:
Obtain the reception packet counting value of described port when current period starts and the reception packet counting value at the end of current period;
According to described reception packet counting value when current period starts and described reception packet counting value at the end of current period, obtain the message amount that described port receives in current period, the message amount received in described current period equals described reception packet counting value at the end of current period and deducts the described reception packet counting value when current period starts;
According to the described message amount received in current period, obtain the instantaneous delivery bandwidth of described port, the instantaneous delivery bandwidth of described port equals the value of the described message amount received in current period divided by the duration gained of described current period.
10. device according to claim 8, is characterized in that, described monitoring module also for:
If there is not message in the buffer memory of described port, judge whether the clock frequency of the described network equipment does overdeviation adjustment;
Correspondingly, if described adjusting module also does overdeviation adjustment for the clock frequency of the described network equipment, the clock frequency of the described network equipment is returned to normal frequency.
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