CN101174586A - Method for regulating threshold voltage of element - Google Patents
Method for regulating threshold voltage of element Download PDFInfo
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- CN101174586A CN101174586A CNA2006101178346A CN200610117834A CN101174586A CN 101174586 A CN101174586 A CN 101174586A CN A2006101178346 A CNA2006101178346 A CN A2006101178346A CN 200610117834 A CN200610117834 A CN 200610117834A CN 101174586 A CN101174586 A CN 101174586A
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- raceway groove
- nmos
- pmos
- groove
- injection
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Abstract
The invention discloses a method for adjusting the threshold voltage of electronic devices, which comprises the following steps: step one, shallow groove isolation forming; step two, P well injection; step three, N well injection; step four, grid oxidation; step five, drain electrode light dope and halo injection; step six, side wall forming; step seven, source and drain electrode injection and annealing; step eight, infusible metal silicide forming; step nine, the forming of interlayer dielectric film before metal precipitation; step ten, the forming of NMOS and PMOS groove adjusting light covers; step eleven, the etching of NMOS and PMOS groove adjusting areas; step twelve, the forming of an NMOS groove adjusting light cover; step thirteen, NMOS groove adjustment and injection; step fourteen, the forming of a PMOS groove adjusting light cover; step fifteen, PMOS groove adjustment and injection; after the groove adjustment and injection, the invention does not performs strong heat treatment, thereby not influencing the groove areas of the device, and effectively adjusting the threshold voltage of the device.
Description
Technical field
The present invention relates to the field field of semiconductor manufacture, especially a kind of method of regulating threshold voltage of element.
Background technology
In the production technology of deep-submicron CMOS, for improving the electric property performance of device, requirement is more and more accurate to the control of the threshold voltage of device.But in traditional technology, the heat treatment of a lot of steps after regulating injection, the MOS raceway groove can be arranged all.
As shown in Figure 1, the method for regulating threshold voltage of element may further comprise the steps in the traditional handicraft: the first step, and shallow trench isolation is from formation; In second step, the P trap injects; In the 3rd step, the NMOS raceway groove is regulated and is injected; In the 4th step, the N trap injects; In the 5th step, the PMOS raceway groove is regulated and is injected; The 6th step, gate oxidation; In the 7th step, lightly doped drain and haloing inject; In the 8th step, abutment wall forms; In the 9th step, source-drain electrode injects and annealing; In the tenth step, refractory metal silicide forms; In the 11 step, form the preceding inter-level dielectric film of precipitated metal.
In traditional handicraft, the MOS raceway groove is regulated the heat treatment step after injecting, may cause the threshold voltage shift of device, also can impact simultaneously being subjected to these heat treated silicon chip surface homogeneity, more cause the threshold voltage of device different distributions to be arranged, thereby influence the electric property of device at silicon chip surface.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method of regulating threshold voltage of element, threshold voltage that can separate controller spare, reduce even eliminate the traditional devices raceway groove and regulate heat treatment after injecting, thereby improve the electric property of device the influence of device channel threshold voltage.
For solving the problems of the technologies described above, the technical scheme that method adopted of regulating threshold voltage of element of the present invention is may further comprise the steps: the first step, and shallow trench isolation is from formation; In second step, the P trap injects; In the 3rd step, the N trap injects; The 4th step, gate oxidation; In the 5th step, lightly doped drain and haloing inject; In the 6th step, abutment wall forms; In the 7th step, source-drain electrode injects and annealing; In the 8th step, refractory metal silicide forms; In the 9th step, form the preceding inter-level dielectric film of precipitated metal; In the tenth step, form NMOS and PMOS raceway groove and regulate light shield; The 11 step, NMOS and PMOS raceway groove regulatory region etching; In the 12 step, form the NMOS raceway groove and regulate light shield; In the 13 step, the NMOS raceway groove is regulated and is injected; In the 14 step, form the PMOS raceway groove and regulate light shield; In the 15 step, the PMOS raceway groove is regulated and is injected.
The another kind of technical scheme of the method for regulating threshold voltage of element of the present invention is may further comprise the steps: the first step, and shallow trench isolation is from formation; In second step, the P trap injects; In the 3rd step, the N trap injects; The 4th step, gate oxidation; In the 5th step, lightly doped drain and haloing inject; In the 6th step, abutment wall forms; In the 7th step, source-drain electrode injects and annealing; In the 8th step, refractory metal silicide forms; In the 9th step, form the preceding inter-level dielectric film of precipitated metal; In the tenth step, form NMOS and PMOS raceway groove and regulate light shield; The 11 step, NMOS and PMOS raceway groove regulatory region etching; In the 12 step, form the PMOS raceway groove and regulate light shield; In the 13 step, the PMOS raceway groove is regulated and is injected; In the 14 step, form the NMOS raceway groove and regulate light shield; In the 15 step, the NMOS raceway groove is regulated and is injected.
After the inter-level dielectric film deposition and planarization of the present invention before metal deposition, open the zone of device channel adjusting with the method for etching the threshold voltage of device is adjusted.After raceway groove is regulated injection, just enter road, back processing procedure, no longer include stronger heat treatment, thereby can the channel region of device not impacted, raceway groove is regulated to inject and also can be improved the NMOS reverse turn short channel effect simultaneously.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the method flow schematic diagram of traditional handicraft regulating threshold voltage of element;
Fig. 2 is the method flow schematic diagram of regulating threshold voltage of element of the present invention;
Fig. 3 is the 9th a step structural representation in the inventive method;
Fig. 4 is the tenth a step structural representation in the inventive method;
Fig. 5 is the 11 a step structural representation in the inventive method;
Fig. 6 is the 13 a step structural representation in the inventive method.
Embodiment
As shown in Figure 2, the technical scheme that method adopted of a kind of regulating threshold voltage of element of the present invention is may further comprise the steps: the first step, and shallow trench isolation is from formation; In second step, the P trap injects; In the 3rd step, the N trap injects; The 4th step, gate oxidation; In the 5th step, lightly doped drain and haloing inject; In the 6th step, abutment wall forms; In the 7th step, source-drain electrode injects and annealing; In the 8th step, refractory metal silicide forms; In the 9th step, as shown in Figure 3, form the preceding inter-level dielectric film of precipitated metal; In the tenth step, as shown in Figure 4, form NMOS and PMOS raceway groove and regulate light shield; The 11 step, as shown in Figure 5, NMOS and PMOS raceway groove regulatory region etching; In the 12 step, form the NMOS raceway groove and regulate light shield; In the 13 step, as shown in Figure 6, the NMOS raceway groove is regulated and is injected; In the 14 step, form the PMOS raceway groove and regulate light shield; In the 15 step, the PMOS raceway groove is regulated and is injected.
As shown in Figure 7, the another kind of technical scheme that method adopted of a kind of regulating threshold voltage of element of the present invention is may further comprise the steps: the first step, and shallow trench isolation is from formation; In second step, the P trap injects; In the 3rd step, the N trap injects; The 4th step, gate oxidation; In the 5th step, lightly doped drain and haloing inject; In the 6th step, abutment wall forms; In the 7th step, source-drain electrode injects and annealing; In the 8th step, refractory metal silicide forms; In the 9th step, form the preceding inter-level dielectric film of precipitated metal; In the tenth step, form NMOS and PMOS raceway groove and regulate light shield; The 11 step, NMOS and PMOS raceway groove regulatory region etching; In the 12 step, form the PMOS raceway groove and regulate light shield; In the 13 step, the PMOS raceway groove is regulated and is injected; In the 14 step, form the NMOS raceway groove and regulate light shield; In the 15 step, the NMOS raceway groove is regulated and is injected.
The present invention just enters road, back processing procedure after raceway groove is regulated injection, no longer carry out stronger heat treatment, thereby can the channel region of device not impacted, effectively regulating threshold voltage of element.
Claims (2)
1. the method for a regulating threshold voltage of element is characterized in that, may further comprise the steps:
The first step, shallow trench isolation is from formation;
In second step, the P trap injects;
In the 3rd step, the N trap injects;
The 4th step, gate oxidation;
In the 5th step, lightly doped drain and haloing inject;
In the 6th step, abutment wall forms;
In the 7th step, source-drain electrode injects and annealing;
In the 8th step, refractory metal silicide forms;
In the 9th step, form the preceding inter-level dielectric film of precipitated metal;
In the tenth step, form NMOS and PMOS raceway groove and regulate light shield;
The 11 step, NMOS and PMOS raceway groove regulatory region etching;
In the 12 step, form the NMOS raceway groove and regulate light shield;
In the 13 step, the NMOS raceway groove is regulated and is injected;
In the 14 step, form the PMOS raceway groove and regulate light shield;
In the 15 step, the PMOS raceway groove is regulated and is injected.
2. the method for a regulating threshold voltage of element is characterized in that, may further comprise the steps:
The first step, shallow trench isolation is from formation;
In second step, the P trap injects;
In the 3rd step, the N trap injects;
The 4th step, gate oxidation;
In the 5th step, lightly doped drain and haloing inject;
In the 6th step, abutment wall forms;
In the 7th step, source-drain electrode injects and annealing;
In the 8th step, refractory metal silicide forms;
In the 9th step, form the preceding inter-level dielectric film of precipitated metal;
In the tenth step, form NMOS and PMOS raceway groove and regulate light shield;
The 11 step, NMOS and PMOS raceway groove regulatory region etching;
In the 12 step, form the PMOS raceway groove and regulate light shield;
In the 13 step, the PMOS raceway groove is regulated and is injected;
In the 14 step, form the NMOS raceway groove and regulate light shield;
In the 15 step, the NMOS raceway groove is regulated and is injected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101178346A CN101174586A (en) | 2006-11-01 | 2006-11-01 | Method for regulating threshold voltage of element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101178346A CN101174586A (en) | 2006-11-01 | 2006-11-01 | Method for regulating threshold voltage of element |
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| Publication Number | Publication Date |
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| CN101174586A true CN101174586A (en) | 2008-05-07 |
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| CNA2006101178346A Pending CN101174586A (en) | 2006-11-01 | 2006-11-01 | Method for regulating threshold voltage of element |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783624A (en) * | 2016-12-31 | 2017-05-31 | 杭州潮盛科技有限公司 | Transistor threshold voltage adjusting method and phase inverter preparation method |
-
2006
- 2006-11-01 CN CNA2006101178346A patent/CN101174586A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783624A (en) * | 2016-12-31 | 2017-05-31 | 杭州潮盛科技有限公司 | Transistor threshold voltage adjusting method and phase inverter preparation method |
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Open date: 20080507 |