CN101167244A

CN101167244A - Gate driver for class D audio amplifier with adaptive DV/DT control

Info

Publication number: CN101167244A
Application number: CNA2006800080211A
Authority: CN
Inventors: 本田纯
Original assignee: International Rectifier Corp USA
Current assignee: Infineon Technologies Americas Corp
Priority date: 2005-04-05
Filing date: 2006-04-04
Publication date: 2008-04-23

Abstract

Provided is a gate driver circuit for a Class D audio amplifier with adaptive dV/dt control. The circuit includes an output switching stage, a gate driver capable of driving the output switching stage with a variable dV/dt; and a mode control circuit for setting an operating mode of the gate driver, wherein, the operating mode is selected from a plurality of operating modes, changes the dV/dt of the gate driver, corresponds to a power output level, and provides a balance point between a generated Electromagnetic Interference (EMI) and an efficiency of the switching stage.

Description

Be used to use the gate drivers of the D class audio amplifier that adapts to DV/DT control

The cross reference of related application

The application based on and require the U.S. Provisional Application 60/668 of " being used to use the gate drivers of the D class audio amplifier that adapts to DV/DT control " by name of proposing on April 5th, 2005,656 interests, and require the priority of this application at this, and its disclosure is incorporated into this as quoting.

Technical field

The present invention relates to the D class A amplifier A, more particularly, relate to and on the D class A amplifier A, use adaptation dV/dt control.

Background technology

Power D class A amplifier A, for example, the amplifier 10 shown in Fig. 1 will be imported waveform and be converted to continuous pulse-width modulation (PWM) analog signal.Can repeat to produce signal with the bandwidth that is lower than pulse frequency just.The output of D class A amplifier A comprises unwanted spectral component, and for example, pulse frequency and harmonic wave thereof must remove it by Passive LC filter 18.Become the amplification duplicate of input after the resulting filtering signal.

Normally, as shown in Figure 1, power transistor 14 and 16 switching stage 12 are born exchange interaction between efficient and the electromagnetic interference (EMI) that sends as the byproduct of power transistor operate as normal.EMI causes introducing unwanted signal (disturbing or noise) in circuit.Need in described switching stage 12, use higher dV/dt so that obtain better efficient.Yet, because dV/dt transient state artifact jumpy (transient artifacts), so higher change in voltage (dV/dt) can become one of reason that causes the EMI noise on the time.

This is the application of audio signal in D class audio frequency in essence, and the average output power of audio signal is significantly less than its peak value.If amplifier has the low EMI noise emission on lower output power level, and the higher efficient on high-output power rank more, so after the design problem of these two opposition can be by compatibility.

Summary of the invention

Therefore, the objective of the invention is to allow to change the grid maneuvering performance so that control dV/dt according to input duty cycle at switching node.

The invention provides the gate driver circuit that is used to use the D class audio amplifier that adapts to dV/dt control.Described circuit comprises the output switching stage, can use variable dV/dt to drive the gate drivers of described output switching stage; And the mode control circuit that is used to be provided with the mode of operation of gate drivers, wherein, described mode of operation is selected from a plurality of mode of operations, changes the dV/dt of gate drivers, in response to power output stage not and be provided at balance point between the efficient of the electromagnetic interference (EMI) of generation and switching stage.

In one embodiment of the invention, described gate drivers has two mode of operations.One is used for high dV/dt, and another is used for low relatively dV/dt, so that reduce EMI, simultaneously as the compromise degradation that causes efficient.Described gate drivers changes self pattern according to the output power level of estimating.Described gate drivers is estimated average to the power output of load by calculating from the power of input duty cycle.

Other features and advantages of the present invention will become apparent in following the present invention description with reference to the accompanying drawings.

Description of drawings

Fig. 1 is the circuit diagram with D class A amplifier A of half-bridge topology;

Fig. 2 A, 2B and 2C are the circuit diagrams of D class A amplifier A that has shown the various embodiment of pattern of the present invention control;

Fig. 3 is the structure chart of the mode control logic of D class A amplifier A of the present invention; And

Fig. 4 A has shown the embodiment of the gate drivers that comprises mode control logic of the present invention, and relevant Fig. 4 B-4D has shown duty detection, total harmonic distortion (THD) and Dead Time figure.

Embodiment

Fig. 2 A, 2B and 2C have shown gate drivers 22 of the present invention.Described gate drivers 22 comprises two kinds of different mode of operations.First pattern is used for temporal high voltage and changes (dV/dt), and second pattern is used for described relatively low dV/dt, so that reduce electromagnetic interference (EMI) as trading off with the degradation of efficient.Described gate drivers 22 is designed to change its pattern according to the output power level of estimating or calculate.

Estimate power output

The gate drivers 22 of the described invention among Fig. 2 A comprises mode control circuit 24, and this circuit can be carried out by the power of the duty ratio 30 of calculating input 28 and estimate function to the average output power rank 32 of load.Described average output power rank 32 can be obtained by the integrated square of input duty cycle, for example, and (0.5-duty ratio) ², these computational methods are represented the output power level to the ohmic load (not shown).If average output power rank 32 has surpassed certain intended level, described gate drivers 22 changes described pattern into high dV/dt by low dV/dt so afterwards.

Described other appropriate threshold of average output power level can be set to be higher than nominal power level other 12.5%, thereby make gate drivers be allowed in the most of the time, be operated under the low dV/dt pattern.12.5% of rated power can be as the maximum average output power of the audio signal output with non-amplitude limit.Described amplitude limit takes place when increasing voltage on the limit of attempting at described amplifier.

Produce division according to loss and heat, the EMI situation of the most serious D class level occurs in the rated power rank.Described gate drivers 22 works in the high dV/dt pattern of high efficiency under this situation compromise to the EMI noise.Yet this situation is rarely found in actual applications.

Calculate power output

Similarly, circuit 24 can by calculate output at described switching stage 12 (shown in Fig. 2 B before the LC filter 18 or shown in Fig. 2 C after the LC filter) voltage, electric current and volt-second (Volt-second) in any one power calculate average output power rank 32 to load.

Fig. 3 has shown the structure chart of mode controller circuit 24.Average calculation unit 40 receives PWM input 28, for averaging, detects duty ratio 30 in one sufficiently long period.Described average 42 process comparator parts 46, the predetermined rank 48 that this comparator partly is used for more described average 42 and keeps at reference rank holding unit 50.If described average 42 is higher than described predetermined rank 48, so described pattern is set to height, otherwise that described pattern is set to is low.

In the circuit in Fig. 4 A, power output is estimated by circuit 40A, for example, uses formula: power=| duty angle-0.5| ² Integrator 40B is used for determining average time.Described average in comparator 46 with threshold.If this average is less than described threshold value, driver H so _oAnd L _oBe maintained at the inefficient pattern of low dV/dt, if be higher than threshold value, driver H so _oAnd L _oBe placed in the high dV/dt pattern of high efficiency.

Similarly, Dead Time circuit 45 is regulated Dead Time according to the output of described comparator 46.This process is done so that when high power, and described Dead Time is set to the bigger value shown in Fig. 4 D.Fig. 4 B has shown that duty testing circuit function and Fig. 4 C have shown the total harmonic distortion (THD) as the function of power.

Circuit of the present invention provides shorter variable Dead Time when low power level, low extreme value (lowFull) and low THD, but bigger efficient is provided when the high power rank.

Though the present invention is described by special embodiment, many other variation and modification and other application will become apparent those skilled in the art.Therefore, preferably, the present invention can't help particular content disclosed herein and limits.

Claims

1. gate driver circuit that is used to use the D class audio amplifier that adapts to dV/dt control, this circuit comprises:

The output switching stage;

Can use variable dV/dt to drive the gate drivers of described output switching stage; And

Be used to be provided with the mode control circuit of the mode of operation of described gate drivers, wherein, described mode of operation is selected from a plurality of mode of operations, changes the dV/dt of described gate drivers, other in response to power output stage, and be provided at balance point between the efficient of the electromagnetic interference of generation and described switching stage.

2. circuit according to claim 1, wherein said a plurality of mode of operations are by being come the average output power rank is estimated to determine by the input to described gate drivers.

3. circuit according to claim 1, wherein said a plurality of mode of operations are to determine by coming for one in the volt-second of output voltage, output current, pulse-width signal output power level calculated on point between described switching stage and filter or the point between described filter and load.

4. circuit according to claim 2, wherein said mode control circuit obtains the average output power rank and estimates described average output power rank in the duty ratio of described input and by the integration that square carries out to input duty cycle by detecting pulse-width modulation, described input duty cycle square represent output power level to load.

5. circuit according to claim 4, if wherein described average output power rank surpasses predetermined threshold value, the power output stage of so described gate drivers is not transformed into high dV/dt from low dV/dt.

6. circuit according to claim 4, wherein said predetermined threshold value be set to larger than nominal power level other 12.5%, wherein said gate drivers is operated in described low dV/dt, and described rated power 12.5% be considered to maximum average output power.

7. circuit according to claim 1, at least one of the output voltage of the different setting that wherein is used for driving described grid by changing output impedance, described gate drivers, and obtain at the output couple current amplitude limiter of described gate drivers.

8. circuit according to claim 1, wherein said mode control circuit are controlled the Dead Time between the ON time of two switches of series connection of described switching stage.

9. circuit according to claim 1, wherein said switching stage comprise two switches of series connection.

10. an operation is used to use the method for the gate driver circuit of the D class audio amplifier that adapts to dV/dt control, said method comprising the steps of:

Determine that the power output stage that can use variable dV/dt to drive the gate drivers of exporting switching stage is other;

Select according to described power output stage not with the mode of operation of the balance point between the efficient of the electromagnetic interference that is provided at generation and described switching stage;

Described mode of operation is set, and the dV/dt of described gate drivers is set thus.

11. method according to claim 10, if wherein described average output power rank surpasses predetermined threshold value, the power output stage of so described gate drivers is not transformed into high dV/dt by low dV/dt.