JP4538783B2 - D class amplifier - Google Patents

Description

  The present invention relates to a D-class amplifier (also referred to as a D-class amplifier or a D-class power amplifier) used for a digital audio amplifier, a motor driver, or the like.

  A D-class amplifier comprising a high-side MOS transistor and a low-side MOS transistor in a switching output stage that are alternately driven by two pulse input waves having opposite phases such as PWM (pulse width modulation) output or PDM (pulse continuous modulation) output, Widely used in digital audio amplifiers, motor drivers, etc., and generally dead time (Dead) at the time of switching of the high-side MOS transistor and low-side MOS transistor (typically MOSFET) connected in series between ± B power supplies of the switching output stage Time; the period during which both the high and low side MOS transistors are in the off state) is controlled to reduce the through current that flows instantaneously through the high side MOS transistor and the low side MOS transistor, and the distortion rate. It is adopted to suppress drive system.

  The drive output method is roughly divided into a high-side MOS transistor Q1 and a low-side MOS transistor Q2 connected between ± B power supplies as shown in FIG. And a full bridge type comprising two sets of switching output stages (Q1, Q2) and (Q3, Q4) of a high side MOS transistor and a low side MOS transistor as shown in FIG.

  10 and 11, the coil L1 and the capacitor C1 surrounded by a broken line frame constitute a low-pass filter circuit LPF, reference numerals 1 and 2 are dead time adjustment circuits, reference numeral 3 is a level shift circuit, reference numerals 4 and 5 Is a MOS transistor driver circuit.

  As a publicly known document relating to this D class amplifier, for example, the following [Patent Document 1] describes a technique for improving the S / N ratio and lowering the distortion rate of a D class amplifier (class D amplifier).

  The class D amplifier described in [Patent Document 1] is a half-bridge type that is driven to be switched by PWM pulse output, and includes a coil and a capacitor between the switching output terminal and a load speaker. The configuration in which the filter circuit LPF is inserted is the same as the circuit configuration in FIG.

JP 2002-359525 A

  In order to improve the distortion rate in both the half-bridge type D-class amplifier of FIG. 10 and the full-bridge type of FIG. 11, it is generally necessary to shorten the dead time.

  However, as the dead time is shortened, the through current (short-through) flowing through the high-side MOS transistors Q1 and Q3 and the low-side MOS transistors Q2 and Q4 increases, and the efficiency (deterioration of power loss) further increases. Causes an increase in heat generation and destruction of the MOS transistor. Therefore, it is usually designed with an appropriate compromise considering both distortion and efficiency.

  For example, in the conventional half-bridge type D-class amplifier of FIG. 10, an appropriate dead time (generally several tens of ns with a digital audio amplifier) is used to reduce distortion while suppressing the through current of the MOS transistors Q1 and Q2. Is adjusted.

  According to the above configuration, the rising of the switching output voltage Va at the switching output terminal A in FIG. 10 at the time of switching (switching when Q2 is turned off and Q1 is turned on) is a waveform schematic diagram of the switching output voltage Va in FIG. As shown in FIG. 4, the [no signal] (including the time of low power output) in the upper part of the drawing is the flyback effect of the coil L1 of the low-pass filter circuit LPF even during the dead time period. Va starts to rise at the moment when the MOS transistor Q2 is turned off by the self-induction action (waveform M1) and the dead time is masked, so that the distortion is hardly deteriorated. Then, when the dead time is over and the MOS transistor Q1 is turned on, its original driving force is applied and it suddenly rises (waveform M2).

  However, when the output power is increased, the flyback effect of the coil L1 disappears at the time of [power output] in the lower part of FIG. 12, and a rise delay (waveform M2) due to the dead time of the switching output voltage Va appears. The distortion becomes worse.

  This phenomenon is a comparison graph (simulation) of the output amplitude voltage waveform W1 of the load speaker when the dead time in FIG. 13 is large (100 ns) and the output amplitude voltage waveform W2 when the dead time is small (30 ns). As can be seen from the above, visible distortion appears in the waveform portion indicated by reference numeral 7 when the dead time is increased.

  However, as described above, if the dead time is set small, the through current increases and the switching loss becomes large (large power loss). Therefore, there is a limit to reducing the dead time, and the problem of distortion cannot be solved.

FIG. 15 is an actual measurement graph of the output waveform (sine wave) and distortion waveform of the speaker of the load SPK in the conventional full bridge type D class amplifier. As can be seen from this figure, when the output is as small as 2 W, the distortion rate THD is as small as 0.0047%, but when the output is as large as 8 W, the distortion rate THD is visibly increased as 0.0222%.

  As described above, in the conventional D-class amplifier, the waveform is distorted and the audio characteristics are deteriorated when the power is output with an output amplitude that eliminates the flyback effect masking the dead time.

  In addition, as a common problem in both [no signal] and [power output] in FIG. 12, overshoot and ringing of a rising / falling waveform at the time of switching of the switching output voltage Va (network of reference numeral 8). The line region) causes the switching MOS transistors Q1 and Q2 to have a withstand voltage margin shortage (the risk of destruction of the MOS transistors) and an unnecessary radiation level increase (EMC level increase), making the circuit design of the D class amplifier difficult.

In fact, it can be seen that as shown in the rise measured waveform in switching of the switching output voltages Va, remarkable overshoot and ringing 8 appearing in the conventional D-class amplifier shown in FIG. 1 6.

  As means for suppressing the overshoot and ringing 8, there are methods such as increasing the dead time or decreasing the slew rate of the MOS transistor. The method for increasing the dead time is a technique realized by a so-called zero switching operation in which the MOSFET is turned on when the switching output voltage Va has risen to some extent by the flyback effect of the coil L1 of the low-pass filter circuit LPF.

  However, when the dead time is increased, eventually, when the output power is increased, the flyback effect by the coil L1 is lost, so that the zero switching operation is not performed, and overshoot and ringing occur again. Naturally, as described above, the dead time begins to appear, and the distortion rate also deteriorates.

  Here, in the conventional D-class amplifier, the reason why the beneficial effect for improving the distortion rate that the dead time is masked by the flyback effect of the coil L1 that appears when there is no signal is eliminated during power output.

First, the half-bridge type D class amplifier shown in Figure 10, when the current flowing through the coil L1 of the low-pass filter circuit LPF is defined as Ia (speaker side direction of the load SPK is positive.) Of FIG 4 As shown in the waveform change diagram of the switching output voltage Va and the current Ia flowing through the coil L1, the current direction of Ia is changed alternately at a duty of 50%. Switching due to the flyback effect becomes dominant for both rise and fall, and no delay due to dead time is visible.

However, increasing the output power, lower for Ia orientation of the at power output] is the (always Ia> 0 in the positive direction in the example of FIG. 1. 4) is only the same direction rather than alternating current due to the flyback effect The timing at which the direction of is opposite to that when the duty is 50% occurs (in FIG. 16, the timing at the rise of Va). At this timing, the rise of the switching output voltage Va due to the flyback effect can no longer be expected, and the rise due to the original switching of the MOS transistor Q1 at a point delayed by the dead time becomes dominant. That is, since the rise from the flyback effect of the coil L1 transitions to the original rise of the MOSFET, the rise point is delayed by the dead time . That is, the dead time is not masked and the distortion rate is deteriorated.

Furthermore, on also changes the slew rate by a transition, because it must set up a switching output voltage Va overcome the reverse flyback (downward flyback effect at the time of the rise of the Va in FIG 4 has occurred.) The slew rate exhibits a complicated movement and causes a further deterioration in distortion.

  The present invention has been made in view of the contradictory characteristics of the distortion and efficiency of the D-class amplifier, and obtains a desirable coil flyback effect that always masks the dead time with a simple configuration. It is an object of the present invention to provide a D-class amplifier having such a configuration that can take a large dead time and realize a zero switching operation.

  In order to solve the above-mentioned problem in the conventional D-class amplifier, it is possible to generate a flyback effect that masks the dead time due to the coil even at the time of large power output as in the case of no signal with a duty of 50%. No delay due to dead time occurs, and there is no deterioration in distortion. In other words, it is important to always start up with the same timing and the same slew rate regardless of the output power.

The present invention provides the following D-class amplifiers (1) to ( 6 ) as means for solving the above-mentioned problems, focusing on the flyback effect of the coil.
(1) a switching output stage having first and second switching elements driven alternately;
A low-pass filter circuit LPF having a coil L1 and a capacitor C1, and inserted between the switching output terminal A of the switching output stage and the load SPK;
A series circuit of a coil L2 and a capacitor C2 connected between the switching output terminal A of the switching output stage and the ground ,
The first switching element is connected to a positive output terminal of a power supply, and the second switching element is connected to a negative output terminal of the power supply;
In the series circuit, the direction of the current flowing through the switching output terminal A of the switching output stage when the first switching element is switched from the on state to the off state is set to the direction of the load SPK. A D class amplifier characterized by adjusting a direction of a current flowing through a switching output terminal A of the switching output stage when an element is switched from an on state to an off state so as to be opposite to the load SPK 10.
(2) a first switching output stage having first and second switching elements driven alternately;
A second switching output stage having a third switching element and a fourth switching element driven alternately;
A first low-pass filter circuit LPF1 having a coil L1 and a capacitor C1 and inserted between a switching output terminal A of the first switching output stage and a load SPK;
A second low-pass filter circuit LPF2 having a coil L1 and a capacitor C1 and inserted between the switching output terminal B of the second switching output stage and the load SPK;
A first series circuit of a coil L3 and a capacitor C3 connected between the switching output terminal A of the first switching output stage and the ground;
A second series circuit of a coil L3 and a capacitor C3 connected between the switching output terminal B of the second switching output stage and the ground ,
The first switching element and the third switching element are connected to a positive output terminal of a power supply, and the second switching element and the fourth switching element are connected to a negative output terminal of a power supply,
In the first series circuit, the direction of the current flowing through the switching output terminal A of the first switching output stage when the first switching element switches from the on state to the off state is the direction of the load SPK. The direction of the current flowing through the switching output terminal A of the first switching output stage when the second switching element switches from the on state to the off state is adjusted to be opposite to the load SPK. And
In the second series circuit, the direction of the current flowing through the switching output terminal B of the second switching output stage when the third switching element switches from the on state to the off state is the direction of the load SPK. The direction of the current flowing through the switching output terminal B of the second switching output stage when the fourth switching element switches from the on state to the off state is adjusted to be opposite to the load SPK. A D-class amplifier 20 characterized by:
(3) a first switching output stage having first and second switching elements that are driven alternately;
A second switching output stage having a third switching element and a fourth switching element driven alternately;
A first low-pass filter circuit LPF1 having a coil L1 and a capacitor C1 and inserted between a switching output terminal A of the first switching output stage and a load SPK;
A second low-pass filter circuit LPF2 having a coil L1 and a capacitor C1 and inserted between the switching output terminal B of the second switching output stage and the load SPK;
A series circuit of a coil L4 and a capacitor C4 connected between the switching output terminal A of the first switching output stage and the switching output terminal B of the second switching output stage ;
The first switching element and the third switching element are connected to a positive output terminal of a power supply, and the second switching element and the fourth switching element are connected to a negative output terminal of a power supply,
In the series circuit, the direction of the current flowing through the switching output terminal A of the first switching output stage when the first switching element switches from the on state to the off state is the direction of the load SPK. Adjusting the direction of the current flowing through the switching output terminal A of the first switching output stage when the switching element of 2 is switched from the on state to the off state so as to be opposite to the load SPK, The direction of the current flowing through the switching output terminal B of the second switching output stage when the third switching element switches from the on state to the off state is the direction of the load SPK, and the fourth switching element is on The direction of the current flowing through the switching output terminal B of the second switching output stage when the state is switched to the off state D class amplifier 30 to the load SPK and adjusts so that the opposite direction.
( 4 ) The D class amplifier 10 according to (1) above, wherein an inductance value of the coil L2 of the series circuit is smaller than an inductance value of the coil L1 of the low pass filter circuit LPF.
(5) the inductance of the coil L3 of the first series circuit is smaller than the inductance value of the coil L1 of the first low-pass filter circuit LPF1,
The D class amplifier 20 according to (2) , wherein an inductance value of the coil L3 of the second series circuit is smaller than an inductance value of the coil L1 of the second low-pass filter circuit LPF2.
( 6 ) The inductance value of the coil L4 of the series circuit is smaller than the inductance value of the coil L1 of the first low-pass filter circuit LPF1 and the inductance value of the coil L1 of the second low-pass filter circuit LPF2. The D class amplifier 30 according to (3) above, which is characterized.

  A newly added LC circuit such as a series-connected coil L2 (or L3, L4) and capacitor C2 (or C3, C4) generates a flyback effect in a direction that always masks dead time regardless of output power. be able to. Hereinafter, the LC circuit including the series-connected coils L2, L3, or L4 and the capacitor C2, C3, or C4 for generating flyback is referred to as a forced flyback generator (abbreviated as FFG).

The D-class amplifier according to the present invention has a circuit configuration in which a forced flyback generating circuit that makes the dead time during switching invisible at all times inserted as described above.
(1) Although it has a simple circuit configuration, the flyback effect of the coil can be obtained even at the time of high power output, and the dead time at the time of switching is always masked, which is effective in improving the distortion.
(2) Since the distortion does not deteriorate even if the dead time is increased by the forced flyback effect, it is possible to design a circuit so as to increase the dead time in advance, and the zero switching operation can be easily realized.
(3) Since zero switching operation is possible regardless of output power, it is possible to reduce unnecessary radiation levels by reducing overshoot and ringing.
(4) By increasing the dead time, it is possible to easily reduce the through current flowing in the high-side MOS transistor and the low-side MOS transistor in the switching output stage. This reduction of the through current not only minimizes the deterioration of both MOS transistors and extends their life, but is also effective in preventing malfunctions of the current detection circuit, etc. Noise mixing and inter-channel interference can be reduced.
(5) Since overshoot can be reduced, it can be expected to avoid breakdown of the MOS transistor, to ensure a breakdown margin, and to extend the lifetime.

  The best mode of the D class amplifier according to the present invention will be described with reference to the drawings. Since circuits such as the PWM modulation circuit before the switching output stage in the conventional D-class amplifier are well-known techniques, the description thereof will be omitted, and the flyback effect of the coil at the time of switching related to the switching output stage and its function will be limited. I will explain. In addition, equivalent parts in the circuit diagrams of the conventional D class amplifier shown in FIGS. 10 and 11 are denoted by the same reference numerals.

  FIG. 1 is a circuit diagram of a D class amplifier (half bridge type) according to a first embodiment of the present invention, and FIG. 2 is a D class amplifier (full bridge type) according to a second embodiment. FIG. 3 is a circuit diagram of a D class amplifier (full bridge type) according to the third embodiment. FIG. 4 is a waveform change diagram of the switching output voltage Va at the switching output terminal A, the current Ia flowing through the coil L1, and the current Ib flowing through the coil L2 in the D class amplifier of FIG. FIG. 5 is a schematic diagram of a rising waveform of the switching output voltage Va.

  In FIG. 1, a D-class amplifier 10 of the present invention includes a switching output stage composed of a high-side MOS transistor Q1 and a low-side MOS transistor Q2 that are alternately driven by pulse input waves P1 and P2, and a switching output terminal of the switching output stage. A half-bridge type D class amplifier having a coil L1 inserted between A and a load SPK (speaker or the like) and a low-pass filter circuit LPF including a capacitor C1, and in particular, the switching output terminal A and the ground The forced flyback generation circuit FFG1 within the broken line frame in which the coil L2 and the capacitor C2 are connected in series is connected between the two.

  In FIG. 2, the D class amplifier 20 of the present invention includes two sets of high side MOS transistors and low side MOS transistors (Q1, Q2), (Q3, Q4) that are alternately driven by pulse input waves P1, P2. Switching output stage and two low-pass filter circuits LPF1 and LPF2 having a coil L1 and a capacitor C1 inserted between the switching output terminals A and B of the switching output stage and the load SPK. In particular, a forced flyback generation circuit FFG2 within a broken line frame in which a coil L3 and a capacitor C3 are connected in series between the full-bridge type switching output terminals A and B and the ground. Is connected.

  In FIG. 3, the D-class amplifier 30 of the present invention includes two sets of high-side MOS transistors and low-side MOS transistors (Q1, Q2), (Q3, Q4) that are alternately driven by pulse input waves P1, P2. Switching output stage and two low-pass filter circuits LPF1 and LPF2 having a coil L1 and a capacitor C1 inserted between the switching output terminals A and B of the switching output stage and the load SPK. In particular, a forced flyback generating circuit FFG3 in a broken line frame in which a coil L4 and a capacitor C4 are connected in series is connected between the full-bridge type switching output terminals A and B. It is the structure which is done.

  Hereinafter, the distortion rate improving operation at the time of switching will be described with reference to FIG. 4 by taking the forced flyback generation circuit FFG3 in the D class amplifier 30 as an example.

  First, the current flowing through the coil L4 and the capacitor C4 of the forced flyback generation circuit FFG3 newly inserted for forced flyback generation is defined as Ib (the direction from the switching output terminal A to the switching output terminal B is positive). In this circuit, the current Ib flows together with the current Ia at the time of switching. However, since the current Ib has no load (speaker or the like), the current changes faster than the current Ia and may take a larger current amplitude. it can.

  Therefore, if the inductance value of the coil L4 is selected to an appropriate value, it is possible to create a state in which the direction of the current Ib is alternately changed even when the output power is increased. Therefore, if the coil L4 is adjusted so that a reverse current whose current Ib is always larger than the current Ia flows at the time of switching at the rising edge of the switching output voltage Va in the lower part of FIG. 4, the total switching output current (Ia + Ib) is substantially equal. As a result, current flows alternately, and the flyback effect in the same direction as when no signal with a duty of 50% can be forcibly obtained. That is, at the rise of Va, Ia + Ib <0, and the flyback direction is the same as when the duty is 50% when there is no signal, and no delay due to dead time occurs.

  As a result, the steep rise after the original dead time of the MOS transistors Q1 and Q2 does not occur, and a stable low distortion rate can be obtained.

  FIG. 4 shows an example in which the current Ia is a forward current, but naturally the same effect can be obtained even in the reverse direction. The operation principle is the same not only for the full-bridge D-class amplifiers 20 and 30 but also for the half-bridge D-class amplifier 10.

  The inductance value of the coil L4 is set to an optimum value in consideration of the values of other circuit elements, but it is important that the change in the current Ib is larger than the current Ia. For example, when the inductor value of the coil L1 is 20 μH, about 10 μH, which is about half of that, is appropriate. Also in the D class amplifiers 10 and 20, for example, the inductance values of the coils L2 and L3 are set to be smaller than the inductance value of the coil L1 of the low-pass filter circuit.

  By the forced flyback generation circuits FFG1, 2, and 3 of the present invention, the rising waveform of the switching output voltage Va is a rising waveform schematic diagram as shown in FIG. 5 regardless of the magnitude of the switching output (even if it is the maximum output power). Since the dead time is always masked, the distortion does not depend on the magnitude of the dead time, and when the dead time is set to a large value, the switching output voltage Va is sufficiently increased by the flyback effect. The transistor can be turned on, and a zero switching operation can be easily realized. As a result, it is possible to obtain an extremely beneficial effect for the D-class amplifier in which through current, overshoot, ringing, and the like are reduced.

  FIG. 6 shows the output amplitude voltage waveform W3 of the load SPK (speaker) of the D class amplifier 30 provided with the forced flyback generation circuit FFG3 according to the present invention and the same output amplitude voltage waveform W4 of the conventional D class amplifier not provided. Although it is a comparative graph (simulation), the effect of the distortion improvement of a forced flyback generation circuit is confirmed.

  FIG. 7 is an actual measurement graph of the output waveform (sine wave) and distortion waveform of the load SPK (speaker) in the D class amplifier 30 of the present invention. As is clear from comparison between FIG. 14 and FIG. 14 described above, when the output is as small as 2 W, the distortion rate THD is as small as 0.0047%, and even when the output is as large as 8 W, the THD is 0.00225%. It turns out that it is stable and small, and it can be seen that a dramatic improvement in the distortion rate can be realized.

  FIG. 8 is a logarithmic graph of simulation values taking the relationship between the presence / absence of the forced flyback generation circuit according to the present invention, the distortion rate THD, and the dead time. In the case of a D-class amplifier without a flyback generation circuit, the distortion rate suddenly increases as the dead time increases. However, in a D-class amplifier with a forced flyback generation circuit, the distortion rate depends on the dead time. It can be seen that the low value is maintained stably. Actually, in the D class amplifier of the present invention, it has been actually measured that a low distortion is secured even when the dead time is set to 100 to 200 ns.

  Further, as apparent from the rising actual measurement waveform at the time of switching of the switching output voltage Va in the D class amplifier 30 of the present invention in FIG. 9, the overshoot and ringing are compared with the case of the conventional same type D class amplifier (see FIG. 15). It can be seen that it is sufficiently suppressed.

  As described above in detail, in the D class amplifier 10 or 20 or 30 including the forced flyback generation circuit FFG1, FFG2 or FFG3 specific to the present invention, regardless of the output level, the dead time is related. Therefore, by setting the dead time large, it is possible to obtain excellent effects such as reduction of through current (improvement of efficiency), reduction of overshoot and ringing, and reduction of unnecessary radiation. .

1 is a circuit diagram of a D-class amplifier according to a first embodiment (half-bridge type) according to the present invention. FIG. It is a circuit diagram of D class amplifier (full bridge type) of the 2nd example of an embodiment concerning the present invention. It is a circuit diagram of D class amplifier (full bridge type) of the 3rd example of an embodiment concerning the present invention. It is a waveform change figure of switching output voltage Va of switching output terminal A, current Ia which flows into coil L1, and current Ib which flows into coil L2 in D class amplifier of the 3rd example of an embodiment concerning the present invention. It is a schematic diagram of the rising waveform of the switching output voltage Va in the D class amplifier of the third embodiment according to the present invention. It is a comparison graph (simulation) of the output amplitude voltage waveform of D class amplifier which provided the forced flyback generation circuit based on this invention, and D class amplifier which is not provided. It is an actual measurement graph of an output waveform (sine wave) and a distortion waveform in D class amplifier of the present invention. It is a logarithmic graph of the simulation value which took the relationship between the presence or absence of the forced flyback generation circuit according to the present invention, the distortion rate THD, and the dead time. It is a rise actual measurement waveform at the time of switching of switching output voltage Va in D class amplifier of the present invention. It is a circuit diagram of a conventional half-bridge type D class amplifier. It is a circuit diagram of a conventional full bridge type D class amplifier. It is a wave form diagram of switching output voltage Va in the conventional D class amplifier. It is a comparison graph (simulation) of the output amplitude voltage waveform W1 when the dead time in the conventional D class amplifier is made large and the output amplitude voltage waveform W2 when the dead time is made small. It is the measurement graph of the output waveform (sine wave) and distortion waveform in the conventional D class amplifier. It is a rising actual measurement waveform at the time of switching of the switching output voltage Va in the conventional D class amplifier. It is a waveform change figure of switching output voltage Va and current Ia which flows into coil L1 in the conventional D class amplifier.

Explanation of symbols

1, 2 Dead time adjustment circuit
3 Level shift circuit 4, 5 Driver circuit
8 Overshoot and ringing 10, 20, 30 D class amplifier Q1, Q3 High side MOS transistor Q2, Q4 Low side MOS transistor C1, C2, C3, C4 Capacitors L, L1, L2, L3, L4 Coils LPF, LPF1, LPF2 Low pass Filter P1, P2 Pulse input wave A, B Switching output terminal M1 Rising waveform due to flyback effect only M2 Rising waveform due to MOS transistor (+ flyback effect) Va Switching output voltage Ia, Ib Current flowing through coil FFG1, FFG2, FFG3 Forced Flyback generator circuit SPK load

Claims (6)

A switching output stage having alternately switched first and second switching elements;
A low-pass filter circuit having a coil and a capacitor, and inserted between a switching output terminal of the switching output stage and a load;
And a series circuit of a connected coil and a capacitor between ground and the switching output of the switching output stage,
The first switching element is connected to a positive output terminal of a power supply, and the second switching element is connected to a negative output terminal of the power supply;
In the series circuit, the direction of the current flowing through the switching output terminal of the switching output stage when the first switching element is switched from the on state to the off state is the load direction, and the second switching element is A D-class amplifier, wherein a direction of a current flowing through a switching output terminal of the switching output stage when switching from an on state to an off state is adjusted to be opposite to the load. A first switching output stage having a first switching element and a second switching element driven alternately;
A second switching output stage having a third switching element and a fourth switching element driven alternately;
A first low-pass filter circuit having a coil and a capacitor, and inserted between a switching output terminal of the first switching output stage and a load;
A second low-pass filter circuit having a coil and a capacitor, and inserted between a switching output terminal of the second switching output stage and a load;
A first series circuit of a coil and a capacitor connected between a switching output terminal of the first switching output stage and a ground;
A second series circuit of a coil and a capacitor connected between the switching output terminal of the second switching output stage and the ground ,
The first switching element and the third switching element are connected to a positive output terminal of a power supply, and the second switching element and the fourth switching element are connected to a negative output terminal of a power supply,
The first series circuit includes a direction of a current flowing through a switching output terminal of the first switching output stage when the first switching element is switched from an on state to an off state, in the direction of the load. Adjusting the direction of the current flowing through the switching output terminal of the first switching output stage when the second switching element is switched from the on state to the off state to be opposite to the load;
In the second series circuit, the direction of the current flowing through the switching output terminal of the second switching output stage when the third switching element is switched from the on state to the off state is the direction of the load. The direction of the current flowing through the switching output terminal of the second switching output stage when the fourth switching element switches from the on state to the off state is adjusted so as to be opposite to the load. D class amplifier. A first switching output stage having a first switching element and a second switching element driven alternately;
A second switching output stage having a third switching element and a fourth switching element driven alternately;
A first low-pass filter circuit having a coil and a capacitor, and inserted between a switching output terminal of the first switching output stage and a load;
A second low-pass filter circuit having a coil and a capacitor, and inserted between a switching output terminal of the second switching output stage and a load;
A series circuit of a coil and a capacitor connected between a switching output terminal of the first switching output stage and a switching output terminal of the second switching output stage ;
The first switching element and the third switching element are connected to a positive output terminal of a power supply, and the second switching element and the fourth switching element are connected to a negative output terminal of a power supply,
The series circuit includes a direction of a current flowing through a switching output terminal of the first switching output stage when the first switching element is switched from an on state to an off state, and the second circuit Adjusting the direction of the current flowing through the switching output terminal of the first switching output stage when the switching element switches from the on-state to the off-state so as to be opposite to the load; The direction of the current flowing through the switching output terminal of the second switching output stage when the element switches from the on state to the off state is the load direction, and the fourth switching element is from the on state to the off state. The direction of the current flowing through the switching output terminal of the second switching output stage when switching is opposite to the load D class amplifier, characterized in that the sea urchin adjustment. The inductance value of the series circuit of the coil, D class amplifier according to claim 1, characterized in that less than the inductance value of the coil of the low-pass filter circuit. The inductance value of the coil of the first series circuit is smaller than the inductance value of the coil of the first low-pass filter circuit,
The inductance value of the coil of the second series circuit, D class amplifier of claim 2, wherein the smaller than the inductance value of the coil of the second low-pass filter circuit. The inductance value of the series circuit of the coil, the inductance value of the coils of the first low-pass filter circuit, and, according to claim 3, wherein smaller than the inductance value of the coils of the second low-pass filter circuit D-class amplifier.

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