JP2007104576A - Switching circuit and digital amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching circuit and a digital amplifier capable of improving the sound quality by eliminating noise produced in the circuit. <P>SOLUTION: The full-bridge switching circuit includes two sets of switching output stages carrying out switching operations on the basis of a drive voltage supplied from a power supply; and low pass filters provided to a final stage in the two sets of the switching output stages, and capacitors respectively configuring the low pass filters. The capacitors are uniformly shared by a power supply side and a ground side, and connected to ground in terms of a high frequency component so as to share noises caused in switching operations by the ground side and the power supply side for cancellation, thus preventing the deterioration in the sound quality due to the noises. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a switching circuit and a digital amplifier, and is suitable for application to, for example, a full-bridge digital amplifier for audio (so-called class D amplifier).

2. Description of the Related Art Conventionally, audio full-bridge class D amplifiers have been proposed that convert an audio signal into a pulse shape by a PWM (Pulse Width Modulation) method and the like and amplify the signal to supply an output audio signal to a speaker (For example, refer to Patent Document 1).
JP 2005-167470 A

  In practice, as shown in FIG. 5, the class D amplifier device 1 is a so-called BTL (Bridged (or Balanced)) by transistors QF1 to QF4 composed of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that constitute two sets of switching output stages. A digital amplifier circuit 2 having a (Transformer Less) circuit is formed, and pulse-like input audio signals Si1 to Si4 PWM-modulated by a preprocessing unit (not shown) are input to the transistors QF1 to QF4 of the digital amplifier circuit 2.

  The digital amplifier circuit 2 amplifies the pulsed input audio signals Si1 to Si4 by the switching operation of the transistors QF1 to QF4 to which a voltage (for example, about 50 V) from the DC power source E is applied, and these are formed by the coil L1 and the capacitor C1. Is sent to a low-pass filter LPF2 formed by a coil L2 and a capacitor C2.

  Here, in the digital amplifier circuit 2, the transistors QF2 and QF3 are turned off when the transistors QF1 and QF4 are turned on, and the transistors QF2 and QF3 are turned on when the transistors QF1 and QF4 are turned off. It is controlled. In other words, in the class D amplifier device 1, the transistors QF1 and QF2 constituting the first switching output stage and the transistors QF3 and QF4 constituting the second switching output stage are respectively complementarily pushed-pull operated. Yes.

  The digital amplifier circuit 2 obtains output audio signals So1 and So2 by removing high-frequency components of the pulsed input audio signals Si1 to Si4 by the low-pass filters LPF1 and LPF2, and outputs them to the input terminals St1 and St2 of the speaker SP1, respectively. Supply.

  As a result, the class D amplifier device 1 applies the potential difference between the output audio signals So1 and So2 supplied to the input terminals St1 and St2 of the speaker SP1 to the speaker SP1, and thus changes the potential difference from the speaker SP1. It is designed to generate a sound that responds.

  By the way, in the class D amplifier device 1 having such a configuration, noise components NZ1 such as ringing noise and jitter noise due to the high-speed switching operation of the transistors QF1 to QF4 in the digital amplifier circuit 2 are generated.

  Here, as shown in FIG. 6, the ringing noise is caused by a waveform sag when switching operation is performed in accordance with the pulse-like input audio signals Si1 to Si4, and the low-pass filters LPF1 and LPF2 have very high frequencies. Appears as audible band noise after passing.

  In this case, in the class D amplifier device 1, not only the noise sound corresponding to the noise component NZ1 is output from the speaker SP1, but also the noise current corresponding to the noise component NZ1 when the transistor QF1 and the transistor QF4 are on, for example. Since Ni1 wraps around from the capacitor C1 of the low-pass filter LPF1 through the capacitor C2 of the low-pass filter LPF1, a noise voltage NV1 (NV1 = Ni1 × R1) is generated by the resistance component R1 and the noise current Ni1 due to the printed pattern of the board. The influence of the noise voltage NV1 also affects other adjacent channels.

  For this reason, the class D amplifier device 1 has a problem that the sound quality of the sound generated from the speaker SP1 and the sound quality of the sound generated from the speaker of another adjacent channel are also deteriorated.

  The present invention has been made in consideration of the above points, and an object of the present invention is to propose a full-bridge type switching circuit and a digital amplifier capable of improving noise quality by removing noise generated in the circuit.

  In order to solve such a problem, in the present invention, in a full-bridge type switching circuit, two switching output stages that perform a switching operation based on a driving voltage supplied from a power supply unit, and the two switching output stages A low-pass filter provided in the final stage is distributed to the ground side and the power supply side evenly by grounding the capacitors that make up the low-pass filter, so that noise generated by the switching operation is distributed to the ground side and the power supply side to cancel each other. Can be made.

  In the present invention, in a digital amplifier having a full-bridge type switching circuit, two sets of switching output stages for amplifying a pulsed input signal by performing a switching operation based on a driving voltage supplied from a power supply unit; A low-pass filter provided at the final stage of the two sets of switching output stages, and by uniformly distributing and grounding the capacitors constituting the low-pass filter to the ground side and the power supply side, noise generated by the switching operation is reduced. They can be distributed to the ground side and the power supply side to cancel each other.

  According to the present invention, in a full-bridge type switching circuit, two switching output stages that perform a switching operation based on a driving voltage supplied from a power supply unit and the final stage of the two sets of switching output stages are provided. By providing a low-pass filter and grounding the capacitors constituting the low-pass filter uniformly to the ground side and the power supply side, noise generated by the switching operation can be distributed to the ground side and the power supply side to cancel each other. Thus, it is possible to realize a full-bridge type switching circuit that can improve noise quality by removing noise generated in the circuit.

  According to the present invention, in the digital amplifier having a full bridge type switching circuit, two sets of switching output stages for amplifying a pulsed input signal by performing a switching operation based on a drive voltage supplied from a power supply unit. And a low-pass filter provided in the final stage of the two sets of switching output stages, and noise generated by the switching operation by uniformly distributing and grounding the capacitors constituting the low-pass filter to the ground side and the power supply side Can be distributed to the ground side and the power source side to cancel each other, thus realizing a digital amplifier capable of improving noise quality by removing noise generated in the circuit.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Class D amplifier device according to the first embodiment (1-1) Circuit configuration of the class D amplifier device according to the first embodiment In FIG. Reference numeral 11 denotes the full bridge type D-class amplifier device according to the first embodiment as a whole, and a digital amplifier circuit 12 in which a so-called BTL circuit is formed by transistors QF1 to QF4 composed of MOSFETs constituting two sets of switching output stages. The pulse-like input audio signals Si1 to Si4 PWM-modulated by a preprocessing unit (not shown) are input to the transistors QF1 to QF4 of the BTL circuit.

  The digital amplifier circuit 12 amplifies the pulsed input audio signals Si1 to Si4 by the switching operation of the transistors QF1 to QF4 to which the voltage (about 50 V) from the DC power source E is applied, and these are amplified from the coil L1 and the capacitors C3 and C4. And a low-pass filter LPF4 including a coil L2 and capacitors C5 and C6.

  Here, the low-pass filter LPF3 grounds the capacitor C3 to the ground side while keeping the coil L1 forming the low-pass filter LPF1 in the conventional class D amplifier device 1 (FIG. 5) as it is, and connects the capacitor C4 to the DC power source E side. Also, it is configured by uniformly distributing and grounding.

  The capacitors C3 and C4 are set so that the capacitance thereof is half that of the capacitor C1 of the low-pass filter LPF1 in the conventional class D amplifier device 1. As described above, in the low-pass filter LPF3, the capacitors C3 and C4 having a half capacity of the capacitor C1 in the low-pass filter LPF1 (FIG. 5) are dividedly grounded to the ground side and the power source side.

  As a result, the class D amplifier device 11 can be viewed as if the DC power source E is also grounded when viewed from the digital amplifier circuit 12, since the capacitor C4 cuts the output voltage of the DC power source E. And C4 are equivalently connected in parallel, and finally the low-pass filter LPF3 has the same frequency characteristics as the cutoff frequency of the low-pass filter LPF1 in the conventional class D amplifier device 1.

  As for the low-pass filter LPF4, the capacitor C5 is grounded to the ground side while the coil L2 forming the low-pass filter LPF2 in the conventional class D amplifier device 1 is left as it is, and the capacitor C6 is evenly connected to the DC power source E side. It is configured by sorting and grounding.

  The capacities of the capacitors C5 and C6 are also set to be half that of the capacitor C2 of the low-pass filter LPF2 in the conventional class D amplifier device 1. As described above, in the low-pass filter LPF4, the capacitors C5 and C6 each having a half capacity of the capacitor C2 in the low-pass filter LPF2 are dividedly grounded to the ground side and the power supply side.

  Also in this case, the digital amplifier circuit 12 can be regarded as the same as the DC power source E being grounded because the capacitor C6 cuts the output voltage of the DC power source E when viewed from the digital amplifier circuit 12. And C6 are connected in parallel, and finally the low-pass filter LPF4 has the same frequency characteristics as the cut-off frequency of the low-pass filter LPF2 in the conventional class D amplifier device 1.

  The digital amplifier circuit 12 is configured such that when the transistors QF1 and QF4 are on, the transistors QF2 and QF3 are off, and when the transistors QF1 and QF4 are off, the transistors QF2 and QF3 are on. The transistors QF1 and QF2 constituting the first switching output stage and the transistors QF3 and QF4 constituting the second switching output stage are each complementarily operated by a push-pull operation.

  The digital amplifier circuit 12 obtains output audio signals So3 and So4 by removing high-frequency components of the pulsed input audio signals Si1 to Si4 by the low-pass filters LPF3 and LPF4, and outputs them to the input terminals St1 and St2 of the speaker SP1, respectively. Supply.

  As a result, the class D amplifier device 11 applies the potential difference between the output audio signals So3 and So4 supplied to the input terminals St1 and St2 of the speaker SP1 to the speaker SP1, thus changing the potential difference from the speaker SP1. It is made to generate the sound according to.

  By the way, in the digital amplifier circuit 12, when the noise component NZ1 is generated by the switching operation of the transistors QF1 to QF4, the noise current Ni2 corresponding to the noise component NZ1 flows from the power source side to the capacitor C4, and the noise current Ni2 is supplied to the capacitor C3. To the ground side.

  By the way, since the capacitance of the capacitor C3 and the capacitor C4 is half that of the capacitor C1, the impedance of the noise current Ni2 is twice that of the capacitor C1, and as a result, the current amount of the noise current Ni2 is also the noise current Ni1 (FIG. 5). ) Of 1/2.

  At this time, in the digital amplifier circuit 12, since there are resistance components R1 and R2 due to the printed pattern of the board, a noise voltage NV2 (NV2 = 1/2 * Ni2 * R1) corresponding to the noise current Ni2 appears on the ground side and the noise voltage NV3 (NV3 = 1/2 * Ni2 * R2) appears on the power supply side.

  At this time, the class D amplifier device 11 synthesizes the noise voltage NV2 and the noise voltage NV3 on the input terminal St2 side of the speaker SP1, and becomes a noise component NZ1 ′ having substantially the same level as the initial noise component NZ1, and the input of the speaker SP1. It is supplied to the terminal St2.

  Therefore, even if the noise component NZ1 is input to the input terminal St1 of the speaker SP1, the digital amplifier circuit 12 is a composite result of the noise voltage NV2 that appears on the ground side and the NV3 that appears on the power supply side due to the basic action of the BTL circuit. Since a certain noise component NZ1 ′ is supplied to the input terminal St2 of the speaker SP1, there is almost no potential difference between the input terminals St1 and St2 on both sides of the speaker SP1, resulting in a response to the noise component NZ1. The noise sound can be prevented from being generated from the speaker SP1.

  As described above, the class D amplifier device 11 confines the noise component NZ1 inside the digital amplifier circuit 12 by the basic operation of the BTL circuit, and cancels the noise component NZ1 inside the circuit.

  Further, the digital amplifier circuit 12 generates a noise voltage NV2 due to the noise current Ni2 and resistance component R1 flowing on the ground side, and generates a noise voltage NV3 due to the noise current Ni2 and resistance component R2 flowing on the power supply side. The potential shifts by the amount of the noise voltage NV2, and the reference potential on the power source side also shifts by the amount of the noise voltage NV3, so that the noise for the other adjacent channels becomes invisible.

  For this reason, the digital amplifier circuit 12 can avoid an adverse effect (noise) on adjacent other channels, like the conventional class D amplifier device 1 (FIG. 5) in which only the ground-side reference potential is fluctuated. ing.

  In the digital amplifier circuit 12, the resistance components R1 and R2 due to the print pattern appear parallel to the reference of the DC power supply E from the low-pass filter LPF3 and the low-pass filter LPF4, and the generated noise voltages NV2 and NV3 are Since the noise voltage NV1 of the conventional class D amplifier device 1 is ½, the influence of malfunction and unnecessary radiation of a system control microcomputer (not shown) can be greatly reduced.

(1-2) Operation and Effect in First Embodiment In the configuration described above, the digital amplifier circuit 12 of the class D amplifier device 11 has a capacitance half that of the capacitor C1 in the low-pass filter LPF1 in the conventional class D amplifier device 1. The capacitors C3 and C4 are divided into the ground side and the power source side, and are uniformly divided and grounded, whereby the secondary low-pass filter LPF3 and coil L2 including the coil L1, capacitors C3 and C4, and the secondary including the capacitors C5 and C6. Low pass filter LPF4.

  Thus, in the digital amplifier circuit 12 of the class D amplifier device 1, the noise component NZ1 generated by the switching operation is input to the input terminal St1 of the speaker SP1, while it is generated on the noise voltage NV2 generated on the ground side and on the power supply side. Since the noise component NZ1 ′, which is the result of the synthesis of the noise voltage NV3, is also supplied to the input terminal St2 of the speaker SP1, a potential difference due to the noise component NZ1 occurs at the input terminals St1 and St2 on both sides of the speaker SP1. Therefore, it is possible to prevent the noise sound corresponding to the noise component NZ1 from being generated from the speaker SP1.

  That is, the digital amplifier circuit 12 obtains the noise component NZ1 ′ by synthesizing the noise voltage NV3 and the noise voltage NV2 corresponding to the noise current Ni2, and cancels the noise component NZ1 generated by the switching operation by the noise component NZ1 ′. As a result, the noise component NZ1 can be removed while confined in the closed loop circuit of the digital amplifier circuit 12.

  Also, the digital amplifier circuit 12 generates a noise voltage NV2 due to the noise current Ni2 and resistance component R1 flowing on the ground side, and generates a noise voltage NV3 due to the noise current Ni2 and resistance component R2 flowing on the DC power supply E side. Is shifted by the noise voltage NV2, and the reference potential on the DC power source E side is also shifted by the noise voltage NV3, so that only the ground-side reference potential is shaken. As shown in FIG. 1, the adverse effect of the noise component NZ1 on other channels can be avoided in advance.

  According to the above configuration, the digital amplifier circuit 12 of the class D amplifier device 11 can remove the noise component NZ1 generated in the digital amplifier circuit 12 by the switching operation and prevent the sound quality deterioration of the sound output from the speaker SP1. In addition, malfunction of a system control microcomputer (not shown), unnecessary radiation can be drastically reduced, and adverse effects on other adjacent channels can be avoided.

(2) Class D amplifier device in the second embodiment (2-1) Circuit configuration of the class D amplifier device in the second embodiment In FIG. Reference numeral 21 denotes a two-channel full-bridge class D amplifier device according to the second embodiment as a whole, and so-called BTL circuits are formed by transistors QF1 to QF4 composed of MOSFETs constituting two sets of switching output stages. A first digital amplifier circuit 22 and a second digital amplifier circuit 23 in which a so-called BTL circuit is formed by transistors QF5 to QF8, which are similarly composed of MOSFETs constituting two sets of switching output stages, are shown in FIG. Pulse-shaped input audio signals Si1 to Si4 PWM-modulated by the processing unit are converted into transistors QF1 to QF1. In addition to being input to QF4, pulsed input audio signals Si5 to Si8 are input to transistors QF5 to QF8.

  The first digital amplifier circuit 22 amplifies the pulsed input audio signals Si1 to Si4 by the switching operation of the transistors QF1 to QF4 to which a voltage (for example, about 50 V) from the DC power source E is applied, and these are amplified by the coil L1 and the capacitor C1. To a low-pass filter LPF1 consisting of a coil L2 and a capacitor C2.

  The capacitors C1 and C2 constituting the low-pass filters LPF1 and LPF2 are grounded to the ground side via a resistance component R1 due to a printed pattern on the board.

  Here, in the first digital amplifier circuit 22, when the transistors QF1 and QF4 are on, the transistors QF2 and QF3 are off, and when the transistors QF1 and QF4 are off, the transistors QF2 and QF3 are on. Thus, the transistors QF1 and QF2 constituting the first switching output stage and the transistors QF3 and QF4 constituting the second switching output stage are respectively complementarily push-pull operated.

  The second digital amplifier circuit 23 amplifies the pulsed input audio signals Si5 to Si8 by the switching operation of the transistors QF5 to QF8 to which the voltage (about 50 V) from the DC power source E is applied, and these are amplified from the coil L3 and the capacitor C7. The low-pass filter LPF5 and the low-pass filter LPF6 including the coil L4 and the capacitor C8 are transmitted.

  The capacitors C7 and C8 constituting the low-pass filters LPF5 and LPF6 have the same capacity as the capacitors C1 and C2 constituting the low-pass filters LPF1 and LPF2, and the substrate is similar to the low-pass filters LPF1 and LPF2. Is grounded to the power supply side via a resistance component R2 of the print pattern.

  That is, in the class D amplifier device 21, as a whole including the first digital amplifier circuit 22 and the second digital amplifier circuit 23, the capacitors C1 and C2 and the capacitors C7 and C8 are uniformly distributed to the ground side and the power supply side, respectively. Sorted and grounded.

  Therefore, since the capacitors C7 and C8 cut the output voltage of the DC power supply E, the class D amplifier device 21 can be regarded as the same as the DC power supply E being grounded, and the capacitors C1 and C2, the capacitors C3, This is equivalent to C4 being connected in parallel.

  The second digital amplifier circuit 23 is configured such that when the transistors QF5 and QF8 are on, the transistors QF6 and QF7 are off, and when the transistors QF5 and QF8 are off, the transistors QF6 and QF7 are on. The transistors QF5 and QF6 constituting the first switching output stage and the transistors QF7 and QF8 constituting the second switching output stage are respectively complementarily pushed-pull operated.

  In particular, in the class D amplifier device 21, the transistors QF1 and QF4 of the first digital amplifier circuit 22 and the transistors QF5 and QF8 of the second digital amplifier circuit 23 are switched in a synchronized state, and the first digital amplifier circuit 22 is switched. The transistors QF2 and QF3 and the transistors QF6 and QF7 of the second digital amplifier circuit 23 are switched in a synchronized state.

  The first digital amplifier circuit 22 obtains output audio signals So1 and So2 by removing high-frequency components of the pulsed input audio signals Si1 to Si4 by the low-pass filters LPF1 and LPF2, and these are obtained as input terminals St1 and St1 of the speaker SP1, respectively. Supply to St2.

  As a result, the class D amplifier device 21 applies the potential difference between the output audio signals So1 and So2 supplied to the input terminals St1 and St2 of the speaker SP1 to the speaker SP1, thus changing the potential difference from the speaker SP1. It is made to generate the sound according to.

  On the other hand, the second digital amplifier circuit 23 also obtains output audio signals So5 and So6 by removing high-frequency components of the pulsed input audio signals Si5 to Si8 by the low-pass filters LPF5 and LPF6, which are respectively input to the speaker SP2. Supply to terminals St3 and St4.

  As a result, the class D amplifier device 21 applies the potential difference between the output audio signals So5 and So6 supplied to the input terminals St3 and St4 of the speaker SP2 to the speaker SP2, thus changing the potential difference from the speaker SP2. It is made to generate the sound according to.

  Incidentally, in the first digital amplifier circuit 22, when the noise component NZ1 is generated by the switching operation of the transistors QF1 to QF4, the noise current Ni1 corresponding to the noise component NZ1 flows from the capacitor C1 to the ground side.

  Similarly, in the second digital amplifier circuit 23, when the noise component NZ3 is generated by the switching operation of the transistors QF5 to QF8 synchronized with the switching operation of the transistors QF1 to QF4, the noise current Ni3 corresponding to the noise component NZ3 is a DC power source. It flows from the E side to the capacitor C7.

  At this time, in the first digital amplifier circuit 22, a noise voltage NV1 (NV1 = Ni1 * R1) corresponding to the noise current Ni1 appears on the ground side, and also in the second digital amplifier circuit 23, a noise voltage corresponding to the noise current Ni3. NV3 (NV3 = Ni3 * R2) appears on the DC power supply E side.

  Accordingly, in the class D amplifier device 21, the noise component NZ1 ′ corresponding to the noise voltage NV1 generated by the first digital amplifier circuit 22 wraps around the input terminal St4 of the speaker SP2, and the noise component NZ3 input to the input terminal St3 of the speaker SP2. Is canceled by the noise component NZ1 ', the noise sound corresponding to the noise component NZ3 can be greatly reduced.

  Similarly, in the class D amplifier device 21, a noise component NZ3 ′ corresponding to the noise voltage NV3 generated in the second digital amplifier circuit 23 wraps around the input terminal St2 of the speaker SP1, and is input to the input terminal St1 of the speaker SP1. Since the noise component NZ1 is canceled by the noise component NZ3 ′, the noise sound corresponding to the noise component NZ1 can be greatly reduced.

  Thus, the class D amplifier device 21 has the noise component NZ1 and the noise inside the first digital amplifier circuit 22 and the second digital amplifier circuit 23 by the basic operation of the BTL circuit in the first digital amplifier circuit 22 and the second digital amplifier circuit 23. The component NZ3 is confined, and the original noise component NZ1 and noise component NZ3 are canceled by the noise components NZ3 ′ and NZ1 ′ generated in the circuit.

  Further, the class D amplifier device 21 generates a noise voltage NV1 (NV1 = Ni1 × R1) on the ground side, and also generates a noise voltage NV3 (NV3 = Ni3 × R2) on the DC power supply E side. Since the potential shifts by the amount of the noise voltage NV1 and the reference potential on the DC power source E side also shifts by the amount of the noise voltage NV3, the noise amount for the adjacent other channel becomes invisible, and the adverse effect on the adjacent other channel. Can be avoided in advance.

(2-2) Operation and Effect in Second Embodiment In the above configuration, in the class D amplifier device 21, the capacitors C1 and C2 in the first digital amplifier circuit 22 are grounded to the ground side, and the second digital amplifier circuit The capacitors C7 and C8 at 23 are distributed to the ground side and the DC power supply E side so as to be grounded to the DC power supply E side, and are grounded uniformly.

  As a result, the class D amplifier device 21 cancels out the noise component NZ3 generated by the second digital amplifier circuit 23 with the noise component NZ1 ′ generated according to the noise current Ni1 of the first digital amplifier circuit 22, and the second digital amplifier circuit Since the noise component NZ1 generated by the first digital amplifier circuit 22 can be canceled out by the noise component NZ3 ′ generated according to the noise current Ni3 of 23, the class D amplifier device 11 (FIG. 1) according to the first embodiment. ), The noise noise corresponding to the noise components NZ1 and NZ3 generated by the switching operation can be reduced without increasing the number of capacitors.

  That is, the class D amplifier device 21 can cancel out the noise component NZ1 and the noise component NZ3 in a closed loop circuit formed by the first digital amplifier circuit 22 and the second digital amplifier circuit 23.

  Further, the class D amplifier device 21 shifts the ground-side reference potential by the noise voltage NV1 by the noise voltage NV1 generated by the first digital amplifier circuit 22, and is powered by the noise voltage NV3 generated by the second digital amplifier circuit 23. Since the reference potential on the side also shifts by the noise voltage NV3, the adverse effects of the noise components NZ1 and NV3 on the other adjacent channels as in the conventional class D amplifier device 1 in which only the reference potential on the ground side is shaken are previously detected. It can be avoided.

  According to the above configuration, the class D amplifier device 21 removes the noise component NZ1 generated by the switching operation of the first digital amplifier circuit 22 and the noise component NZ3 generated by the switching operation of the second digital amplifier circuit 23 to remove the speaker. It is possible to prevent deterioration in sound quality of sounds output from SP1 and SP2, and to avoid adverse effects on other adjacent channels in advance.

(3) Experimental Results Next, the left and right front speakers and the rear in the class D amplifier device 11 in the first embodiment, the class D amplifier device 21 in the second embodiment, and the conventional class D amplifier device 1 described above. The result of actual measurement of the residual noise of the speaker is verified by comparing with each other.

  As shown in FIG. 3, in the class D amplifier device 11 according to the first embodiment, the residual noise is improved by about 10 [dBm] as a whole compared to the conventional class D amplifier device 11, and the second Also in the class D amplifier device 21 in this embodiment, the overall improvement is about 5 [dBm] compared to the conventional class D amplifier device 11.

  In other words, the class D amplifier devices 11 and 21 in the first and second embodiments are configured to cancel the noise components NZ1 and NZ3 by utilizing the basic operation of the BTL circuit, so that the canceling action is effective. It was demonstrated that residual noise was reduced.

(4) Other Embodiments In the above-described first embodiment, the switching circuit of the present invention is applied to the class D amplifier device 11 having a one-channel configuration, and in the above-described second embodiment. Although the case where the switching circuit of the present invention is applied to the class D amplifier device 21 having a two-channel configuration has been described, the present invention is not limited to this, and the switching circuit of the present invention can be divided into a plurality of channels (see FIG. For example, the present invention may be applied to a class D amplifier device 31 having a 4-channel configuration.

  In this class D amplifier device 31, a first digital amplifier circuit 32 to a fourth digital amplifier circuit 35 are provided so as to correspond to four channels. Among the capacitors C11 to C18 constituting the low-pass filters LPF11 to LPF18, capacitors C11 to C14 are uniformly distributed to the ground side, and capacitors C15 to C18 are uniformly distributed to the DC power source E side to be grounded.

  At this time, in the class D amplifier device 31, the transistors QF11 and QF14, the transistors QF15 and QF18, the transistors QF19 and QF22, the transistors QF23 and QF26 are synchronized, the transistors QF12 and QF13, the transistors QF16 and QF17, The transistors QF20 and QF21 are synchronized with the transistors QF24 and QF25.

  In this way, the class D amplifier device 31 replaces the capacitors C11 to C18 constituting the low pass filters LPF11 to LPF18 of the first digital amplifier circuit 32 to the fourth digital amplifier circuit 35 corresponding to an even number of channels with the ground side and the DC power supply E. The noise components (not shown) generated by the switching operations of the first digital amplifier circuit 32 to the fourth digital amplifier circuit 35 are generated in accordance with the noise components by uniformly distributing them to the ground and grounding them. The voltages can be canceled out by the inside of the circuit, and noise components output from the speakers SP11 to SP13 are reduced.

  Although not shown, in the class D amplifier device 31, the capacitors C13 and C14 of the second digital amplifier circuit 33 are grounded to the DC power supply E side, and the capacitors C17 and C18 of the fourth digital amplifier circuit 35 are grounded to the ground side. In short, the combination is not limited as long as the capacitors C11 to C18 are uniformly distributed to the ground side and the DC power supply E side and grounded.

  In the first and second embodiments described above, the case where the PWM-modulated pulsed input audio signals Si1 to Si8 are amplified has been described. However, the present invention is not limited to this, and the PDM ( A pulse density modulation (DSD) modulated or DSD (Direct Stream Digital) modulated input audio signal may be amplified.

  In the first and second embodiments described above, the case where the present invention is applied to the class D amplifier devices 11 and 21 that amplify the input audio signals Si1 to Si8 has been described. However, the present invention may be applied to a digital amplifier device that amplifies various signals.

  Furthermore, in the first and second embodiments described above, the description has been given of the case where the transistors QF1 to QF8 made of MOSFETs are used as the switching output stage. However, the present invention is not limited to this, but from a junction FET or the like. Any other switching means may be used as long as it is a voltage driven transistor.

1 is a schematic circuit diagram illustrating a configuration of a class D amplifier device according to a first embodiment. It is a rough-line circuit diagram which shows the structure of the class D amplifier apparatus in 2nd Embodiment. It is a chart which shows measured data. It is a rough-line circuit diagram which shows the structure of the class D amplifier apparatus in other embodiment. It is a rough-line circuit diagram about the structure of the conventional class D amplifier apparatus. It is a basic diagram with which it uses for description of ringing noise.

Explanation of symbols

  1, 11, 21, 31... Class D amplifier device 2, 12, 22, 32... First digital amplifier circuit, 23, 33... Second digital amplifier circuit, 34. ... 4th digital amplifier circuit.

Claims (4)

In full-bridge type switching circuit,
Two sets of switching output stages for performing a switching operation based on a driving voltage supplied from a power supply unit;
A low-pass filter provided at the final stage of the two sets of switching output stages,
A switching circuit characterized in that the capacitors constituting the low-pass filter are uniformly distributed to the ground side and the power supply side and grounded. 2. The switching circuit according to claim 1, wherein the capacitors have the same capacitance of a ground side capacitor to be grounded to the ground side and a power source side capacitor to be grounded to the power source side. The two sets of switching output stages are provided in a plurality according to the number of the final stages, and perform the switching operation in a synchronized state based on the drive voltage supplied from the power supply unit. 2. The switching circuit according to 1. In a digital amplifier having a full bridge type switching circuit,
Two sets of switching output stages for amplifying a pulsed input signal by performing a switching operation based on a driving voltage supplied from a power supply unit;
A low-pass filter provided at the final stage of the two sets of switching output stages,
A digital amplifier characterized in that the capacitors constituting the low-pass filter are uniformly distributed to the ground side and the power supply side and grounded.

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