CN101165224A - Germanium doping silicon wafer with internal purity absorbing function and preparation method thereof - Google Patents
Germanium doping silicon wafer with internal purity absorbing function and preparation method thereof Download PDFInfo
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- CN101165224A CN101165224A CNA2007100704014A CN200710070401A CN101165224A CN 101165224 A CN101165224 A CN 101165224A CN A2007100704014 A CNA2007100704014 A CN A2007100704014A CN 200710070401 A CN200710070401 A CN 200710070401A CN 101165224 A CN101165224 A CN 101165224A
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Abstract
The present invention discloses Ge doped silicon chip possessing inward impurity gettering function and its preparation process. The silicon chip has oxygen concentration of (5-15)x10<17>/cu cm, Ge concentration of 1x10<13>-1x10<20>/cu cm, clean region width of 10-100 microns, and bulk microdefect density of 1x10<5>-1x10<10>/cu cm. In the inward impurity gettering process based on quick heat treatment, the small amount of Ge atoms in the silicon chip can form complex with the injected voids to promote oxygen deposition and to form one clean region in certain width near the surface of the silicon chip while increasing the inside bulk microdefect density obviously. The process has high inward impurity gettering effect, and the silicon chip is applied in making integrated circuit and can result in high product quality.
Description
Technical field
The present invention relates to a kind of germanium doping silicon wafer, belong to semiconductor applications with internal impurity absorbing function.
Background technology
The pulling of crystals silicon chip is widely used in the manufacturing of integrated circuit (IC) chip.It is 1 * 10 that Chinese patent CN 1422988A discloses a kind of concentration that contains
13～1 * 10
21Cm
-3Phosphorus or boron or arsenic or antimony, concentration is 1 * 10
13～1 * 10
20Cm
-3The micro germanium-doped vertical-pulling silicon single crystal of germanium, germanium doping silicon wafer prepared therefrom can interact with point defect (from gap Siliciumatom, room) owing to adulterated germanium atom, has the effect that suppresses primary microdefect (particularly cavity blemish) in the silicon single-crystal, can effectively improve the quality and the yield rate of silicon single-crystal, help reducing the production cost of pulling of crystals silicon chip.
Along with the continuous development of semiconductor device art, integrated circuit technique is only required the high-purity area free from defect that forms 2～5 μ m at the nearly upper layer of silicon chip, is called clear area or clean area (DZ).Reach such purpose, adopt the technology of outer gettering or intrinsic gettering usually.Generally contain 10 in the Czochralski silicon wafer
17～10
18Cm
-3The oxygen impurities of the order of magnitude, the physical strength that it can strengthen Czochralski silicon wafer on the one hand reduces owing to the warpage that causes in the device technology thermal cycling, thereby does not influence the alignment precision of photoetching process; Can in wafer bulk, precipitate and form secondary defect (BMD) by suitable heat treatment process oxygen impurities on the other hand, and in the external diffusion formation area free from defect of the nearly surf zone of silicon chip owing to oxygen, Here it is so-called systemic impurity process (Tan, T.Y., et al., AppliedPhyscis Letter 30,175 (1977)).
Defect area can be absorbed inevitable metal contamination in the device fabrication in the body that the silicon chip systemic impurity process forms, and the clean area on the nearly surface of silicon chip can be used as the active area of unicircuit, thereby systemic impurity process has great importance to the raising of unicircuit rate in blocks.The intrinsic gettering phenomenon of Czochralski silicon wafer in 1976 by reported first (Rozgonyi, G.A., et al., Journal of the Electrochemistry Society 123,1910 (1976)), develop the standard systemic impurity process (Nagasawa that so-called " height-low-Gao " three-step annealing after gradually, et al., Applied Physcis Letter, 37,622 (1980); Peibt, H., et al., Physica Status Solidi, A 68,253 (1981); Peibt, H., et al., Physica Status Solidi, A 68,253 (1981)).That is: the first step is annealed being higher than under 1100 ℃ the temperature, and the oxygen impurities external diffusion that makes the nearly surf zone of silicon chip is to form clean area, and this step carries out under inert atmosphere usually; Second step is in 600～750 ℃ of annealing down of low temperature, to form the core of oxygen precipitation in wafer bulk; The 3rd step 1000～1100 ℃ of middle high temperature down annealing make the oxygen precipitation core that in second step annealing, forms grow up and form secondary defect.Thereby, forming flawless clean area on the nearly surface of silicon chip, formation has highdensity microdefect (oxygen precipitation and secondary defect) in vivo.More than each heat treatment step generally all in the diffusion heat treatments stove, finish.Usually, the power of the ability of intrinsic gettering can be represented with the width of clean area and the density of bulky micro defect.
The heat budget of three step systemic impurity process is bigger, and relatively poor with the processing compatibility of unicircuit.Continuous progress along with device technology, the widespread use of shallow-junction devices and super shallow-junction devices requires to reduce the thermal treatment temp (K.Sueoko in the device making technics process, et al., Solid State Phenomena, 82-84,49 (2002)), the intrinsic gettering effect of the standard systemic impurity process of traditional " height-low-Gao " three-step annealing generation also will be lowered.And, further increase along with the Czochralski silicon wafer diameter, the magnetic control pulling technique is widely used in the preparation (H.Yu of the pulling of crystals silicon chip of diameter more than 8 inches, et al., Journal ofInorganic Materials, 20,453 (2005)), the oxygen concn in the silicon chip since in the crystal pulling process silicon melt the body convection current and be suppressed and descend inevitably.And the decline of oxygen impurity concentration in the monocrystalline silicon piece, oxygen precipitation produces the ability of bulky micro defect in the silicon chip with weakening, thereby reduces the Internal Gettering of Silicon Wafers effect.Therefore, the intravital microdefect density of large diameter Czochralski silicon wafer is lower, and the gettering effect of poisonous metal is awaited further to improve.
Employing can significantly reduce the heat budget of systemic impurity process based on the intrinsic gettering technology of rapid thermal treatment process, and can inject a certain amount of room in silicon chip, promotes the generation of oxygen precipitation and secondary defect thereof.Adopt simultaneously and in silicon chip, carry out micro-doping techniques, the formation complex body relevant with foreign atom and room in the wafer bulk will be made, strengthen the nucleation ability of oxygen precipitation, significantly improve the density of interior oxygen precipitation of wafer bulk and secondary defect thereof, thereby to the gettering effect of poisonous metal, improve device yield in the raising device manufacturing processes.
Summary of the invention
The objective of the invention is to propose a kind of germanium doping silicon wafer and intrinsic gettering thereof and form technology with higher internal impurity absorbing function.
Germanium doping silicon wafer with internal impurity absorbing function of the present invention, the oxygen concn of silicon chip are 5～15 * 10
17Cm
-3, germanium concentration is 1 * 10
13～1 * 10
20Cm
-3, it is characterized in that the clean area width is 10～100 μ m, bulky micro defect density is 1 * 10
5～1 * 10
10Cm
-3
Preparation method with germanium doping silicon wafer of internal impurity absorbing function of the present invention has following two kinds of schemes.
Scheme 1:
Preparation method with germanium doping silicon wafer of internal impurity absorbing function is characterized in that step is as follows, below each step all under argon gas or protection of nitrogen gas, carry out:
1) be 5～15 * 10 with oxygen concn
17Cm
-3, germanium concentration is 1 * 10
13～1 * 10
20Cm
-3The germanium-doped vertical-pulling silicon single crystal sheet, in rapid heat-treatment furnace 1100～1300 ℃ of insulations 5～100 seconds, then with 10～100 ℃/second rate of temperature fall with the silicon chip cool to room temperature;
2) will place the diffusion heat treatments stove through the silicon chip that step 1) is handled,, with 1～10 ℃ of/minute temperature rise rate silicon chip will be warmed up to 1000～1200 ℃ then 600～900 ℃ of insulations 4～50 hours;
3) will be through step 2) silicon chip handled places the diffusion heat treatments stove, 1000～1200 ℃ of insulations 4～30 hours, with 50～200 ℃ of/minute rate of temperature fall with the silicon chip cool to room temperature.
Scheme 2:
Preparation method with germanium doping silicon wafer of internal impurity absorbing function is characterized in that step is as follows, below each step all under argon gas or protection of nitrogen gas, carry out:
1) be 5～15 * 10 with oxygen concn
17Cm
-3, germanium concentration is 1 * 10
13～1 * 10
20Cm
-3The germanium-doped vertical-pulling silicon single crystal sheet, in rapid heat-treatment furnace 1100～1300 ℃ of insulations 5～100 seconds, then with 10～100 ℃/second rate of temperature fall with the silicon chip cool to room temperature;
2) will place the diffusion heat treatments stove through the silicon chip that step 1) is handled, 1000～1200 ℃ the insulation 4～30 hours after, again with 50～200 ℃ of/minute rate of temperature fall with the silicon chip cool to room temperature.
Beneficial effect of the present invention is:
The germanium atom that contains trace in the Czochralski silicon wafer of invention, after handling based on the systemic impurity process of rapid thermal treatment process, since germanium atom can be in silicon chip with rapid thermal treatment process in the room injected form certain complex body and promote oxygen precipitation to generate, has the flawless clean area of certain width in the formation of nearly surface in the silicon chip, and make intravital bulky micro defect (oxygen precipitation and secondary defect) density significantly improve, therefore, has higher intrinsic gettering ability, poisonous metal had better gettering effect, this silicon chip is applied to make unicircuit, can improve the yield rate of unicircuit.
Description of drawings
Fig. 1 is the cleavage surface defect distribution Photomicrograph of embodiment 1 ordinary straight pulled silicon wafer (CZ-Si) and Ge doped vertical pulling silicon chip (GCZ-Si), wherein, is that CZ-Si amplifies 200 times Photomicrograph (a), (b) is that GCZ-Si amplifies 200 times Photomicrograph.
Fig. 2 is the cleavage surface defect distribution Photomicrograph of embodiment 3 ordinary straight pulled silicon wafers (CZ-Si) and Ge doped vertical pulling silicon chip (GCZ-Si), wherein, is that CZ-Si amplifies 200 times Photomicrograph (a), (b) is that GCZ-Si amplifies 200 times Photomicrograph.
Embodiment
Embodiment 1
Choose 6 inches Ge doped vertical pulling silicon chips (GCZ-Si) of argon shield growth, germanium concentration is 1 * 10
18Cm
-3, oxygen concn is 9 * 10
17Cm
-3, resistivity is 10 ohmcms.In order in silicon chip, to form clean area and bulk defects district, silicon chip is incubated 60 seconds in 1260 ℃ in rapid heat-treatment furnace, drop to room temperature with 50 ℃/second rate of temperature fall then, then in the diffusion heat treatments stove in 750 ℃ of insulations 4 hours down, be warmed up to 1000 ℃ and with 2 ℃/minute temperature rise rate then 1000 ℃ of insulations 16 hours.All thermal treatment is all carried out under argon gas atmosphere.Silicon chip after the thermal treatment corroded 3 minutes through cleavage and in Sirtl preferential etch liquid, with OLYMPUS MX50 type microscope the defect distribution situation of cleavage surface was observed then and took pictures.
In order to do contrast, oxygen concn is all identical with resistivity, does not have the common czochralski silicon monocrystal (CZ-Si) of doped germanium atom also to experience identical processing.Fig. 1 has provided through after the aforesaid thermal treatment, the photo of the cleavage surface defect distribution of ordinary straight pulled silicon wafer (CZ-Si) and Ge doped vertical pulling silicon chip (GCZ-Si), wherein, (a) be that CZ-Si amplifies 200 times Photomicrograph (the clean area width is 25 μ m, and bulky micro defect density is 9 * 10
8Cm
-3), be that GCZ-Si amplifies 200 times Photomicrograph (the clean area width is 18 μ m, and bulky micro defect density is 2 * 10 (b)
9Cm
-3).From figure (a) and (b) as can be seen, after three step intrinsic gettering thermal treatment process, clean (DZ) district and bulky micro defect (BMD) district in CZ-Si and GCZ-Si, have all been formed, though the clean area width of GCZ-Si is more smaller than CZ-Si, but still can reach more than the 10 μ m of unicircuit manufacturing requirement.Show that thus the germanium doping silicon wafer that the present invention proposes can satisfy large-scale integrated circuit to form the requirement of high-purity zero defect thin layer on the nearly surface of silicon chip.In addition, pass through based on having formed the oxygen precipitation more more intensive in the GCZ-Si body behind the three step systemic impurity process of rapid thermal treatment process than CZ-Si, more highdensity oxygen precipitation of formation and secondary defect will help intrinsic gettering in the bulky micro defect district, can improve the gettering effect of silicon chip to poisonous metal in the device manufacturing processes.
Embodiment 2
Choose 8 inches Ge doped vertical pulling silicon chips of argon shield growth, germanium concentration is 1 * 10
15Cm
-3, oxygen concn is 6 * 10
17Cm
-3, resistivity is 15 ohmcms.Silicon chip is incubated 5 seconds down in 1300 ℃ in rapid heat-treatment furnace, drop to room temperature with 30 ℃/second rate of temperature fall then, then in the diffusion heat treatments stove in 650 ℃ of insulations 4 hours down, be warmed up to 1050 ℃ and with 3 ℃/minute temperature rise rate then 1050 ℃ of insulations 50 hours.All thermal treatment is all carried out under argon gas atmosphere.Can obtain having the silicon chip of intrinsic gettering ability, it has the flawless clean area that width is 14 μ m on the nearly surface of silicon chip, be 5 * 10 and have density in wafer bulk
9Cm
-3Bulky micro defect (oxygen precipitation and secondary defect).
Embodiment 3
Choose 5 inches Ge doped vertical pulling silicon chips (GCZ-Si) of argon shield growth, germanium concentration is 8 * 10
17Cm
-3, oxygen concn is 11 * 10
17Cm
-3, resistivity is 20 ohmcms.It is all identical with resistivity to choose oxygen concn, and the ordinary straight pulled silicon wafer (CZ-Si) that does not have doped germanium atom sheet as a comparison also experiences following processing.With silicon chip in rapid heat-treatment furnace in 1260 ℃ of down insulations 60 seconds, drop to room temperature with 40 ℃/second rate of temperature fall then, then in the diffusion heat treatments stove in 1050 ℃ of insulations 20 hours down.All thermal treatment is all carried out under argon gas atmosphere.Silicon chip after the thermal treatment corroded 3 minutes through cleavage and in Sirtl preferential etch liquid, with OLYMPUS MX50 type microscope the defect distribution situation of cleavage surface was observed then and took pictures.
Fig. 2 has provided through after the aforesaid thermal treatment, the photo of the cleavage surface defect distribution of ordinary straight pulled silicon wafer (CZ-Si) and Ge doped vertical pulling silicon chip (GCZ-Si), wherein, (a) be that CZ-Si amplifies 200 times Photomicrograph (the clean area width is 30 μ m, and bulky micro defect density is 7 * 10
7Cm
-3), be that GCZ-Si amplifies 200 times Photomicrograph (the clean area width is 45 μ m, and bulky micro defect density is 1 * 10 (b)
8Cm
-3).As seen from the figure, after two step intrinsic gettering thermal treatment process, tangible cleaning (DZ) district and bulky micro defect (BMD) district in GCZ-Si and CZ-Si, have all been formed, the width in DZ district is all more than 20 μ m, and formed the bulky micro defect more more intensive in the GCZ-Si wafer bulk than CZ-Si silicon chip, illustrate that thus the GCZ-Si silicon chip has higher intrinsic gettering ability than CZ-Si silicon chip.Show that thus the germanium doping silicon wafer that the present invention proposes can satisfy large-scale integrated circuit to forming high-purity zero defect thin layer on the nearly surface of silicon chip, forms the requirement of highdensity gettering point (bulky micro defect) in wafer bulk.
Embodiment 4
Choose 8 inches Ge doped vertical pulling silicon chips of argon shield growth, germanium concentration is 1 * 10
20Cm
-3, oxygen concn is 5 * 10
17Cm
-3, resistivity is 1 ohmcm.With silicon chip in rapid heat-treatment furnace in 1150 ℃ of down insulations 20 seconds, drop to room temperature with 10 ℃/second rate of temperature fall then, then in the diffusion heat treatments stove in 1000 ℃ of insulations 20 hours down.All thermal treatment is all carried out under argon gas atmosphere.Also can obtain having the silicon chip of intrinsic gettering ability, obtain having the flawless clean area that width is 25 μ m on the nearly surface of silicon chip, forming density in wafer bulk is 5 * 10
7Cm
-3Bulky micro defect (oxygen precipitation and secondary defect).
Claims (3)
1. germanium doping silicon wafer with internal impurity absorbing function, the oxygen concn of silicon chip is 5～15 * 10
17Cm
-3, germanium concentration is 1 * 10
13～1 * 10
20Cm
-3, it is characterized in that the clean area width is 10～100 μ m, bulky micro defect density is 1 * 10
5～1 * 10
10Cm
-3
2. the described preparation method with germanium doping silicon wafer of internal impurity absorbing function of claim 1 is characterized in that step is as follows, below each step all under argon gas or protection of nitrogen gas, carry out:
1) be 5～15 * 10 with oxygen concn
17Cm
-3, germanium concentration is 1 * 10
13～1 * 10
20Cm
-3The germanium-doped vertical-pulling silicon single crystal sheet, in rapid heat-treatment furnace 1100～1300 ℃ of insulations 5～100 seconds, then with 10～100 ℃/second rate of temperature fall with the silicon chip cool to room temperature;
2) will place the diffusion heat treatments stove through the silicon chip that step 1) is handled,, with 1～10 ℃ of/minute temperature rise rate silicon chip will be warmed up to 1000～1200 ℃ then 600～900 ℃ of insulations 4～50 hours;
3) will be through step 2) silicon chip handled places the diffusion heat treatments stove, 1000～1200 ℃ of insulations 4～30 hours, with 50～200 ℃ of/minute rate of temperature fall with the silicon chip cool to room temperature.
3. the described preparation method with germanium doping silicon wafer of internal impurity absorbing function of claim 1 is characterized in that step is as follows, below each step all under argon gas or protection of nitrogen gas, carry out:
1) be 5～15 * 10 with oxygen concn
17Cm
-3, germanium concentration is 1 * 10
13～1 * 10
20Cm
-3The germanium-doped vertical-pulling silicon single crystal sheet, in rapid heat-treatment furnace 1100～1300 ℃ of insulations 5～100 seconds, then with 10～100 ℃/second rate of temperature fall with the silicon chip cool to room temperature;
2) will place the diffusion heat treatments stove through the silicon chip that step 1) is handled, 1000～1200 ℃ the insulation 4～30 hours after, again with 50～200 ℃ of/minute rate of temperature fall with the silicon chip cool to room temperature.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104762656A (en) * | 2014-01-02 | 2015-07-08 | 浙江大学 | Intrinsic gettering technology of major diameter czochralski silicon chip |
| CN105706218A (en) * | 2013-10-31 | 2016-06-22 | 国立研究开发法人科学技术振兴机构 | Semiconductor-substrate manufacturing method and semiconductor-device manufacturing method in which germanium layer is heat-treated |
| CN106917143A (en) * | 2015-12-25 | 2017-07-04 | 有研半导体材料有限公司 | A kind of improvement silicon chip inside oxygen precipitation and the method for obtaining clean surface area |
| CN111201341A (en) * | 2016-06-08 | 2020-05-26 | 环球晶圆股份有限公司 | High resistivity single crystal silicon ingot and wafer with improved mechanical strength |
| CN111733455A (en) * | 2019-08-29 | 2020-10-02 | 浙江大学 | Monocrystalline silicon wafer containing germanium and nitrogen impurities, method for preparing same and integrated circuit comprising same |
-
2007
- 2007-07-30 CN CNA2007100704014A patent/CN101165224A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105706218A (en) * | 2013-10-31 | 2016-06-22 | 国立研究开发法人科学技术振兴机构 | Semiconductor-substrate manufacturing method and semiconductor-device manufacturing method in which germanium layer is heat-treated |
| CN105706218B (en) * | 2013-10-31 | 2018-09-25 | 国立研究开发法人科学技术振兴机构 | The manufacturing method for the semiconductor substrate that germanium layer is heat-treated and the manufacturing method of semiconductor device |
| CN104762656A (en) * | 2014-01-02 | 2015-07-08 | 浙江大学 | Intrinsic gettering technology of major diameter czochralski silicon chip |
| CN104762656B (en) * | 2014-01-02 | 2017-12-22 | 浙江大学 | A kind of systemic impurity process of major diameter Czochralski silicon wafer |
| CN106917143A (en) * | 2015-12-25 | 2017-07-04 | 有研半导体材料有限公司 | A kind of improvement silicon chip inside oxygen precipitation and the method for obtaining clean surface area |
| CN111201341A (en) * | 2016-06-08 | 2020-05-26 | 环球晶圆股份有限公司 | High resistivity single crystal silicon ingot and wafer with improved mechanical strength |
| US11142844B2 (en) | 2016-06-08 | 2021-10-12 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
| US11655560B2 (en) | 2016-06-08 | 2023-05-23 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
| US11655559B2 (en) | 2016-06-08 | 2023-05-23 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
| CN111733455A (en) * | 2019-08-29 | 2020-10-02 | 浙江大学 | Monocrystalline silicon wafer containing germanium and nitrogen impurities, method for preparing same and integrated circuit comprising same |
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