CN101162606A - Bit line pre-charging producer of dynamic ram - Google Patents
Bit line pre-charging producer of dynamic ram Download PDFInfo
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- CN101162606A CN101162606A CNA200610136152XA CN200610136152A CN101162606A CN 101162606 A CN101162606 A CN 101162606A CN A200610136152X A CNA200610136152X A CN A200610136152XA CN 200610136152 A CN200610136152 A CN 200610136152A CN 101162606 A CN101162606 A CN 101162606A
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Abstract
The invention provides a DRAM bit line pre-charge voltage generator, which comprises a first amplifier provided with a first current source and controlling a first PMOS transistor by comparing a first voltage with a pre-charge voltage, a second amplifier provided with a second current source and controlling a second PMOS transistor by comparing a second voltage with the pre-charge voltage, a third amplifier provided with a third current source and controlling a first NMOS transistor by comparing a third voltage with the pre-charge voltage and a fourth amplifier provided with a fourth current source and controlling a second NMOS transistor by comparing the first voltage with the pre-charge voltage. The pre-charge voltage provides feedbacks from output nodes connecting the second PMOS transistor and the first NMOS transistor.
Description
Technical field
The invention relates to a kind of dynamic RAM (DRAM) bit-line pre-charge and press generator, and more particular words it, be to press generator about a kind of DRAM bit-line pre-charge of the feedback of its output signal that uses.
Background technology
DRAM needs high stability bit-line pre-charge to press to satisfy long multiple new round-robin demand, and therefore, bit-line pre-charge presses generator must represent the feature of stable easily and low output impedance.Generally speaking, when the DRAM bit-line pre-charge pressed generator to apply pre-charge pressure to the bit line of semiconductor device, this pre-charge pressure had the value corresponding to half of supply voltage, (V
Cc-V
Ss)/2 (with reference to figure 1).
At United States Patent (USP) the 5th, 255, in No. 232 (hereinafter referred to as ' 232), disclose a kind of DRAM bit-line pre-charge and press generator.Fig. 1 shows the circuit diagram of the DRAM pre-charge pressure generator 1 in ' 232.Pre-charge pressure generator 1 comprises: first voltage divider 10, it is used to produce the first voltage division signal V
D1And the second voltage division signal V
D2And output circuit 12, it is used in response to this first voltage division signal V
D1And this second voltage division signal V
D2And generation pre-charge pressure V
Pre
This first voltage divider 10 comprises and is connected in supply-voltage source V
CcAnd the PMOS transistor M1 between the first node S1, be connected in the first nmos pass transistor M2 between first node S1 and the Section Point S2, be connected in the 2nd PMOS transistor M3 between Section Point S2 and the 3rd node S3, and be connected in the 3rd node S3 and ground voltage supplies V
SsBetween the second nmos pass transistor M4.The grid of the one PMOS transistor M1 is connected to ground voltage supplies V
Ss, and therefore a PMOS transistor M1 is used as the fixed resistance with fixed resistance value.Again, the grid of the second nmos pass transistor M4 is connected to supply-voltage source V
Cc, and therefore the second nmos pass transistor M4 is used as the fixed resistance with fixed resistance value.The big I of the one PMOS transistor M1 and the second nmos pass transistor M4 is determined the voltage at output node S4 place, and restriction is supplied voltage source V certainly via first voltage divider 10
CcFlow to ground voltage supplies V
SsElectric current.Therefore on the other hand, the grid of the first nmos pass transistor M2 is connected to its drain electrode, and the first nmos pass transistor M2 is as active resistance (active resistor), and the resistance value of this active resistance is with from supply-voltage source V
CcSupply voltage (that is, V
Cc-V
Ss) level increase and reduce.Therefore again, the grid of the 2nd PMOS transistor M3 is connected to its drain electrode, and the 2nd PMOS transistor M3 is as active resistance, and the resistance value of this active resistance is with from supply-voltage source V
CcSupply voltage level increase and increase.
The shortcoming of DRAM pre-charge pressure generator 1 is described below.The 3rd nmos pass transistor M5 can not disconnect fully, because the grid-source voltage that is applied thereto is near its threshold value voltage, and identical situation is suitable for the 3rd PMOS transistor M6.In addition, the size of the 3rd nmos pass transistor M5 and the 3rd PMOS transistor M6 should be enough greatly to provide enough electric current to pre-charge line.Therefore, big leakage current is supplied voltage source V certainly via output circuit 12
CcFlow to ground voltage supplies V
Ss
Fig. 2 is about the preliminary filling electric current at output node S4 place and the I-V graph of a relation of pre-charge pressure.Curve A is the I-V curve of desirable pre-charge pressure generator, wherein departs from the V of half when pre-charge pressure
CcDuring voltage, provide big preliminary filling electric current pre-charge pressure is recovered back the V of half
CcVoltage.That is curve A shows the preferable ability that pre-charge pressure departs from that suppresses.Yet curve B (the I-V curve of DRAM pre-charge pressure generator 1) shows until pre-charge pressure to be reached when departing from more greatly, and the pre-charge pressure that has departed from could recover.Therefore, the pre-charge pressure that is produced by DRAM pre-charge pressure generator 1 manifests bigger departing from.
As shown in Figure 3, United States Patent (USP) the 6th, 265, No. 858 (hereinafter referred to as ' 858) disclose a kind of voltage-regulating circuit of pressing generator as the DRAM bit-line pre-charge.This voltage-regulating circuit 2 comprises: generating circuit from reference voltage 20, comparator circuit 21 and output circuit 22.This generating circuit from reference voltage 20 comprises the first transistor QP10 and transistor seconds QP11, first resistance R 10 and second resistance R 12 and variable resistor R11.The first transistor QP10 and transistor seconds QP11 be equivalence substantially in size, and has diode PMOS type, and the resistance value of first resistance R 10 and second resistance R 12 is higher than the resistance value of variohm R11 substantially.First resistor R 10 and second resistor R 12 have the resistance of equivalence substantially.Comparator circuit 21 comprises the first differential amplifier DA1 and the second differential amplifier DA2.The first differential amplifier DA1 has the first node of being coupled to N10 and pre-charge pressure V
PreThe first input end and second input end.The first reference voltage V at the more anti-phase terminal of first differential amplifier DA1 place
Ref1Pre-charge pressure V with noninverting terminal place from first lead-out terminal 50
Pre, and produce the first control signal CS1.The second differential amplifier DA2 has the Section Point of being coupled to N11 and pre-charge pressure V
PreThe first input end and second input end.The second reference voltage V at the more anti-phase terminal of second differential amplifier DA2 place
Ref2Pre-charge pressure V with noninverting terminal place
Pre, and produce the second control signal CS2.Output circuit 22 comprises coupled in series in supply-voltage source V
CcWith ground voltage supplies V
SsBetween the 3rd transistor QP12 of PMOS type and the 4th transistor QN10 of NMOS type, and come controlling output circuit 22 according to the first control signal CS1 and the second control signal CS2.The grid of the 3rd transistor QP12 receives the second control signal CS2, and the grid of the 4th transistor QN10 receives the first control signal CS1.First electrode of the 3rd transistor QP12 and the 4th transistor QN10 is coupled to supply-voltage source V respectively
CcWith ground voltage supplies V
SsSecond electrode of the 3rd transistor QP12 and the 4th transistor QN10 is coupled to pre-charge pressure V jointly in the 3rd node N12 place
PreIn operation, the first reference voltage V
Ref1(V
Cc/ 2+ Δ V) is applied to V
Ref2(V
Cc/ 2-Δ V) first node N10, and second reference voltage is applied to Section Point N11.If pre-charge pressure V
PreLess than the first reference voltage V
Ref1And greater than the second reference voltage V
Ref2, then the 3rd transistor QP12 and the 4th transistor QN10 all are converted into " disconnection " state.Therefore, pre-charge pressure V
PreDo not change.If pre-charge pressure V
PreLess than the second reference voltage V
Ref2, then the 3rd transistor QP12 and the 4th transistor QN10 are converted into " connection " state and " disconnection " state respectively.Therefore, electric current flows to the 3rd node N12 via the 3rd transistor QP12, stably keeps pre-charge pressure V thus
PreLevel.Perhaps, as pre-charge pressure V
PreLevel greater than the first reference voltage V
Ref1The time, the first control signal CS1 and the second control signal CS2 are converted into high level.Therefore, electric current flows to ground voltage supplies V via the 4th transistor QN10
Ss, stably keep pre-charge pressure V thus
PreLevel.
Fig. 4 shows about the 3rd node N12 place about the preliminary filling electric current I
PreWith pre-charge pressure V
PreGraph of a relation.(dead zone) is present in V in the dead band
Ref2With V
Ref1Between, that is, as pre-charge pressure V
PreIn the time of in the dead band, leakage current (that is, I
Pre) the 3rd transistor QP12 and the 4th transistor QN10 flow through.Compare with the curve B of Fig. 2, the I-V curve of Fig. 4 is at pre-charge pressure V
PreDepart from half V
CcAnd steeper when leaving the dead band.Yet, instability problem can take place in voltage-regulating circuit 2.The circuit part that comprises the first differential amplifier DA1 and the 4th transistor QN10 forms the RC circuit equivalently, and this RC circuit provides a limit; Similarly, there are the second differential amplifier DA2 and the 3rd transistor QP12 to form another limit.In view of evolution of feedback controlling theory, two limits are included in the voltage-regulating circuit 2, and this voltage-regulating circuit 2 is with pre-charge pressure V
PreAs feedback signal, and must carefully design the position of two limits in the s plane to avoid pre-charge pressure V
PreVibration.
Fig. 5 is baud (Bode) gain diagram and the baud phase diagram of two kinds of feedback systems (stable and unstable).For stable feedback system, at gain crossover frequency W
GcThe place, its gain drop to below the 0dB, and phase place is more than negative 180 degree (relating to curve C and C ').Yet, for unstable feedback system, at gain crossover frequency W
Gc 'The place, its phase place its gain drop to below the 0dB before drop to below negative 180 degree (relating to curve D and D ').
Generally speaking, for high density DRAM (for example, the capacity that 128Mb is above), the MOS transistor of output circuit 22 that is used for voltage-regulating circuit 2 is enough greatly to drive bit line.That is the equivalent capacity of MOS transistor is also enough big, and therefore, and the limit that is provided by big electric capacity will be arranged in the low-frequency region place of frequency spectrum.The low-frequency pole of being introduced will make the baud gain diagram of feedback system begin landing in stability at lower frequencies, and form than low gain crossover frequency (with reference to figure 5), and wherein feedback system becomes stable.Therefore, for the voltage-regulating circuit that is used for high density DRAM, there is not stable problem.Yet for low-density DRAM (for example, the capacity that 16Mb is following), process technique produces the pattern of some failures that cause the leakage current in the bit line at present.In order to compensate the leakage current among the low-density DRAM, be used in MOS transistor in the voltage-regulating circuit 2 must be designed to have high driving force (that is, big size), the little equivalent RC value that the high frequency poles of providing perhaps is provided, however so the MOS transistor of design will be easy to cause voltage-regulating circuit 2 instabilities.
Summary of the invention
One aspect of the present invention provides a kind of DRAM bit-line pre-charge to press generator, and it as feedback signal, reaches low stability problem with the big leakage current of eliminating in the prior art with its output signal.
The present invention provides a kind of DRAM bit-line pre-charge to press generator on the other hand, and it has the low-frequency pole that provided by two amplifiers to show the feature of robustness, low standby current and low output impedance.
The DRAM bit-line pre-charge of first embodiment of the invention presses generator to comprise: have first amplifier of first current source, second amplifier with second current source, the 3rd amplifier with the 3rd current source, the 4th amplifier with the 4th current source, a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, reach second nmos pass transistor.This first amplifier comparison, first voltage and pre-charge pressure are to control a PMOS transistor.This second amplifier comparison, second voltage and this pre-charge pressure are to control the 2nd PMOS transistor.The 3rd amplifier comparison tertiary voltage and this pre-charge pressure are to control this first nmos pass transistor.The 4th amplifier relatively this first voltage and this pre-charge pressure to control this second nmos pass transistor.The one PMOS transistor is coupled to supply-voltage source via its drain electrode.The 2nd PMOS transistor is coupled to the transistorized source electrode of a PMOS via its drain electrode.This first nmos pass transistor is coupled to the transistorized source electrode of the 2nd PMOS via its drain electrode.This second nmos pass transistor is coupled to the source electrode of this first nmos pass transistor via its drain electrode, and is coupled to ground voltage supplies.This pre-charge pressure is to obtain from being connected in the output node between this first nmos pass transistor of the 2nd PMOS transistor AND gate.Each amplifier and corresponding transistor thereof show and have RC value equivalent RC (resistance-capacitance) circuit of (that is, its resistance and electric capacity amass).Have this first amplifier of big RC value and the low-frequency pole in corresponding transistor and the 4th amplifier and the corresponding transistor introducing s plane thereof thereof, to reach the feature of robustness, low standby current and low output impedance.
The DRAM bit-line pre-charge of second embodiment of the invention presses generator to comprise: have first amplifier of first current source, second amplifier with second current source, the 3rd amplifier with the 3rd current source, the 4th amplifier with the 4th current source, a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor, reach voltage divider.This first amplifier comparison, first pre-charge pressure and reference voltage are to control a PMOS transistor.This second amplifier comparison, second pre-charge pressure and this reference voltage are to control the 2nd PMOS transistor.The 3rd amplifier comparison pre-charge pressure and this reference voltage are to control first nmos pass transistor.The 4th amplifier relatively this first pre-charge pressure and this reference voltage to control this second nmos pass transistor.The one PMOS transistor is coupled to supply-voltage source via its drain electrode.The 2nd PMOS transistor is coupled to the transistorized source electrode of a PMOS via its drain electrode.This first nmos pass transistor is coupled to the transistorized source electrode of the 2nd PMOS via its drain electrode.This second nmos pass transistor is coupled to the source electrode of this first nmos pass transistor via its drain electrode, and is coupled to ground voltage supplies.This pre-charge pressure is to obtain from being connected in the output node between this first nmos pass transistor of the 2nd PMOS transistor AND gate.Have this first amplifier of big RC value and the low-frequency pole in corresponding transistor and the 4th amplifier and the corresponding transistor introducing s plane thereof thereof.This voltage divider is used for producing first pre-charge pressure and second pre-charge pressure according to supply-voltage source and pre-charge pressure, and determines the lower boundary of this pre-charge pressure.In this embodiment, reference voltage is the coboundary of pre-charge pressure.
The DRAM bit-line pre-charge of third embodiment of the invention presses generator to comprise: have first amplifier of first current source, second amplifier with second current source, the 3rd amplifier with the 3rd current source, the 4th amplifier with the 4th current source, a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor, reach voltage divider.This first amplifier comparison, first pre-charge pressure and reference voltage are to control a PMOS transistor.This second amplifier comparison pre-charge pressure and this reference voltage are to control the 2nd PMOS transistor.The 3rd amplifier comparison second pre-charge pressure and this reference voltage are to control first nmos pass transistor.The 4th amplifier relatively this first pre-charge pressure and this reference voltage to control this second nmos pass transistor.The one PMOS transistor is coupled to supply-voltage source via its drain electrode.The 2nd PMOS transistor is coupled to the transistorized source electrode of a PMOS via its drain electrode.This first nmos pass transistor is coupled to the transistorized source electrode of the 2nd PMOS via its drain electrode.This second nmos pass transistor is coupled to the source electrode of this first nmos pass transistor via its drain electrode, and is coupled to ground voltage supplies.This pre-charge pressure is to obtain from being connected in the output node between this first nmos pass transistor of the 2nd PMOS transistor AND gate.Have this first amplifier of big RC value and the low-frequency pole in corresponding transistor and the 4th amplifier and the corresponding transistor introducing s plane thereof thereof.This voltage divider is used for producing first pre-charge pressure and second pre-charge pressure according to ground voltage supplies and pre-charge pressure, and determines the coboundary of this pre-charge pressure.In this embodiment, reference voltage is the lower boundary of pre-charge pressure.
In above-mentioned three embodiment, the equivalent resistance of each amplifier can change by the electric current of adjusting the corresponding current source, and each transistorized equivalent capacity can be adjusted by changing the corresponding transistor size.
Description of drawings
Fig. 1 is that a known DRAM bit-line pre-charge is pressed generator;
Fig. 2 is the preliminary filling electric current relevant with Fig. 1 and the I-V graph of a relation of pre-charge pressure;
Fig. 3 is that another known DRAM bit-line pre-charge is pressed generator;
Fig. 4 is the preliminary filling electric current relevant with Fig. 3 and the I-V graph of a relation of pre-charge pressure;
Fig. 5 is the baud gain diagram and the baud phase diagram of two kinds of feedback systems;
Fig. 6 presses generator according to the DRAM bit-line pre-charge of the first embodiment of the present invention;
Fig. 7 is a DRAM bit-line pre-charge pressure generator according to a second embodiment of the present invention; And
Fig. 8 is that the DRAM bit-line pre-charge of a third embodiment in accordance with the invention is pressed generator.
[main element label declaration]
1 DRAM pre-charge pressure generator, 2 voltage-regulating circuits
3 DRAM bit-line pre-charges are pressed generator
4 DRAM bit-line pre-charges are pressed generator
5 DRAM bit-line pre-charges are pressed generator
10 first voltage dividers, 12 output circuits
20 generating circuit from reference voltage, 21 comparator circuits
22 output circuits, 40 voltage dividers
50 voltage divider CS1, first control signal
The CS2 second control signal DA1 first differential amplifier
The DA2 second differential amplifier I
1First current source
I
2The second current source I
3The 3rd current source
I
4The 4th current source I
PreThe preliminary filling electric current
M1 the one PMOS transistor M2 first nmos pass transistor
M3 the 2nd PMOS transistor M4 second nmos pass transistor
N10 first node N11 Section Point
N12 the 3rd node OP1 first amplifier
The OP2 second amplifier OP3 the 3rd amplifier
OP4 the 4th amplifier Q1 the one PMOS transistor
Q2 the 2nd PMOS transistor Q3 first nmos pass transistor
The Q4 second nmos pass transistor QN10 the 4th transistor
QP10 the first transistor QP11 transistor seconds
QP12 the 3rd transistor R1 first resistor
R10 first resistor R 11 variohms
R12 second resistor R 2 second resistors
R3 the 3rd resistor S1 first node
S2 Section Point S3 the 3rd node
V
1The first voltage V
2Second voltage
V
3Tertiary voltage V
4The 4th voltage
V
CcSupply-voltage source V
D1First voltage division signal
V
D2The second voltage division signal V
PrePre-charge pressure
V
Pre1The first pre-charge pressure V
Pre2Second pre-charge pressure
V
RefWith reference to electric V
Ref1First reference voltage
V
Ref2The second reference voltage V
SsGround voltage supplies
Embodiment
Fig. 6 presses generator 3 according to the DRAM bit-line pre-charge of the first embodiment of the present invention.The DRAM bit-line pre-charge presses generator 3 to comprise: have the first current source I
1The first amplifier OP1, have the second current source I
2The second amplifier OP2, have the 3rd current source I
3The 3rd amplifier OP3, have the 4th current source I
4The 4th amplifier OP4, a PMOS transistor Q1, the 2nd PMOS transistor Q2, the first nmos pass transistor Q3, and the second nmos pass transistor Q4.The one PMOS transistor Q1 is coupled to supply-voltage source V via its drain electrode
Cc, and be coupled to the output terminal of the first amplifier OP1 via its grid.The 2nd PMOS transistor Q2 is coupled to the source electrode of a PMOS transistor Q1 via its drain electrode, and is coupled to the output terminal of the second amplifier OP2 via its grid.The first nmos pass transistor Q3 is coupled to the source electrode of the 2nd PMOS transistor Q2 via its drain electrode, and is coupled to the output terminal of the 3rd amplifier OP3 via its grid.The second nmos pass transistor Q4 is coupled to the source electrode of the first nmos pass transistor Q3 via its drain electrode, is coupled to the output terminal of the 4th amplifier OP4 via its grid, and is coupled to ground voltage supplies V
SsThe first amplifier OP1 is the first voltage V relatively
1With pre-charge pressure V
PreTo control a PMOS transistor Q1.V
PreBe to obtain from being connected to the output node N1 between the 2nd PMOS transistor Q2 and the first nmos pass transistor Q3.The second amplifier OP2 is the second voltage V relatively
2With pre-charge pressure V
PreTo control the 2nd PMOS transistor Q2.The 3rd amplifier OP3 is tertiary voltage V relatively
3With pre-charge pressure V
PreTo control the first nmos pass transistor Q3.The 4th amplifier OP4 is the first voltage V relatively
1With pre-charge pressure V
PreTo control the second nmos pass transistor Q4.
Amplifier and transistor can be regarded as equivalent resistance and equivalent capacity respectively.Therefore, the first amplifier OP1 and a PMOS transistor Q1 provide a RC value, the second amplifier OP2 and the 2nd PMOS transistor Q2 provide the 2nd RC value, the 3rd amplifier OP3 and the first nmos pass transistor Q3 provide the 3rd RC value, and the 4th amplifier OP4 and the second nmos pass transistor Q4 provide the 4th RC value.The RC value is equivalent to the long-pending of resistance and electric capacity.The one RC value is greater than the 2nd RC value, and the 4th RC value is greater than the 3rd RC value.The first voltage V
1, the second voltage V
2And tertiary voltage V
3The reference voltage that provides for the outside.Tertiary voltage V
3And the second voltage V
2Be respectively pre-charge pressure V
PreCoboundary and lower boundary.According to the circuit shown in Fig. 6, can provide tertiary voltage V from first node N10 and Section Point N11 respectively
3And the second voltage V
2(with reference to figure 3).The first voltage V
1Between the second voltage V
2With tertiary voltage V
3Between.That is, there is V
3＞V
1＞V
2Relation.Preferably, the first voltage V
1Be the second voltage V
2With tertiary voltage V
3Average, that is, (V
2+ V
3)/2.
Higher RC value is corresponding to than low-frequency pole.Therefore, be lower than gain crossover frequency W by interpolation
Gc 'The low-frequency pole of (with reference to figure 5), the unsettled feedback system of Fig. 5 become gain and drop to systems stabilisation below the 0dB before its phase place drop to negative 180 degree.Compare with comparator circuit 21 and the output circuit 22 of Fig. 3, the DRAM bit-line pre-charge of the first embodiment of the present invention presses generator 3 further to comprise two amplifier OP1, OP4 and two transistor Q1, Q4, to introduce low-frequency pole.In order to introduce low-frequency pole, the size of a PMOS transistor Q1 and the second nmos pass transistor Q4 is respectively greater than the size of the 2nd PMOS transistor Q2 and the first nmos pass transistor Q3.Preferably, the size of a PMOS transistor Q1 and the second nmos pass transistor Q4 is respectively at least 10 times of size of the 2nd PMOS transistor Q2 and the first nmos pass transistor Q3.
The another way of introducing low-frequency pole is: design the second current source I
2And the 3rd current source I
3Electric current respectively greater than the first current source I
1And the 4th current source I
4Electric current.In order to simplify circuit, can be respectively with the second current source I
2And the first current source I
1Substitute the 3rd current source I
3And the 4th current source I
4, the second current source I wherein
2Electric current keep greater than the first current source I
1Electric current.
The principle of operation of the first embodiment of the present invention below is described.With reference to figure 6, because V as mentioned above
2＜V
1＜V
3So, if pre-charge pressure V
PreLess than the second voltage V
2, pre-charge pressure V then
PreAlso will be less than the first voltage V
1And tertiary voltage V
3, that is, V
Pre＜V
1And V
Pre＜V
3Therefore a PMOS transistor Q1 and the 2nd PMOS transistor Q2 connect, yet the first nmos pass transistor Q3 and the second nmos pass transistor Q4 disconnect.Therefore, pre-charge pressure V
PreLevel increase.
If pre-charge pressure V
PreGreater than tertiary voltage V
3, pre-charge pressure V then
PreWill be greater than the first voltage V
1And the second voltage V
2, that is, V
Pre＞V
1And V
Pre＞V
2Therefore, a PMOS transistor Q1 and the 2nd PMOS transistor Q2 disconnect, yet the first nmos pass transistor Q3 and the second nmos pass transistor Q4 connect.Therefore, pre-charge pressure V
PreReduce.
As pre-charge pressure V
PreBetween tertiary voltage V
3With the second voltage V
2Between the time, the 2nd PMOS transistor Q2 and the first nmos pass transistor Q3 disconnect, therefore, pre-charge pressure V
PreRemain unchanged, and obtain the low electric current of keeping.
Fig. 7 is a DRAM pre-charge pressure generator 4 according to a second embodiment of the present invention.Except the input signal that has added voltage divider 40 and four amplifier OP1-OP4, the circuit of Fig. 7 is similar to the circuit of Fig. 6 in fact.The DRAM bit-line pre-charge presses generator 4 to comprise: have the first current source I
1The first amplifier OP1, have the second current source I
2The second amplifier OP2, have the 3rd current source I
3The 3rd amplifier OP3, have the 4th current source I
4The 4th amplifier OP4, a PMOS transistor Q1, the 2nd PMOS transistor Q2, the first nmos pass transistor Q3, the second nmos pass transistor Q4, and voltage divider 40.The first amplifier OP1 is the first pre-charge pressure V relatively
Pre1With reference voltage V
RefTo control a PMOS transistor Q1.The second amplifier OP2 is the second pre-charge pressure V relatively
Pre2With reference voltage V
PreTo control the 2nd PMOS transistor Q2.The 3rd amplifier OP3 is pre-charge pressure V relatively
PreWith reference voltage V
RefTo control the first nmos pass transistor Q3.The 4th amplifier OP4 is the first pre-charge pressure V relatively
Pre1With reference voltage V
RefTo control the second nmos pass transistor Q4.The current source I of Fig. 7
1-I
4Between relation and the current source I of Fig. 6
1-I
4Between relation identical.In addition, the physics magnitude relationship between the transistor Q1-Q4 of the physics magnitude relationship between the transistor Q1-Q4 of Fig. 7 and Fig. 6 is identical.In this embodiment, only externally provide reference voltage V
Ref, and the first pre-charge pressure V
Pre1And the second pre-charge pressure V
Pre2Be according to supply-voltage source V
CcAnd pre-charge pressure V
PreAnd produce from voltage divider 40.Voltage divider 40 comprises first resistor R 1, second resistor R 2 and the 3rd resistor R 3, and these resistor in series connect.The first pre-charge pressure V
Pre1Be to obtain from being connected in the node between first resistor R 1 and second resistor R 2.The second pre-charge pressure V
Pre2Be to obtain from being connected in the node between second resistor R 2 and the 3rd resistor R 3.In this embodiment, voltage divider 40 also is used for determining pre-charge pressure V
PreLower boundary, and reference voltage V
RefBe pre-charge pressure V
PreThe coboundary.Pre-charge pressure V
PreLower boundary equal reference voltage V
RefDeduct the voltage difference of crossing over first resistor R 1 and second resistor R 2.That is, pre-charge pressure V
PreLower boundary through being defined as V
L=V
Ref-Δ V, wherein Δ V=[(R1+R2)/(R1+R2+R3) * (V
Cc-V
Pre)].
The principle of operation of the second embodiment of the present invention then is described.With reference to figure 7, if pre-charge pressure V
PreLess than pre-charge pressure V
PreLower boundary (that is, V
L), hinting V
Pre1＜V
RefAnd V
Pre2＜V
Ref, a PMOS transistor Q1 and the 2nd PMOS transistor Q2 connect, however the first nmos pass transistor Q3 and the second nmos pass transistor Q4 disconnect.Therefore, pre-charge pressure V
PreLevel increase.If pre-charge pressure V
PreGreater than reference voltage V
Ref, imply V
Pre1＞V
RefAnd V
Pre2＞V
Pre, a PMOS transistor Q1 and the 2nd PMOS transistor Q2 disconnect, however the first nmos pass transistor Q3 and the second nmos pass transistor Q4 connect.Therefore, pre-charge pressure V
PreReduce.As charging voltage V
PreBetween reference voltage V
RefWith pre-charge pressure V
PreLower boundary (that is, V
L) between the time, the 2nd PMOS transistor Q2 and the first nmos pass transistor Q3 disconnect, therefore, pre-charge pressure V
PreRemain unchanged, and obtain the low electric current of keeping.
Fig. 8 is that the DRAM bit-line pre-charge of a third embodiment in accordance with the invention is pressed generator 5.Except the input signal that rearranges voltage divider 50 and four amplifier OP1-OP4, the circuit of Fig. 8 is similar to the circuit of Fig. 7 in fact.The DRAM bit-line pre-charge presses generator 5 to comprise: have the first current source I
1The first amplifier OP1, have the second current source I
2The second amplifier OP2, have the 3rd current source I
3The 3rd amplifier OP3, have the 4th current source I
4The 4th amplifier OP4, a PMOS transistor Q1, the 2nd PMOS transistor Q2, the first nmos pass transistor Q3, the second nmos pass transistor Q4, and voltage divider 50.The first amplifier OP1 is the first pre-charge pressure V relatively
Pre1With reference voltage V
RefTo control a PMOS transistor Q1.The second amplifier OP2 is pre-charge pressure V relatively
PreWith reference voltage V
RefTo control the 2nd PMOS transistor Q2.The 3rd amplifier OP3 is the second pre-charge pressure V relatively
Pre2With reference voltage V
RefTo control the first nmos pass transistor Q3.The 4th amplifier OP4 is the first pre-charge pressure V relatively
Pre1With reference voltage V
RefTo control the second nmos pass transistor Q4.The current source I of Fig. 8
1-I
4Between relation and the current source I of Fig. 7
1-I
4Between relation identical.In addition, the physics magnitude relationship between the transistor Q1-Q4 of the physics magnitude relationship between the transistor Q1-Q4 of Fig. 8 and Fig. 7 is identical.In this embodiment, only externally provide reference voltage V
Ref, and the first pre-charge pressure V
Pre1And the second pre-charge pressure V
Pre2Be according to ground voltage supplies V
SsAnd pre-charge pressure V
PreAnd produce from voltage divider 50.Voltage divider 50 comprises first resistor R 1, second resistor R 2 and the 3rd resistor R 3, and these resistor in series connect.The first pre-charge pressure V
Pre1Be to obtain from being connected in the node between first resistor R 1 and second resistor R 2.The second pre-charge pressure V
Pre2Be to obtain from being connected in the node between second resistor R 2 and the 3rd resistor R 3.In this embodiment, voltage divider 50 also is used for determining pre-charge pressure V
PreThe coboundary, and reference voltage V
RefBe pre-charge pressure V
PreLower boundary.Pre-charge pressure V
PreThe coboundary equal reference voltage V
RefAdd the voltage difference of crossing over first resistor R 1 and second resistor R 2.That is, pre-charge pressure V
PreThe coboundary through being defined as V
U=V
Ref+ Δ V, wherein Δ V=[(R1+R2)/(R1+R2+R3) * (V
Pre-V
Ss)].
The principle of operation of the third embodiment of the present invention below is described.Referring to Fig. 8, if pre-charge pressure V
PreLess than pre-charge pressure V
PreLower boundary (that is, V
Ref), hinting V
Pre1＜V
RefAnd V
Pre2＜V
Ref, a PMOS transistor Q1 and the 2nd PMOS transistor Q2 connect, however the first nmos pass transistor Q3 and the second nmos pass transistor Q4 disconnect.Therefore, pre-charge pressure V
PreLevel increase.If pre-charge pressure V
PreGreater than pre-charge pressure V
PreThe coboundary (that is, V
U), hinting V
Pre1＞V
RefAnd V
Pre2＞V
Ref, a PMOS transistor Q1 and the 2nd PMOS transistor Q2 disconnect, however the first nmos pass transistor Q3 and the second nmos pass transistor Q4 connect.Therefore, pre-charge pressure V
PreReduce.As charging voltage V
PreBetween reference voltage V
RefWith pre-charge pressure V
PreThe coboundary (that is, V
U) between the time, the 2nd PMOS transistor Q2 and the first nmos pass transistor Q3 disconnect, therefore, pre-charge pressure V
PreRemain unchanged, and obtain the low electric current of keeping.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to those disclosed embodiments, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by appended claim scope.
Claims (20)
1. a DRAM bit-line pre-charge is pressed generator, and it comprises:
First amplifier, its comparison first voltage and pre-charge pressure are coupled to a PMOS transistor of supply-voltage source with control;
Second amplifier, it compares second voltage and this pre-charge pressure is coupled to transistorized the 2nd PMOS transistor of a PMOS with control;
The 3rd amplifier, it compares tertiary voltage and this pre-charge pressure is coupled to transistorized first nmos pass transistor of the 2nd PMOS with control; And
The 4th amplifier, its comparison first voltage and this pre-charge pressure are coupled to second nmos pass transistor of this first nmos pass transistor and ground voltage supplies with control;
Wherein, this pre-charge pressure is to be obtained from the output node that is connected between this first nmos pass transistor of the 2nd PMOS transistor AND gate.
2. DRAM bit-line pre-charge according to claim 1 is pressed generator, and wherein each of this first amplifier, this second amplifier, the 3rd amplifier and the 4th amplifier has first current source, second current source, the 3rd current source and the 4th current source respectively.
3. DRAM bit-line pre-charge according to claim 1 is pressed generator, and wherein this tertiary voltage and this second voltage are respectively the coboundary and the lower boundary of this pre-charge pressure.
4. DRAM bit-line pre-charge according to claim 2 is pressed generator, and wherein the electric current of this second current source and the 3rd current source is respectively greater than the electric current of this first current source and the 4th current source.
5. DRAM bit-line pre-charge according to claim 4 is pressed generator, and wherein the electric current of this first current source and this second current source equals the electric current of the 4th current source and the 3rd current source respectively.
6. DRAM bit-line pre-charge according to claim 1 is pressed generator, and wherein this first voltage is between this second voltage and this tertiary voltage.
7. a DRAM bit-line pre-charge is pressed generator, and it comprises:
First amplifier, its comparison reference voltage and first pre-charge pressure are coupled to a PMOS transistor of supply-voltage source with control;
Second amplifier, relatively this reference voltage and second pre-charge pressure are coupled to transistorized the 2nd PMOS transistor of a PMOS with control for they;
The 3rd amplifier, relatively this reference voltage and pre-charge pressure are coupled to transistorized first nmos pass transistor of the 2nd PMOS with control for they;
The 4th amplifier, relatively this reference voltage and this first pre-charge pressure are coupled to second nmos pass transistor of this first nmos pass transistor and ground voltage supplies with control for they; And
Voltage divider, it produces this first pre-charge pressure and this second pre-charge pressure according to this supply-voltage source and this pre-charge pressure;
Wherein, this pre-charge pressure is to be obtained from the output node that is connected between this first nmos pass transistor of the 2nd PMOS transistor AND gate.
8. DRAM bit-line pre-charge according to claim 7 is pressed generator, and wherein each of this first amplifier, this second amplifier, the 3rd amplifier and the 4th amplifier has first current source, second current source, the 3rd current source and the 4th current source respectively.
9. DRAM bit-line pre-charge according to claim 7 is pressed generator, and wherein this reference voltage is the coboundary of this pre-charge pressure, and this voltage divider is determined the lower boundary of this pre-charge pressure.
10. DRAM bit-line pre-charge according to claim 7 is pressed generator, and wherein this voltage divider comprises first resistance, second resistance and the 3rd resistance, and this constant resistance is to be connected in series.
11. DRAM bit-line pre-charge according to claim 10 is pressed generator, wherein this first pre-charge pressure is to be obtained from the node that is connected between this first resistance and this second resistance, and this second pre-charge pressure is to be obtained from the node that is connected between this second resistance and the 3rd resistance.
12. DRAM bit-line pre-charge according to claim 10 is pressed generator, wherein the lower boundary of this pre-charge pressure equals the voltage difference that this reference voltage deducts this first resistance of leap and this second resistance.
13. DRAM bit-line pre-charge according to claim 8 is pressed generator, wherein the electric current of this second current source and the 3rd current source is respectively greater than the electric current of this first current source and the 4th current source.
14. a DRAM bit-line pre-charge is pressed generator, it comprises
First amplifier, its comparison reference voltage and first pre-charge pressure are coupled to a PMOS transistor of supply-voltage source with control;
Second amplifier, relatively this reference voltage and pre-charge pressure are coupled to transistorized the 2nd PMOS transistor of a PMOS with control for they;
The 3rd amplifier, relatively this reference voltage and second pre-charge pressure are coupled to transistorized first nmos pass transistor of the 2nd PMOS with control for they;
The 4th amplifier, relatively this reference voltage and this first pre-charge pressure are coupled to second nmos pass transistor of this first nmos pass transistor and ground voltage supplies with control for they; And
Voltage divider, it produces this first pre-charge pressure and this second pre-charge pressure according to this ground voltage supplies and this pre-charge pressure;
Wherein, this pre-charge pressure is to be obtained from the output node that is connected between this first nmos pass transistor of the 2nd PMOS transistor AND gate.
15. DRAM bit-line pre-charge according to claim 14 is pressed generator, wherein each of this first amplifier, this second amplifier, the 3rd amplifier and the 4th amplifier has first current source, second current source, the 3rd current source and the 4th current source respectively.
16. DRAM bit-line pre-charge according to claim 14 is pressed generator, wherein this reference voltage is the lower boundary of this pre-charge pressure, and this voltage divider is determined the coboundary of this pre-charge pressure.
17. DRAM bit-line pre-charge according to claim 14 is pressed generator, wherein this voltage divider comprises first resistance, second resistance and the 3rd resistance, and this constant resistance is to be connected in series.
18. DRAM bit-line pre-charge according to claim 17 is pressed generator, wherein this first pre-charge pressure is to be obtained from the node that is connected between this first resistor and this second resistor, and this second pre-charge pressure is to be obtained from the node that is connected between this second resistor and the 3rd resistor.
19. DRAM bit-line pre-charge according to claim 17 is pressed generator, wherein the coboundary of this pre-charge pressure equals the voltage difference that this reference voltage adds this first resistance of leap and this second resistance.
20. DRAM bit-line pre-charge according to claim 15 is pressed generator, wherein the electric current of this second current source and the 3rd current source is respectively greater than the electric current of this first current source and the 4th current source.
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| CNB200610136152XA CN100573711C (en) | 2006-10-13 | 2006-10-13 | The bit-line pre-charge of dynamic RAM is pressed generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610136152XA CN100573711C (en) | 2006-10-13 | 2006-10-13 | The bit-line pre-charge of dynamic RAM is pressed generator |
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| CN101162606A true CN101162606A (en) | 2008-04-16 |
| CN100573711C CN100573711C (en) | 2009-12-23 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157193A (en) * | 2011-03-28 | 2011-08-17 | 钰创科技股份有限公司 | Voltage adjuster of memory |
| CN103226538A (en) * | 2013-05-14 | 2013-07-31 | 苏州文芯微电子科技有限公司 | Impedance matching circuit based on high-speed serial communication bus actuator |
| CN110890119A (en) * | 2018-09-07 | 2020-03-17 | 三星电子株式会社 | Voltage generation circuit, memory device and method for generating bit line precharge voltage |
| WO2023178829A1 (en) * | 2022-03-23 | 2023-09-28 | 长鑫存储技术有限公司 | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
| US11798617B2 (en) | 2022-03-23 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
| US11869609B2 (en) | 2022-03-23 | 2024-01-09 | Changxin Memory Technologies, Inc. | Method and apparatus for testing memory, medium and device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2840068B2 (en) * | 1997-12-08 | 1998-12-24 | 株式会社日立超エル・エス・アイ・システムズ | Dynamic RAM |
| KR100336751B1 (en) * | 1999-07-28 | 2002-05-13 | 박종섭 | Voltage regulating circuit |
| CN1184644C (en) * | 2001-03-16 | 2005-01-12 | 矽统科技股份有限公司 | Memory updating system |
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2006
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157193A (en) * | 2011-03-28 | 2011-08-17 | 钰创科技股份有限公司 | Voltage adjuster of memory |
| CN103226538A (en) * | 2013-05-14 | 2013-07-31 | 苏州文芯微电子科技有限公司 | Impedance matching circuit based on high-speed serial communication bus actuator |
| CN110890119A (en) * | 2018-09-07 | 2020-03-17 | 三星电子株式会社 | Voltage generation circuit, memory device and method for generating bit line precharge voltage |
| CN110890119B (en) * | 2018-09-07 | 2023-09-19 | 三星电子株式会社 | Voltage generating circuit, memory device and method for generating bit line precharge voltage |
| WO2023178829A1 (en) * | 2022-03-23 | 2023-09-28 | 长鑫存储技术有限公司 | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
| US11798617B2 (en) | 2022-03-23 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
| US11869609B2 (en) | 2022-03-23 | 2024-01-09 | Changxin Memory Technologies, Inc. | Method and apparatus for testing memory, medium and device |
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| Publication number | Publication date |
|---|---|
| CN100573711C (en) | 2009-12-23 |
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