CN103226538A - Impedance matching circuit based on high-speed serial communication bus actuator - Google Patents
Impedance matching circuit based on high-speed serial communication bus actuator Download PDFInfo
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- CN103226538A CN103226538A CN2013101761772A CN201310176177A CN103226538A CN 103226538 A CN103226538 A CN 103226538A CN 2013101761772 A CN2013101761772 A CN 2013101761772A CN 201310176177 A CN201310176177 A CN 201310176177A CN 103226538 A CN103226538 A CN 103226538A
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Abstract
The invention discloses an impedance matching circuit based on a high-speed serial communication bus actuator. The impedance matching circuit comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a first current source circuit, a second current source circuit and a third current source circuit, wherein the first operational amplifier is electrically connected with the first current source circuit; the third operational amplifier is electrically connected with the third current source circuit, and the first operational amplifier is electrically connected with the third operational amplifier through the second current source circuit; and the second operational amplifier is electrically connected with a bus driving circuit of the bus actuator. The impedance matching circuit provided by the invention has the advantages that a negative feedback loop is additionally arranged on the basic of the existing impedance matching circuit, upper and lower output impedances are respectively matched with the impedance of a transmission line, and the integrity of a signal is well guaranteed.
Description
Technical field
The present invention relates to the CMOS(complementary metal oxide semiconductor (CMOS)) the integrated circuit (IC) design field, particularly relate to a kind of impedance matching circuit based on the high speed serial communication bus driver.
Background technology
In the high speed serial communication field, H configuration bus activation configuration is a kind of differential bus drives structure commonly used.In order to make that high speed signal can normal transmission, need make the impedance matching of equivalent output impedance and transmission line of bus driver.In present H structure difference High Speed Driver (high-speed bus driver), its impedance matching circuit can only be realized the coupling of differential impedance, and can not accomplish the coupling of single-ended impedance.Because the single-ended output impedance separately and the single-ended impedance of transmission line do not match up and down, cause the signal transmission to produce distortion.
Summary of the invention
The technical matters that the present invention mainly solves provides a kind of impedance matching circuit based on the high speed serial communication bus driver, solved that the single-ended impedance of single-ended output impedance and transmission line does not match in the existing impedance matching circuit, caused the signal transmission to produce the defective of distortion easily.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of impedance matching circuit based on the high speed serial communication bus driver is provided, comprise first operational amplifier, second operational amplifier, the 3rd operational amplifier, first source lines, second source lines and the 3rd source lines, described first operational amplifier and first source lines electrically connect, described the 3rd operational amplifier and the 3rd source lines electrically connect, described first operational amplifier electrically connects by second source lines and the 3rd operational amplifier, wherein, the bus driving circuits of described second operational amplifier and bus driver electrically connects.
In a preferred embodiment of the present invention, described first source lines, second source lines and the 3rd source lines are for being connected in parallel.
In a preferred embodiment of the present invention, described first source lines comprises the 5th MOS device of series connection setting successively and one 150 ohm resistance.
In a preferred embodiment of the present invention, described second source lines comprises two 100 ohm the resistance that series connection successively is provided with.
In a preferred embodiment of the present invention, described the 3rd source lines comprises the 6th MOS device of series connection setting successively, one 150 ohm resistance and the 7th MOS device.
In a preferred embodiment of the present invention, electric current on described first source lines, second source lines and the 3rd source lines equates, the resistance of described the 5th MOS device is 50 ohm, and the resistance sum of described the 6th MOS device and the 7th MOS device is 50 ohm.
In a preferred embodiment of the present invention, described bus driving circuits comprises the 4th source lines, the 5th source lines and the 6th source lines, described the 4th source lines comprises the MOS device that series connection successively is provided with, the 2nd MOS device and the 8th MOS device, the 3rd MOS device that described the 5th source lines is connected successively and is provided with, the 4th MOS device and the 9th MOS device, described the 6th source lines comprises one 100 ohm resistance, and described the 4th source lines is connected in parallel by the 6th source lines and the 5th source lines.
In a preferred embodiment of the present invention, described the 6th source lines is connected the lower end of the 2nd MOS device and the lower end of the 3rd MOS device.
In a preferred embodiment of the present invention, a described MOS device and the 2nd MOS device electrically connect with four-operational amplifier and the 5th operational amplifier respectively.
In a preferred embodiment of the present invention, described the 3rd MOS device and the 4th MOS device electrically connect with the 6th operational amplifier and the 7th operational amplifier respectively.
The invention has the beneficial effects as follows: the impedance matching circuit based on the high speed serial communication bus driver of the present invention, on the basis of existing impedance matching circuit, increased a feedback loop, make output impedance up and down all can with the impedance matching of transmission line, thereby make the integrality of signal can access better assurance.
Description of drawings
Fig. 1 is existing bus driving circuits figure;
Fig. 2 is the impedance matching circuit figure of Fig. 1;
Fig. 3 is the circuit diagram that existing impedance matching circuit adds bus driving circuits;
Fig. 4 is the impedance matching circuit figure that the present invention is based on the high speed serial communication bus driver;
Fig. 5 is the bus driving circuits figure of Fig. 4;
Fig. 6 is invention adds bus driving circuits based on the impedance matching circuit of high speed serial communication bus driver a circuit diagram;
Mark in the accompanying drawing is as follows: U1, first operational amplifier, U2, second operational amplifier, U3, the 3rd operational amplifier, U4, four-operational amplifier, U5, the 5th operational amplifier, U6, the 6th operational amplifier, U7, the 7th operational amplifier, U3, the 3rd operational amplifier, M1, a MOS device, M2, the 2nd MOS device, M3, the 3rd MOS device, M4, the 4th MOS device, M5, the 5th MOS device, M6, the 6th MOS device, M7, the 7th MOS device, M8, the 8th MOS device, M9, the 9th MOS device.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present invention is described in detail, thereby protection scope of the present invention is made more explicit defining so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that.
As shown in Figure 1, be the circuit diagram of the impedance matching circuit of bus driver in the prior art.When a MOS device M1 and the 4th MOS device M4 are input as when high Vdp〉Vdn, differential signal is being for just, and when the 2nd MOS device M2 and the 3rd MOS device M3 are input as when high, Vdp＜Vdn differential signal is for negative.For making that high speed signal can normal transmission, need make the impedance matching of equivalent output impedance and transmission line of bus driver.As shown in Figure 2, its impedance matching circuit can only be realized the coupling of differential impedance, and can not accomplish the coupling of single-ended impedance.The equiva lent impedance sum of two output devices equates with the differential impedance of transmission line up and down, but up and down separately single-ended output impedance and the single-ended impedance of transmission line do not match, cause signal transmission to produce distortion.
As shown in Figure 3, because the degenerative effect of amplifier, voltage V1=V2=VDD_OU, the electric current of two current sources equate, so Rm5+Rm6+100=100+100 gets Rm5+Rm6=100 ohm.
In bus driving circuits, when being output as timing, preoutp=1, preoutn=0.The one MOS device M1 and the 4th MOS device M4 open, gate voltage equals PREVDD, the gate voltage of the 2nd MOS device M2 and the 3rd MOS device M3 is 0, be in off state, so a MOS device M1 is consistent with the working point of the 5th MOS device M5, the 4th MOS device M4 is consistent with the working point of the 6th MOS device M6, so Rm1+Rm4=100 ohm.
When being output as when negative, just in time opposite, a MOS device M1 and the 4th MOS device M4 turn-off, and the 2nd MOS device M2 and the 3rd MOS device M3 open, Rm2+Rm3=100 ohm.In fact a MOS device M1 the 3rd MOS device M3 also, the 2nd MOS device M2 and the 4th MOS device M4 are symmetries respectively.Consider monolateral output traditionally, we can say equivalent output impedance sum when a MOS device M1 and the 2nd MOS device M2 are in working order, difference output impedance just is 100 ohm, existing circuit can only guarantee that output impedance sum (being difference output impedance) is 100 ohm up and down, can not guarantee up and down output impedance separately, be that single-ended output impedance is 50 ohm, so in data transmission procedure, still can cause signal distortion.
The present invention has increased a feedback loop on the basis of existing design, make output impedance up and down all can with the impedance matching of transmission line, thereby make the integrality of signal can access better assurance.
See also Fig. 4, the invention provides a kind of impedance matching circuit based on the high speed serial communication bus driver, comprise the first operational amplifier U1, the second operational amplifier U2, the 3rd operational amplifier U3, first source lines, second source lines and the 3rd source lines, the described first operational amplifier U1 and first source lines electrically connect, described the 3rd operational amplifier U3 and the 3rd source lines electrically connect, the described first operational amplifier U1 electrically connects by second source lines and the 3rd operational amplifier U3, wherein, the bus driving circuits of described second operational amplifier U2 and bus driver electrically connects, and described bus driving circuits is the bus driving circuits of H type structure.
In above-mentioned, described first source lines, second source lines and the 3rd source lines are for being connected in parallel.Wherein, described first source lines comprises the 5th MOS device M1 of series connection setting successively and one 150 ohm resistance; Described second source lines comprises two 100 ohm the resistance that series connection successively is provided with.Described the 3rd source lines comprises the 6th MOS device M6, one 150 ohm resistance and the 7th MOS device M7 that series connection successively is provided with.
In the present invention, electric current on described first source lines, second source lines and the 3rd source lines equates, so the resistance of described the 5th MOS device M5 is 50 ohm, the resistance sum of described the 6th MOS device M6 and the 7th MOS device M7 is 50 ohm.
In the present invention, the bus driving circuits of described second operational amplifier U2 and bus driver electrically connects.As shown in Figure 5, described bus driving circuits comprises the 4th source lines, the 5th source lines and the 6th source lines, described the 4th source lines comprises the MOS device M1 that series connection successively is provided with, the 2nd MOS device M2 and the 8th MOS device M8, the 3rd MOS device M3 that described the 5th source lines is connected successively and is provided with, the 4th MOS device M4 and the 9th MOS device M9, described the 6th source lines comprises one 100 ohm resistance, and described the 4th source lines is connected in parallel by the 6th source lines and the 5th source lines.Wherein, described the 6th source lines is connected the lower end of the 2nd MOS device M2 and the lower end of the 3rd MOS device M3.
In above-mentioned, a described MOS device M1 and the 2nd MOS device M2 electrically connect with four-operational amplifier U4 and the 5th operational amplifier U5 respectively; Described the 3rd MOS device M3 and the 4th MOS device M4 electrically connect with the 6th operational amplifier U6 and the 7th operational amplifier U7 respectively.
Using two feedback loops respectively two groups of MOS devices up and down to be controlled among the present invention, make that the equiva lent impedance of the 5th MOS device M5 is 50 Ω, is 50 ohm after the equiva lent impedance addition of the 6th MOS device M6 and the 7th MOS device M7 simultaneously.Be complementary with prior art, new bus driving circuits has increased by two MOS devices, the 8th MOS device M8 and the 9th MOS device M9.The size of the one MOS device M1 and the 3rd MOS device M3 and the 5th MOS device M5's is measure-alike; The size of the 2nd MOS device M2 and the 4th MOS device M4 and the 6th MOS device M6's is measure-alike; The size of the 8th MOS device M8 and the 9th MOS device M9 is measure-alike with the 7th MOS device M7 then.
Because degenerative effect, the VDD_OUT signal level is identical with V2, and the grid of a MOS device M1, the 2nd MOS device M2, the 3rd MOS device M3 and the 4th MOS device M4 is subjected to the control of PREVDD.Like this, a MOS device M1, the 3rd MOS device M3 have identical working point and identical device size with the 5th MOS device M5, so identical equiva lent impedance is arranged.The 2nd MOS device M2, the 4th MOS device M4 have identical working point and identical device size with the 6th MOS device M6, so identical equiva lent impedance is arranged.The 8th MOS device M8, the 9th MOS device M9 have identical working point and identical device size with the 7th MOS device M7, so identical equiva lent impedance is arranged.So the equiva lent impedance of a MOS device M1, the 3rd MOS device M3 is 50 ohm, the equiva lent impedance of the 2nd MOS device M2 and the 8th MOS device M8 sum, the 4th MOS device M4 and the 9th MOS device M9 sum is 50 ohm.Thereby realized the bus driver coupling of single-ended output impedance and transmission line impedance up and down.
As shown in Figure 6, because the degenerative effect of amplifier, voltage V1=V2=V3=VDD_OU, the electric current of three current sources equate, so Rm5=50 ohm and Rm6+Rm7=50 ohm.
In bus driving circuits, when being output as timing, preoutp=1, preoutn=0.The one MOS device M1 and the 4th MOS device M4 open, gate voltage equals PREVDD, the gate voltage of the 2nd MOS device M2 and the 3rd MOS device M3 is 0, be in off state, so a MOS device M1 is consistent with the working point of the 5th MOS device M5, the 4th MOS device M4 is consistent with the working point of the 6th MOS device M6, and the 9th MOS device M9 is consistent with the 7th MOS device M7 working point, so Rm1=50 ohm, Rm4+Rm9=50 ohm.
When being output as when negative, just in time opposite, a MOS device M1 and the 4th MOS device M4 turn-off, and the 2nd MOS device M2 and the 3rd MOS device M3 open, thus Rm3=50 ohm, Rm2+Rm8=50 ohm.Can guarantee that single-ended output impedance is 50 ohm, so in data transmission, can better guarantee signal integrity.
The impedance matching circuit that the present invention discloses based on the high speed serial communication bus driver, on the basis of existing impedance matching circuit, increased a feedback loop, make output impedance up and down all can with the impedance matching of transmission line, thereby make the integrality of signal can access better assurance.
The above only is embodiments of the invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (10)
1. impedance matching circuit based on the high speed serial communication bus driver, it is characterized in that, comprise first operational amplifier, second operational amplifier, the 3rd operational amplifier, first source lines, second source lines and the 3rd source lines, described first operational amplifier and first source lines electrically connect, described the 3rd operational amplifier and the 3rd source lines electrically connect, described first operational amplifier electrically connects by second source lines and the 3rd operational amplifier, wherein, the bus driving circuits of described second operational amplifier and bus driver electrically connects.
2. the impedance matching circuit based on the high speed serial communication bus driver according to claim 1 is characterized in that, described first source lines, second source lines and the 3rd source lines are for being connected in parallel.
3. the impedance matching circuit based on the high speed serial communication bus driver according to claim 1 is characterized in that, described first source lines comprises the 5th MOS device of series connection setting successively and one 150 ohm resistance.
4. the impedance matching circuit based on the high speed serial communication bus driver according to claim 1 is characterized in that, described second source lines comprises two 100 ohm the resistance that series connection successively is provided with.
5. the impedance matching circuit based on the high speed serial communication bus driver according to claim 1 is characterized in that, described the 3rd source lines comprises the 6th MOS device of series connection setting successively, one 150 ohm resistance and the 7th MOS device.
6. according to the described impedance matching circuit of one of claim 1-5 based on the high speed serial communication bus driver, it is characterized in that, electric current on described first source lines, second source lines and the 3rd source lines equates, the resistance of described the 5th MOS device is 50 ohm, and the resistance sum of described the 6th MOS device and the 7th MOS device is 50 ohm.
7. the impedance matching circuit based on the high speed serial communication bus driver according to claim 1, it is characterized in that, described bus driving circuits comprises the 4th source lines, the 5th source lines and the 6th source lines, described the 4th source lines comprises the MOS device that series connection successively is provided with, the 2nd MOS device and the 8th MOS device, the 3rd MOS device that described the 5th source lines is connected successively and is provided with, the 4th MOS device and the 9th MOS device, described the 6th source lines comprises one 100 ohm resistance, and described the 4th source lines is connected in parallel by the 6th source lines and the 5th source lines.
8. the impedance matching circuit based on the high speed serial communication bus driver according to claim 7 is characterized in that, described the 6th source lines is connected the lower end of the 2nd MOS device and the lower end of the 3rd MOS device.
9. the impedance matching circuit based on the high speed serial communication bus driver according to claim 7 is characterized in that, a described MOS device and the 2nd MOS device electrically connect with four-operational amplifier and the 5th operational amplifier respectively.
10. the impedance matching circuit based on the high speed serial communication bus driver according to claim 7 is characterized in that, described the 3rd MOS device and the 4th MOS device electrically connect with the 6th operational amplifier and the 7th operational amplifier respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013101761772A CN103226538A (en) | 2013-05-14 | 2013-05-14 | Impedance matching circuit based on high-speed serial communication bus actuator |
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| CN2013101761772A CN103226538A (en) | 2013-05-14 | 2013-05-14 | Impedance matching circuit based on high-speed serial communication bus actuator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104281804A (en) * | 2014-09-22 | 2015-01-14 | 深圳市金立通信设备有限公司 | Terminal |
| CN107168916A (en) * | 2017-07-12 | 2017-09-15 | 珠海市杰理科技股份有限公司 | The output impedance control circuit of interface circuit |
| CN109417521A (en) * | 2016-04-28 | 2019-03-01 | 康杜实验室公司 | Low-power multi-level driver |
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| US20120032656A1 (en) * | 2010-08-04 | 2012-02-09 | Sungkyunkwan University Foundation For Corporate Collaboration | Voltage regulator for impedance matching and pre-emphasis, method of regulating voltage for impedance matching and pre-emphasis, voltage mode driver including the voltage regulator, and voltage-mode driver using the method |
| CN203287891U (en) * | 2013-05-14 | 2013-11-13 | 苏州文芯微电子科技有限公司 | Impedance matching circuit based on high-speed serial communication bus driver |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101005285A (en) * | 2006-01-18 | 2007-07-25 | 马维尔国际贸易有限公司 | Flash adc |
| CN101162606A (en) * | 2006-10-13 | 2008-04-16 | 晶豪科技股份有限公司 | Bit line pre-charging producer of dynamic ram |
| US20120032656A1 (en) * | 2010-08-04 | 2012-02-09 | Sungkyunkwan University Foundation For Corporate Collaboration | Voltage regulator for impedance matching and pre-emphasis, method of regulating voltage for impedance matching and pre-emphasis, voltage mode driver including the voltage regulator, and voltage-mode driver using the method |
| CN203287891U (en) * | 2013-05-14 | 2013-11-13 | 苏州文芯微电子科技有限公司 | Impedance matching circuit based on high-speed serial communication bus driver |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104281804A (en) * | 2014-09-22 | 2015-01-14 | 深圳市金立通信设备有限公司 | Terminal |
| CN109417521A (en) * | 2016-04-28 | 2019-03-01 | 康杜实验室公司 | Low-power multi-level driver |
| CN109417521B (en) * | 2016-04-28 | 2022-03-18 | 康杜实验室公司 | Low power multi-level driver |
| CN107168916A (en) * | 2017-07-12 | 2017-09-15 | 珠海市杰理科技股份有限公司 | The output impedance control circuit of interface circuit |
| CN107168916B (en) * | 2017-07-12 | 2019-08-20 | 珠海市杰理科技股份有限公司 | The output impedance control circuit of interface circuit |
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