CN101150087A - Device with plating through structure and its making method - Google Patents
Device with plating through structure and its making method Download PDFInfo
- Publication number
- CN101150087A CN101150087A CNA2007101672415A CN200710167241A CN101150087A CN 101150087 A CN101150087 A CN 101150087A CN A2007101672415 A CNA2007101672415 A CN A2007101672415A CN 200710167241 A CN200710167241 A CN 200710167241A CN 101150087 A CN101150087 A CN 101150087A
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- dielectric materials
- metal column
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
This invention relates to a method for manufacuring devices with coppered structure including: providing a backing to form a seed metal layer on it, forming a patternized metal circuit layer on the metal layer, forming a positive developed photoresistance layer on the mtal circuit layer and the seed metal layer, patternizing the photoresistance layer to define at least one through hole with a preset depth-width ratio to expose part of the patternized metal circuit layer, plating a metal material in the hole to form a metal post, removing the photoresistance layer, etching said seed metal layer to isolated circuits of the circuit layer and forming a dielectric layer on the backing, covering the crcuit layer and part of the metal post and exposing top of the metal post.
Description
Technical field
The invention relates to a kind of plating through structure, more be particularly to a kind of device and manufacture method thereof with plating through structure.
Background technology
Along with the geometric shape of semiconductor device is more and more littler, the size of components on its active surface also diminishes thereupon.For example, the passive component of semiconductor device (electric capacity) is made of two metal layers and plated-through-hole.In order to make the electric capacity smaller volume, then the area of this metal level need reduce, and this plated-through-hole need have high-aspect-ratio.In the manufacture method that has semiconductor device now, normally utilize sensing optical activity benzocyclobutene (Benzocyclobutene with plated-through-hole (via); BCB) as low dielectric material layer.Yet when sensing optical activity BCB made the small size plated-through-hole with the exposure imaging processing procedure, the size of this plated-through-hole can be subject to the characteristic that sensing optical activity BCB is the macromolecular material of minus development.
With reference to figure 1, it shows a kind of existing semiconductor device 10.This semiconductor device 10 comprises the low dielectric material layer 30 of a silicon substrate 12, some metallic traces 16 and a sensing optical activity BCB.This silicon substrate 12 is provided with several connection pads 15, in order to the integrated circuit (IC) (figure does not show) that is electrically connected to active surface.This metallic circuit 16 is disposed on this silicon substrate 12, and is electrically connected to this connection pad 15.The dielectric materials layer 30 of this sensing optical activity BCB is to be patterned by an exposure imaging processing procedure, in order to definition through hole 20.Metal material 22 is formed in this through hole 20, and to finish a plated-through-hole 24, it is positioned on this metallic circuit 16.Because this sensing optical activity BCB is the macromolecular material that minus develops, the through hole 20 that the dielectric materials layer 30 of this sensing optical activity BCB is defined when the exposure imaging processing procedure, its resolution is not good, and therefore aperture shape can't form minute sized plated-through-hole 24 for little big down.Normally, be the sensing optical activity BCB of 5 μ m with thickness t 1, the aperture d1 that can only form through hole 20 is 30 μ m, so the depth-to-width ratio of this plated-through-hole 24 (ratio of depth D 1/ width W 1) can only be limited less than 0.167.Again, make small plated-through-hole 24 in the dielectric materials layer 30 of this sensing optical activity BCB with the exposure imaging processing procedure, easily BCB is residued in the plated-through-hole 24, easy-clear does not so cause the manufacturing and electrical problem of back-end process easily.
No. the 20040077174th, U.S. Patent Publication, title are " manufacture method of the plated-through-hole of high-aspect-ratio (Method for forming a high aspect ratio via) ", disclose a kind of manufacture method of plated-through-hole.Though this patent discloses the manufacture method of the plated-through-hole of high-aspect-ratio, this patent does not disclose the photoresist layer that utilizes eurymeric to develop, and finishing plated-through-hole, and this plated-through-hole is positioned at dielectric materials, and has a method greater than 0.167 high-aspect-ratio.
Therefore, just have a kind of method that can solve aforesaid shortcoming need be provided.
Summary of the invention
A purpose of the present invention is to provide a kind of manufacture method that dielectric materials has the device of high-aspect-ratio plating through structure that is arranged in.
Another object of the present invention is to provide a kind of device with high-aspect-ratio plating through structure, this plating through structure is arranged in dielectric materials, and this dielectric materials to can be non-photosensitive macromolecular material made.
For reaching above-mentioned purpose, the invention provides a kind of manufacture method and comprise: a base material is provided with device of plating through structure; Form a seed metal layer on this base material; Form a pattern metal circuit layer on this seed metal layer; The photoresist layer that forms eurymeric development is on this pattern metal circuit layer and this seed metal layer; This photoresist layer of patterning exposes partly this pattern metal circuit layer in order to define at least one through hole, and wherein this through hole has a predetermined depth-to-width ratio; Electroplate a metal material in this through hole, to form a metal column, wherein this metal column has an end face; Remove this photoresist layer; Etch away this seed metal layer of part, the circuit that makes this pattern metal circuit layer is electrical isolation each other; And form a dielectric materials layer on this base material, and coat this pattern metal circuit layer and this metal column of part, and expose the end face of this metal column.This metal column is a plating through structure, and its depth-to-width ratio is between 0.167 and 2.
For reaching above-mentioned purpose, a kind of device of the present invention with plating through structure, it comprises: a base material; One seed metal layer is disposed on this base material; One metallic circuit layer is disposed on this seed metal layer; One metal column is disposed on this metallic circuit layer, and has an end face; And a dielectric materials layer, in order to coating this metallic circuit layer and this metal column of part, and expose the end face of this metal column, wherein the depth-to-width ratio of this metal column is between 0.167 and 2.
Compared with prior art, the photoresist layer that the present invention utilizes eurymeric to develop is finished plating through structure earlier, and then seals this plating through structure with dielectric materials and be positioned at it, so makes this plating through structure have a high-aspect-ratio.Moreover it is made that dielectric materials need not be defined as the photosensitive macromolecular material, and it is made also to can be non-photosensitive macromolecular material.In addition, the present invention utilizes dry etching steps that unnecessary dielectric material is removed on this plating through structure, so can avoid the manufacturing and electrical problem of back-end process.The high-aspect-ratio plating through structure that is positioned at dielectric materials of the present invention can be applicable to the passive component (electric capacity) or circuit rerouting layer (the Redistribution Layer of semiconductor device; RDL).
Description of drawings
Fig. 1 is the generalized section of the semiconductor device with plating through structure of prior art.
Fig. 2 is the flow chart of the manufacture method of the device with plating through structure structure of the first embodiment of the present invention.
Fig. 3 to Fig. 9 is the generalized section of the manufacture method of the device with plating through structure structure of this first embodiment of the present invention.
Figure 10 is the flow chart of the manufacture method of the device with plating through structure structure of the second embodiment of the present invention.
Figure 11 to Figure 17 is the generalized section of the manufacture method of the device with plating through structure structure of this second embodiment of the present invention.
Embodiment
With reference to figure 2, it shows the manufacture method of the device with plating through structure of the first embodiment of the present invention.In the present embodiment, this device is one to be used for circuit rerouting layer (Redistribution Layer; RDL) device 100.This manufacture method comprises the following step: with reference to figure 3, in step 202, provide a base material 102, such as silicon substrate.In step 204, a seed metal layer 104 is formed on this base material 102.In step 208, a pattern metal circuit layer 106 is formed on this seed metal layer 104.Such as, this pattern metal circuit layer 106 can be formed on this seed metal layer 104 by electroplating process or micro image etching procedure.
With reference to figure 4, in step 210, the sensing optical activity photoresist layer 108 that an eurymeric is developed is formed on this pattern metal circuit layer 106 and this seed metal layer 104.
With reference to figure 5, in step 212, with these photoresist layer 108 patternings, in order to define at least one through hole 110, it exposes partly this pattern metal circuit layer, and has a predetermined high-aspect-ratio.Since the macromolecular material that this photoresist layer 108 develops for eurymeric, the through hole 110 of this photoresist layer 108 when the exposure imaging processing procedure, its resolution is preferable, and the aperture is less.For example, be the sensing optical activity photoresist layer 108 of 10 μ m with thickness t 2, the aperture d2 that can form through hole 110 is 5 μ m, thus the depth-to-width ratio of this through hole 110 (ratio of depth D 2/ width W 2) can to promote be 2 and can not be subject to 0.167.Preferable, the predetermined depth-to-width ratio of this through hole 110 can be between 0.167 and 2.
With reference to figure 6, in step 214, as electroplate lead wire, at least one metal material 112 is plated in this through hole 110 by this seed metal layer 104, to form a metal column 114, it is positioned on this metallic circuit 106, and wherein this metal column 114 has an end face 116.Because the aperture of the through hole 110 that this sensing optical activity photoresist layer 108 is defined is less, therefore can form minute sized metal column 114.
With reference to figure 7,, remove this photoresist layer 108 in step 216.In step 218, etch away this seed metal layer 104 of part, with so that the circuit of this pattern metal circuit layer 106 electrical isolation each other.
With reference to figure 8, in step 220,, a dielectric materials layer 120 is formed on this base material 102, in order to this seed metal layer 104, this pattern metal circuit layer 106 and this metal column 114 are coated by coating method.Preferably, control the thickness of this dielectric materials layer 120, with the end face 116 that directly exposes this metal column 114.This dielectric materials layer 120 is the dielectric coefficient value less than 3.5 dielectric materials (low k material).It is made that this dielectric materials layer 120 can be the photosensitive macromolecular material.It is made that this sensing optical activity dielectric materials layer can be the macromolecular material that minus develops, such as benzocyclobutene (Benzocyclobutene; BCB) or pi (polyimide; PI).It is made that this sensing optical activity dielectric materials layer also can be the macromolecular material that eurymeric develops.Perhaps, it is made that this dielectric materials layer can be non-photosensitive macromolecular material, such as benzocyclobutene (Benzocyclobutene; BCB) or pi (polyimide; PI).In step 222, this dielectric materials layer 120 is solidified.
With reference to figure 9, in step 224, this dielectric materials layer 120 is etched to a predetermined thickness, in order to the end face 116 that exposes this metal column 114, so to finish the device 100 that this is used for circuit rerouting layer, wherein the etching step of this dielectric materials layer 120 is to carry out dry etching steps by an oxygen plasma processing procedure.Concrete, this metal column 114 is a plating through structure, it has the predetermined depth-to-width ratio (ratio of depth D 2/ width W 2) that is same as this through hole 110, for example between 0.167 and 2.
Compared with prior art, the photoresist layer that the present invention utilizes eurymeric to develop is finished plating through structure earlier, and then seals this plating through structure with dielectric materials and be positioned at it, so makes this plating through structure have a high-aspect-ratio.Moreover it is made that dielectric materials need not be defined as the photosensitive macromolecular material, and it is made also to can be non-photosensitive macromolecular material.In addition, the present invention utilizes dry etching steps that unnecessary dielectric material is removed on this plating through structure, so can avoid the manufacturing and electrical problem of back-end process.
With reference to Figure 10, it shows the manufacture method of the device with plating through structure of the second embodiment of the present invention.In the present embodiment, this device is semiconductor device 300.This manufacture method comprises the following step: with reference to Figure 11, in step 402, provide a base material 302, such as silicon substrate, it is provided with several connection pads 306, in order to the integrated circuit (IC) (figure does not show) that is electrically connected to active surface.In step 404, a metal level 304 is formed on this base material 302, and is electrically connected to this connection pad 306.
With reference to Figure 12, in step 410, the sensing optical activity photoresist layer 308 that an eurymeric is developed is formed on this metal level 304.
With reference to Figure 13, in step 412, with these photoresist layer 308 patternings, in order to define at least one through hole 310, wherein this through hole 310 exposes partly this metal level 304, corresponding to the position of this connection pad 306, and has a predetermined high-aspect-ratio.Since the macromolecular material that this photoresist layer 308 develops for eurymeric, the through hole 310 of this photoresist layer 308 when the exposure imaging processing procedure, its resolution is preferable, and the aperture is less.For example, be the sensing optical activity photoresist layer 308 of 10 μ m with thickness t 2, the aperture d2 that can form through hole 310 is 5 μ m, thus the depth-to-width ratio of this through hole 310 (ratio of depth D 2/ width W 2) can to promote be 2 and can not be subject to 0.167.Preferably, the predetermined depth-to-width ratio of this through hole 310 can be between 0.167 and 2.
With reference to Figure 14, in step 414, as electroplate lead wire, at least one metal material 312 is plated in this through hole 310 by this metal level 304, to form a metal column 314, it is positioned on this metal level 304, and wherein this metal column 314 has an end face 316.Because the aperture of the through hole 310 that this sensing optical activity photoresist layer 308 is defined is less, therefore can form minute sized metal column 314.
With reference to Figure 15,, remove this photoresist layer 308 in step 416.In step 418, etch away this metal level 304 of part, forming a metallic circuit layer, and make those connection pads 306 electrical isolation each other.
With reference to Figure 16, in step 420,, a dielectric materials layer 320 is formed on this base material 302, in order to this metal level 304, those connection pads 306 and this metal column 314 are coated by coating method.Preferably, control the thickness of this dielectric materials layer 320, with the end face 316 that directly exposes this metal column 314.This dielectric materials layer 320 is the dielectric coefficient value less than 3.5 dielectric materials (low k material).It is made that this dielectric materials layer 320 can be the photosensitive macromolecular material.It is made that this sensing optical activity dielectric materials layer can be the macromolecular material that minus develops, such as benzocyclobutene (Benzocyclobutene; BCB) or pi (polyimide; PI).It is made that this sensing optical activity dielectric materials layer also can be the macromolecular material that eurymeric develops.Perhaps, it is made that this dielectric materials layer can be non-photosensitive macromolecular material, such as benzocyclobutene (Benzocyclobutene; BCB) or pi (polyimide; PI).In step 422, this dielectric materials layer 320 is solidified.
With reference to Figure 17, in step 424, this dielectric materials layer 320 is etched to a predetermined thickness, in order to the end face 316 that exposes this metal column 314, so to form semiconductor device 300, wherein the etching step of this dielectric materials layer 320 is to carry out dry etching steps by an oxygen plasma processing procedure.Particularly, this metal column 314 is a plating through structure, and it has the predetermined depth-to-width ratio (ratio of depth D 2/ width W 2) that is same as this through hole 310, such as between 0.167 and 2.
Compared with prior art, the photoresist layer that the present invention utilizes eurymeric to develop is finished earlier plating through structure, And then seal this plating through structure position in the inner with dielectric materials, so make this plating through structure have one High-aspect-ratio. Moreover it is made that dielectric materials need not be defined as the photosensitive macromolecular material, also can For non-photosensitive macromolecular material made. In addition, the present invention utilizes dry etching steps with unnecessary Jie Electric material removes on this plating through structure, so can avoid the manufacturing and electrical problem of back-end process.
The high-aspect-ratio plating through structure structure that is positioned at dielectric materials of the present invention is not only to be applied to The passive component in the field of semiconductor device (electric capacity) or circuit rerouting layer, the present invention also can be applicable to appoint The what passive component of its technical field or circuit rerouting layer.
Claims (16)
1. manufacture method with device of plating through structure, its spy is to comprise the following step:
One base material is provided;
Form a seed metal layer on this base material;
Form a pattern metal circuit layer on this seed metal layer;
The photoresist layer that forms eurymeric development is on this pattern metal circuit layer and this seed metal layer;
This photoresist layer of patterning exposes partly this pattern metal circuit layer in order to define at least one through hole, and wherein this through hole has a predetermined depth-to-width ratio;
Electroplate a metal material in this through hole, to form a metal column, wherein this metal column has an end face;
Remove this photoresist layer;
Etch away this seed metal layer of part, the circuit that makes this pattern metal circuit layer is electrical isolation each other; And
Form a dielectric materials layer on this base material, and coat this pattern metal circuit layer and this metal column of part, and expose this end face of this metal column.
2. manufacture method with device of plating through structure, its spy is: comprise the following step:
One base material is provided, has several connection pads;
Form a metal level on this base material, and be electrically connected to this connection pad;
The photoresist layer that forms eurymeric development is on this metal level;
This photoresist layer of patterning exposes partly this metal level in order to define at least one through hole, and wherein this through hole has a predetermined depth-to-width ratio;
Electroplate a metal material in this through hole, to form a metal column, wherein this metal column has an end face;
Remove this photoresist layer;
Etch away this metal level of part, forming a metallic circuit layer, and make those connection pads electrical isolation each other; And
Form a dielectric materials layer on this base material, and coat this metal level and this metal column of part, and expose the end face of this metal column.
3. manufacture method as claimed in claim 1 or 2, its spy is: it comprises in addition this dielectric materials layer is etched to a predetermined thickness, in order to the step of the end face that exposes this metal column.
4. manufacture method as claimed in claim 3, its spy is: the etching step of this dielectric materials layer is to be undertaken by an oxygen plasma processing procedure.
5. manufacture method as claimed in claim 1 or 2, its spy is: this predetermined depth-to-width ratio is between 0.167 and 2.
6. manufacture method as claimed in claim 2, its spy is: this through hole is corresponding to the position of those connection pads.
7. device with plating through structure, it is characterized in that: it comprises a base material, a seed metal layer, a metallic circuit layer, a metal column and a dielectric materials layer; This seed metal layer is disposed on this base material; This metallic circuit layer is disposed on this seed metal layer; This metal column is disposed on this metallic circuit layer, and has an end face; This dielectric materials layer in order to coating this metallic circuit layer and this metal column of part, and exposes the end face of this metal column, and wherein the depth-to-width ratio of this metal column is between 0.167 and 2.
8. device with plating through structure, it is characterized in that: it comprises a base material, a metallic circuit layer, a metal column, a dielectric materials layer; This base material has several connection pads; This metallic circuit layer is disposed on this base material, and is electrically connected to this connection pad; This metal column is disposed on this metallic circuit layer, and has an end face; This dielectric materials layer in order to coating this metallic circuit layer and this metal column of part, and exposes the end face of this metal column, and wherein the depth-to-width ratio of this metal column is between 0.167 and 2.
9. as claim 7 or 8 described devices, it is characterized in that: this dielectric materials layer is non-photosensitive macromolecular material layer.
10. device as claimed in claim 9 is characterized in that: this macromolecular material is benzocyclobutene (Benzocyclobutene; BCB) or pi (polyimide; PI).
11. as claim 7 or 8 described devices, it is characterized in that: this dielectric materials layer has a low dielectric set occurrence, and it is less than 3.5.
12. as claim 7 or 8 described devices, it is characterized in that: this dielectric materials layer is the sensing optical activity dielectric materials layer.
13. device as claimed in claim 12 is characterized in that: this sensing optical activity dielectric materials layer is that the macromolecular material of minus development is made.
14. device as claimed in claim 13 is characterized in that: the macromolecular material that this minus develops is benzocyclobutene (Benzocyclobutene; BCB) or pi (polyimide; PI).
15. device as claimed in claim 12 is characterized in that: this sensing optical activity dielectric materials layer is that the macromolecular material of eurymeric development is made.
16. as claim 7 or 8 described devices, it is characterized in that: this device is the semiconductor device, and this base material is a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101672415A CN101150087B (en) | 2007-10-30 | 2007-10-30 | Device with plating through structure and its making method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101672415A CN101150087B (en) | 2007-10-30 | 2007-10-30 | Device with plating through structure and its making method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101150087A true CN101150087A (en) | 2008-03-26 |
| CN101150087B CN101150087B (en) | 2010-06-09 |
Family
ID=39250526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101672415A Active CN101150087B (en) | 2007-10-30 | 2007-10-30 | Device with plating through structure and its making method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101150087B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266931B (en) * | 2008-04-28 | 2010-06-02 | 日月光半导体制造股份有限公司 | Method for making the device with deep depth ration plating pass hole |
| CN105957843A (en) * | 2011-05-26 | 2016-09-21 | 台湾积体电路制造股份有限公司 | Conductive via structure |
-
2007
- 2007-10-30 CN CN2007101672415A patent/CN101150087B/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101266931B (en) * | 2008-04-28 | 2010-06-02 | 日月光半导体制造股份有限公司 | Method for making the device with deep depth ration plating pass hole |
| CN105957843A (en) * | 2011-05-26 | 2016-09-21 | 台湾积体电路制造股份有限公司 | Conductive via structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101150087B (en) | 2010-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10629647B2 (en) | Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device | |
| JP2951215B2 (en) | Method of manufacturing fine pattern electronic interconnect structure by phase mask laser | |
| TW200832641A (en) | Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof | |
| US7338816B2 (en) | Magnetic field sensing device and a fabricating method of the same | |
| KR20080066773A (en) | Fine pitch interconnect and method of making | |
| JPH10224014A (en) | Method for creating metallic stand-off on electronic circuit | |
| CN101150087B (en) | Device with plating through structure and its making method | |
| US8186043B2 (en) | Method of manufacturing a circuit board | |
| CN112599424A (en) | Manufacturing method of ultrathin substrate structure | |
| TW200849542A (en) | Device having high aspect ratio via in low dielectric material and method for manufacturing the same | |
| CN101266931B (en) | Method for making the device with deep depth ration plating pass hole | |
| KR20070043856A (en) | Interconnect assemblies and methods | |
| TW201307184A (en) | Thin film structure for high density inductors and redistribution in wafer level packaging | |
| KR20080005528A (en) | Probe pad structure in a ceramic space transformer | |
| JP2004103911A (en) | Method for forming wiring | |
| EP0285820A2 (en) | Method and structure for identifying non-functional chip connect pads | |
| JP4023236B2 (en) | Method for forming metal wiring | |
| KR100598308B1 (en) | Method of forming a damascene pattern in a semiconductor device | |
| US7863181B2 (en) | Method for manufacturing a device having a high aspect ratio via | |
| US10607856B2 (en) | Manufacturing method of redistribution layer | |
| JP5880508B2 (en) | Wiring board and manufacturing method thereof | |
| KR20240002751A (en) | Method for manufacturing semiconductor package | |
| KR100372657B1 (en) | Method for forming contact of semiconductor device | |
| KR100905708B1 (en) | Method for fabricating probe card assembly using silicon bonded wafer | |
| KR20160001826A (en) | Method for manufacturing a circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |