CN101140887A - Method for manufacturing FinFET transistor - Google Patents
Method for manufacturing FinFET transistor Download PDFInfo
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- CN101140887A CN101140887A CNA200710176291XA CN200710176291A CN101140887A CN 101140887 A CN101140887 A CN 101140887A CN A200710176291X A CNA200710176291X A CN A200710176291XA CN 200710176291 A CN200710176291 A CN 200710176291A CN 101140887 A CN101140887 A CN 101140887A
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Abstract
The invention discloses a manufacturing method for FinFET transistor, which is to take the SOI (semiconductor on insulator) wafer with crystallographic orientation of (110) as the underlay material, rust the semiconductor layer of the SOI material by aeolotropic rusting to form a semiconductor bar with smooth side perpendicular to the surface and make high doping on the middle part of the semiconductor bar. Then taking the semiconductor bar as the underlay, select from two sides to make epitaxial growth of a semiconductor film and rust the high doping area of the semiconductor bar by large rusting selection ratio of heavy and light doping. The both ends and the extension layer of the semiconductor bar left forms a super thin Fin body, on which gate dielectric and gate electrode are grown. After the next step of normal CMOS, the FinFET transistor thus is produced.
Description
Technical field
The present invention relates to the method for a kind of making FinFET (fin-shaped field effect transistor).
Background technology
Since the integrated circuit invention, its performance steadily improves always.The raising of performance mainly is to realize by the size of constantly dwindling integrated circuit (IC)-components.At present, the characteristic size of integrated circuit (IC)-components (MOSFET) has narrowed down to nanoscale.Under this yardstick, the various basic restrictions with reality begin to occur, and make the development that is based upon the integrated circuit technique on the silicon planar CMOS technology just suffer unprecedented challenge.It is generally acknowledged that through great efforts, the CMOS technology still might be advanced to 20 nanometers even 10 nm technology node, but after 45 nanometer nodes, traditional planar CMOS technology will be difficult to further develop, new technology must produce in good time.In the middle of the various new technologies that proposed, multiple-grid MOS device technology is considered to be hopeful most the technology that is applied after inferior 45 nanometer nodes.Compare with the single gate device of tradition, the multiple-grid device has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
At present, FinFET (fin-shaped field effect transistor) device can be realized by the planar CMOS technology of routine because of its self-alignment structure, thereby is become most promising multiple-grid device.FinFET structurally can be divided into double grid FinFET and three gate FinFETs.Concerning double grid FinFET, for obtaining acceptable device performance, the thickness that requires its Fin is 1/2～1/3 of grid length, and like this, the level of microfabrication must develop in advance significantly.On the other hand, with regard to three gate FinFETs, because three faces of Fin body all are subjected to the control of gate electrode, ought to have stronger short channel control ability, therefore the thickness of Fin body can be worked as with the grid appearance or is bigger, (minimum) characteristic size that is device is still long for grid, and the microfabrication level is not proposed extraordinary requirement, thereby more compatible with the traditional cmos process technology.Yet, theoretical and experimental study shows that all under channel doping concentration condition with higher, three gate FinFETs have presented more good short-channel properties really, but at raceway groove is under the situation of light (nothing) doping, and three grid structures are not compared with double-gate structure and significantly improved.And under the nanoscale situation, for fear of the dispersion of the discrete device threshold voltage that causes of amount of impurities, the MOS device can not adopt highly doped raceway groove, promptly must adopt light (nothing) doped channel.In addition, under the situation of identical channel area, the device of three grid structures is than double-gate structure, even the device of single grid structure takies more chip area.Therefore, comprehensive, double grid FinFET is preferable new device structure.
Although it seems that at present double grid FinFET more promises to be follow-on integrated circuit (IC)-components than three gate FinFETs, before entering practicability, must solve some crucial technical barriers.The processing of ultra-thin Fin body is exactly one of topmost difficult problem.The Experiment Preparation technology of being reported at present all can not become big production technology.The manufacture method of the Fin body of being demonstrated is so far normally passed through certain means again on the basis of photoetching, manage as litho pattern being carried out districts such as ashing (Ashing), to reach further dwindling of figure.This technology can not be used for the making of circuit because the uniformity of the descriptive geometry size that forms and repeatability are very poor.Side wall figure transfer technology (spacer imagetransfer) can be used to make individual devices though be a kind of easy nanoscale process technology, and this technology can produce numerous parasitic figures, thereby can not be used for the making of circuit.
Summary of the invention
The purpose of this invention is to provide the transistorized method of a kind of making FinFET.
The transistorized method of making FinFET provided by the present invention comprises the steps:
1) selecting the crystal orientation for use is that the SOI wafer of (110) is a backing material, at substrate surface growth one deck film dielectric layer, after the photoetching, corrodes the semiconductor layer of described soi wafer with anisotropic etchant, and it is smooth and perpendicular to the semiconductor bar on surface to form a side; Then, the mid portion to described semiconductor bar carries out heavy doping;
2) be substrate with described soi wafer, the epitaxial loayer of respectively growing in the side of described semiconductor bar;
3) erode the film dielectric layer at described semiconductor bar top, manifest the top of semiconductor bar self; Then, erode the middle heavy doping part of described semiconductor bar, keep the unadulterated zone of epitaxial loayer and two ends of described semiconductor bar both sides, form two ultra-thin Fin bodies, the zone at described semiconductor bar two ends will become transistorized source region of FinFET and drain region respectively;
4) growth gate dielectric layer and gate material on described Fin body, then photoetching, etching gate material form gate electrode figure; Then, mixed in described gate electrode, source region and drain region;
5) growth of passivation layer on the full wafer wafer, this passivation layer of photoetching and etching is in the source, the contact zone of leakage and gate electrode forms via hole; Then, the growth layer of metal film, this metal film of photoetching and etching forms metal electrode and interconnection line, obtains described FinFET transistor.
Wherein, the described film dielectric layer of step 1) is a silicon dioxide layer.Anisotropic etchant is a tetramethyl ammonium hydroxide solution, and mass concentration is 15-35%.It is as follows that the mid portion of described semiconductor bar is carried out the heavy doping process: the mid portion at described semiconductor bar carries out heavy doping, and dopant is N type commonly used or p type impurity, and implantation dosage is greater than 1 * 10
14Cm
-2, the injection energy is 10-50KeV; Under 850～950 ℃ temperature, annealed 20～50 minutes then.
Step 2) described epitaxial loayer is the non-impurity-doped silicon fiml, and thickness is the 10-50 nanometer.
The film dielectric layer that step 3) erodes described semiconductor bar top adopts the silica erosion liquid (BOE solution) of buffering to corrode; Erode the middle heavy doping of described semiconductor bar and partly adopt the corrosive liquid corrosion, described corrosive liquid is by 40%HF, 70%HNO
3And 100%CH
3COOH forms, and its volume ratio is 1/ (2.5-3.5)/(7.5-8.5), is preferably 1/3/8.
The described gate dielectric layer of step 4) is silicon dioxide layer, silicon oxynitride or hafnium, and thickness is 0.7～20 nanometer; Described gate material is a polysilicon.Mixed in described gate electrode, source region and drain region, used dopant is N type commonly used or p type impurity, and the injection energy is 15～45KeV, and implantation dosage is (1～10) * 10
15Cm
-2
In doping process of the present invention, the used dopant of preparation N type device is a N type impurity, as V group elements such as arsenic, phosphorus; The used dopant of preparation P type device is a p type impurity, as III family elements such as boron, galliums.
Advantage of the present invention and good effect: the thickness of Fin body must be 1/2～1/3 of grid length in the FinFET device, but, the minimum feature size that the advanced CMOS technology of each up-to-date release of generation can be processed is the length of grid normally, therefore can not satisfy the much smaller Fin body processing of size.In the technical scheme that the present invention proposes, the processing of Fin body is not subjected to the restriction of photoetching and lithographic technique level, makes FinFET technology and main stream of CMOS technology compatible fully; Secondly, the thickness of Fin body determines by epitaxy technique, so the uniformity of the uniformity of Fin body thickness, Fin bodily form looks all can improve a lot and improve; Moreover, as the side of the semiconductor bar of epitaxial substrate require smooth and as far as possible with Surface Vertical, so just can obtain high-quality epitaxial loayer.The side that conventional lithographic method forms is general more coarse, and is difficult to fully vertical with the surface.In technical solution of the present invention, owing to adopted the anisotropic etch of high selection ratio, the side of formed semiconductor bar is vertical naturally and surperficial near minute surface, promotes the performance of FinFET device.
Description of drawings
Fig. 1-Fig. 7 shows main manufacturing process steps successively, wherein:
Fig. 1 has illustrated the substrate S OI material that adopted;
Fig. 2 has illustrated the processing step that top thin silicon dioxide layer 4 and supporter silicon strip 5 forms, right side part to illustrate the stereogram of silicon strip 5;
Fig. 3 has illustrated the processing step that silicon strip 5 mid portions mix, right side part to illustrate the stereogram of silicon strip 5;
Fig. 4 has illustrated the processing step of silicon strip 5 both sides epitaxial growth silicon fimls 7, right side part to illustrate the stereogram of silicon strip 5;
Fig. 5 has illustrated the processing step of heavy doping partial corrosions in the middle of top thin silicon dioxide layer 4 and the silicon strip 6, right side part to illustrate the stereogram of silicon strip 5;
Fig. 6 has illustrated the processing step of gate medium 8 silicon dioxide growth;
Fig. 7 has illustrated the processing step of gate material electrode 9 and figure processing, right side part to illustrate the plane graph of component graphics this moment.
Embodiment
The present invention prepares the transistorized method of FinFET and mainly adopts following process: selecting the crystal orientation for use is that SOI (the semiconductor on insulator) wafer of (110) is a backing material, it is smooth and perpendicular to the semiconductor bar on surface that the semiconductor layer that corrodes this SOI material with anisotropic caustic solution forms a side, and the mid portion of this semiconductor bar is carried out heavy doping.Be substrate with this semiconductor bar then, from both sides selective epitaxy growth semiconductor film, utilize corrosion enough big between weight, the light dope material to select ratio again, erode the heavily doped region of semiconductor bar, stay the two ends and the epitaxial loayer of semiconductor bar, just form required ultra-thin Fin body.Growth gate medium and gate electrode carry out the conventional cmos later process again on this Fin body, promptly obtain the FinFET transistor.
Concrete manufacture method, mainly be may further comprise the steps to shown in Figure 7 by Fig. 1:
As shown in Figure 1, the substrate that is adopted is that the crystal orientation is the soi wafer of (110), comprises silicon body region 1, buried oxidation layer 2 and monocrystalline silicon membrane 3, and monocrystalline silicon membrane 3 is not for or light dope, and thickness is 50～250nm.
As shown in Figure 2, at first at the thin oxide layer 4 of superficial growth one deck 10～50nm, growing method can be one of following method: conventional thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD) etc.Carry out after the conventional photoetching, use earlier the dry etching thin oxide layer, use anisotropic etchant (Tetramethylammonium hydroxide (TMAH) solution, mass concentration is 20～40%) corrosion monocrystalline silicon membrane 3 to form silicon strip 5 then, the side of formed silicon strip 5 is (111) crystal orientation.
As shown in Figure 3, the mid portion to formed silicon strip 5 carries out arsenic ion injection doping to form highly doped silicon area 6.Implantation dosage is 1 * 10
15Cm
-2, inject energy 33KeV.Under 900 ℃, annealed 30 minutes then.
As shown in Figure 4, at silicon strip 5 both sides epitaxial growths one epitaxial loayer 7.Because the bottom of silicon strip 5 and top are covered by thin oxide layer 4 and buried oxidation layer 2, therefore can guarantee to grow occurs over just two sides of silicon strip, and epitaxial loayer 7 is a non-impurity-doped silicon, and thickness is 10～50 nanometers.
As shown in Figure 5, at first with the silica erosion liquid (BOE solution, the NH that cushion
4F: water=70g: 135ml, and add 12ml HF) falls the thin oxide layer 4 at silicon strip 5 tops, then with corrosive liquid corrosion (40%HF/70%HNO
3/ 100%CH
3COOH=1: 3: 8 (volume ratio)), erodes the highly doped silicon area 6 of silicon strip mid portion, stay not (gently) doped region at epitaxial loayer 7 and silicon strip 5 two ends.Like this, form two Fin bodies, the mid portion of epitaxial loayer 7 will become the channel region of device, and the zone at silicon strip 5 two ends will become source region (D district) and drain region (the S district) of device respectively.
As shown in Figure 6, the silicon dioxide gate dielectric layer 8 of thermal oxide growth 0.7～2 nanometer on the Fin body.
As shown in Figure 7, the polysilicon layer 9 of deposit one 80～200 nanometer thickness, photoetching and etching form gate electrode (G district) then.Follow ion implantation doping gate electrode, source region and drain region.To n type device, dopant is V group elements such as arsenic, phosphorus, and to p type device, dopant is III family elements such as boron, gallium.Inject energy 15～45KeV, implantation dosage (1～10) * 10
15Cm
-2
Enter the conventional cmos later process at last, the phosphorosilicate glass layer that comprises deposit one deck 200～500 nanometers is as passivation layer, by photoetching and this passivation layer of etching in the source, the contact zone opening contact hole of leakage and grid, and the aluminium film of deposit one deck 400～800 nanometers and photoetching and etching formation metal electrode and interconnection line etc., promptly make the FinFET transistor.
Claims (9)
1. make the transistorized method of FinFET for one kind, comprise the steps:
1) selecting the crystal orientation for use is that the SOI wafer of (110) is a backing material, at substrate surface growth one deck film dielectric layer, after the photoetching, corrodes the semiconductor layer of described soi wafer with anisotropic etchant, and it is smooth and perpendicular to the semiconductor bar on surface to form a side; Then, the mid portion to described semiconductor bar carries out heavy doping;
2) be substrate with described soi wafer, the epitaxial loayer of respectively growing in the side of described semiconductor bar;
3) erode the film dielectric layer at described semiconductor bar top, manifest the top of semiconductor bar self; Then, erode the middle heavy doping part of described semiconductor bar, keep the unadulterated zone of epitaxial loayer and two ends of described semiconductor bar both sides, form two ultra-thin Fin bodies, the zone at described semiconductor bar two ends will become transistorized source region of FinFET and drain region respectively;
4) growth gate dielectric layer and gate material on described Fin body, then photoetching, etching gate material form gate electrode figure; Then, mixed in described gate electrode, source region and drain region;
5) growth of passivation layer on entire wafer, this passivation layer of photoetching and etching is in the source, the contact zone of leakage and gate electrode forms via hole; Then, the growth layer of metal film, this metal film of photoetching and etching forms metal electrode and interconnection line, obtains described FinFET transistor.
2. method according to claim 1 is characterized in that: the described film dielectric layer of step 1) is a silicon dioxide layer.
3. method according to claim 1 is characterized in that: the described anisotropic etchant of step 1) is a tetramethyl ammonium hydroxide solution, and mass concentration is 15-35%.
4. method according to claim 1 is characterized in that: it is as follows that step 1) is carried out the heavy doping process to the mid portion of described semiconductor bar:
Mid portion at described semiconductor bar carries out heavy doping, and dopant is N type commonly used or p type impurity, and implantation dosage is greater than 1 * 10
14Cm
-2, the injection energy is 10-50KeV; Under 850～950 ℃ temperature, annealed 20～50 minutes then.
5. according to the arbitrary described method of claim 1-4, it is characterized in that: step 2) described epitaxial loayer is the non-impurity-doped silicon fiml, thickness is the 10-50 nanometer.
6. according to the arbitrary described method of claim 1-4, it is characterized in that: the film dielectric layer that step 3) erodes described semiconductor bar top adopts the silica erosion liquid (BOE solution) of buffering to corrode; Erode the middle heavy doping of described semiconductor bar and partly adopt the corrosive liquid corrosion, described corrosive liquid is by 40%HF, 70%HNO
3And 100%CH
3COOH forms, and its volume ratio is 1/ (2.5-3.5)/(7.5-8.5), is preferably 1/3/8.
7. according to the arbitrary described method of claim 1-4, it is characterized in that: the described gate dielectric layer of step 4) is silicon dioxide layer, silicon oxynitride or hafnium, and thickness is 0.7～20 nanometer; Described gate material is a polysilicon.
8. method according to claim 7 is characterized in that: mixed in described gate electrode, source region and drain region, used dopant is N type commonly used or p type impurity, and the injection energy is 15～45KeV, and implantation dosage is (1～10) * 10
15Cm
-2
9. method according to claim 8 is characterized in that: described N type impurity is arsenic or phosphorus; P type impurity is boron or gallium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710176291XA CN100550326C (en) | 2007-10-24 | 2007-10-24 | The transistorized method of a kind of making FinFET |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710176291XA CN100550326C (en) | 2007-10-24 | 2007-10-24 | The transistorized method of a kind of making FinFET |
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| CN101140887A true CN101140887A (en) | 2008-03-12 |
| CN100550326C CN100550326C (en) | 2009-10-14 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130014A (en) * | 2011-01-05 | 2011-07-20 | 北京大学深圳研究生院 | Method for manufacturing FinFET (field effect transistor) |
| CN103594372A (en) * | 2012-08-17 | 2014-02-19 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
| CN103824759A (en) * | 2014-03-17 | 2014-05-28 | 北京大学 | Method for preparing plurality of layers of superfine silicon lines |
| WO2015032279A1 (en) * | 2013-09-04 | 2015-03-12 | International Business Machines Corporation | Trench sidewall protection for selective epitaxial semiconductor material formation |
| US9362387B2 (en) | 2013-02-05 | 2016-06-07 | Huawei Technologies Co., Ltd. | Method for producing multi-gate in FIN field-effect transistor |
-
2007
- 2007-10-24 CN CNB200710176291XA patent/CN100550326C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130014A (en) * | 2011-01-05 | 2011-07-20 | 北京大学深圳研究生院 | Method for manufacturing FinFET (field effect transistor) |
| CN102130014B (en) * | 2011-01-05 | 2012-11-07 | 北京大学深圳研究生院 | Method for manufacturing FinFET (field effect transistor) |
| CN103594372A (en) * | 2012-08-17 | 2014-02-19 | 中国科学院微电子研究所 | Manufacturing method for semiconductor device |
| US9362387B2 (en) | 2013-02-05 | 2016-06-07 | Huawei Technologies Co., Ltd. | Method for producing multi-gate in FIN field-effect transistor |
| WO2015032279A1 (en) * | 2013-09-04 | 2015-03-12 | International Business Machines Corporation | Trench sidewall protection for selective epitaxial semiconductor material formation |
| US9252014B2 (en) | 2013-09-04 | 2016-02-02 | Globalfoundries Inc. | Trench sidewall protection for selective epitaxial semiconductor material formation |
| US9269575B2 (en) | 2013-09-04 | 2016-02-23 | Globalfoundries Inc. | Trench sidewall protection for selective epitaxial semiconductor material formation |
| CN103824759A (en) * | 2014-03-17 | 2014-05-28 | 北京大学 | Method for preparing plurality of layers of superfine silicon lines |
| CN103824759B (en) * | 2014-03-17 | 2016-07-06 | 北京大学 | A kind of method preparing the ultra-fine silicon lines of multilamellar |
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| Publication number | Publication date |
|---|---|
| CN100550326C (en) | 2009-10-14 |
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