CN110416297A - N-type fin formula field effect transistor and forming method thereof - Google Patents
N-type fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN110416297A CN110416297A CN201810389918.8A CN201810389918A CN110416297A CN 110416297 A CN110416297 A CN 110416297A CN 201810389918 A CN201810389918 A CN 201810389918A CN 110416297 A CN110416297 A CN 110416297A
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 230000005669 field effect Effects 0.000 title claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 131
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- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 310
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 55
- 229910052710 silicon Inorganic materials 0.000 claims description 55
- 239000010703 silicon Substances 0.000 claims description 55
- 229910052698 phosphorus Inorganic materials 0.000 claims description 27
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 26
- 239000011574 phosphorus Substances 0.000 claims description 26
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical group [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
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- 239000012495 reaction gas Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 5
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 3
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- 238000000926 separation method Methods 0.000 description 13
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
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- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 3
- TVGGZXXPVMJCCL-UHFFFAOYSA-N [Si].[La] Chemical compound [Si].[La] TVGGZXXPVMJCCL-UHFFFAOYSA-N 0.000 description 3
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- LGERWORIZMAZTA-UHFFFAOYSA-N silicon zinc Chemical compound [Si].[Zn] LGERWORIZMAZTA-UHFFFAOYSA-N 0.000 description 3
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- 239000010937 tungsten Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
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- 238000005520 cutting process Methods 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
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- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- JXBAVRIYDKLCOE-UHFFFAOYSA-N [C].[P] Chemical compound [C].[P] JXBAVRIYDKLCOE-UHFFFAOYSA-N 0.000 description 1
- FAUIDPFKEVQLLR-UHFFFAOYSA-N [O-2].[Zr+4].[Si+4].[O-2].[O-2].[O-2] Chemical compound [O-2].[Zr+4].[Si+4].[O-2].[O-2].[O-2] FAUIDPFKEVQLLR-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
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- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
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- 239000008246 gaseous mixture Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
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- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides a kind of forming method of N-type fin formula field effect transistor with multiple fins, for the forming method the following steps are included: forming epitaxial layer on multiple fins, epitaxial layer has gap between fin adjacent to each other；Fin contact etching stop layer is formed on epitaxial layer, which can fill gap.The forming method fills the gap between fin, epitaxial layer originally separate is connected by continuing epitaxial lateral overgrowth on existing epitaxial layer.In subsequent contact etching step, the film layer of gap location prevents gap location from being cut through as fin contact etching stop layer, so as to avoid the generation of leakage point of electricity after deposit metal, improves product yield.
Description
Technical field
The present invention relates to field of semiconductor fabrication processes, more particularly it relates to which a kind of N-type fin field effect is brilliant
The manufacturing method of body pipe.
Background technique
In existing fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) production technology
In, phosphorus doping and Ge-doped silicon epitaxy layer are widely used in the carrier mobility and source-drain electrode for improving transistor
In doping.Wherein, Germanium-doped silicon epitaxial layer is generally formed on the fin of p-type FinFET, to obtain the p-type source and drain of high-dopant concentration
Pole；And the source and drain areas in N-type FinFET fin is then provided with the phosphorous doped silicon epitaxial layer of high-dopant concentration, to improve device
Energy.
In some FinFETs, a plurality of fin can be arranged in certain single FinFET transistors (such as 4T-FinFET),
The a plurality of fin is collectively as source-drain electrode, therefore these fins can be shorted mutually, in this way the source-drain area in p-type FinFET
Just without having to worry about short problems when domain grows Germanium-doped silicon epitaxial layer, and it is bigger to obtain so that them is merged (merge) as far as possible
Extension volume.Since the compression stress of the bigger generation of the volume of Germanium-doped silicon epitaxial layer is higher, p-type FinFET compression
The raising of stress usually can be realized by the increase of epitaxial layer volume.
For N-type FinFET, situation is then not quite similar.In the outer delay of source and drain areas growth of N-type FinFET, more small size
Phosphorous doped silicon epitaxial layer can more obtain better tensile stress effect, therefore in prior art, generally use small size,
Phosphorous doped silicon epitaxial layer separate between fin.
Although in the later process such as extension, side wall technique, source and drain injection, metal gates growth, this small size
, discontinuous phosphorous doped silicon epitaxial layer do not influence device efficiency.But during contact etching forms contact hole, this
The gap location for the phosphorous doped silicon epitaxial layer that kind does not merge will be cut through, and after depositing metal, metal layer bottom will be with fin bottom
Position undoped with phosphorus connects, and such tie point will become the leakage point of electricity in IC system, damages device performance and product
Yield.
Summary of the invention
In view of the above problem of the prior art, i.e. gap of N-type FinFET transistor during contact etching, between fin
Place is easy to be cut through, and forming a large amount of leakage point of electricity finally influences device performance and yield, and the present invention provides one kind to have multiple fins
The forming method of the N-type fin formula field effect transistor in portion can prevent the generation of leakage point of electricity, improve product yield.
The forming method of the N-type fin formula field effect transistor the following steps are included:
Epitaxial layer is formed on multiple fins, epitaxial layer has gap between fin adjacent to each other；
Fin contact etching stop layer is formed on epitaxial layer, which can fill gap.
Forming method provided by the present invention fills multiple fins by growing fin contact etching stop layer on epitaxial layer
Gap between portion connects epitaxial layer originally separate.In subsequent contact etching step, the fin of gap location
Contact etching stop layer can prevent fin gap location from being cut through, and so as to avoid the generation of leakage point of electricity after deposit metal, improve
Product yield.
In more excellent technical solution of the invention, the formation fin contact etching stop layer the step of in, the fin
Portion's contact etching stop layer is obtained by continuing epitaxial lateral overgrowth on the crystal face of the epitaxial layer.
Further, in more excellent technical solution of the invention, the fin is formed using chemical vapor deposition method and is connect
Touch etching stop layer.
Further, in more excellent technical solution of the invention, the fin is formed using chemical vapor deposition method
When contact etching stop layer, cavity temperature is 400-800 DEG C.
Further, in more excellent technical solution of the invention, the fin is formed using chemical vapor deposition method
When contact etching stop layer, the reaction gas of use includes at least SiH4、SiH2Cl2、PH3、H2、HCl。
In more excellent technical solution of the invention, epitaxial layer is phosphorous doped silicon epitaxial layer.When epitaxial layer is outside phosphorous doped silicon
When prolonging layer, volume is smaller, and the tensile stress applied to fin is bigger；Therefore, technical staff can be using small size, discontinuous
Epitaxial layer cooperates continuous fin contact etching stop layer to avoid the generation of leakage point of electricity under the premise of guaranteeing tensile stress effect.
Further, in more excellent technical solution of the invention, use is undoped, phosphorus is lightly doped or phosphorus in the silicon that adulterates
Fin contact etching stop layer is made in material or metal-semiconductor compounds.Preferably, the metal-semiconductor compounds are titanium
Silicon compound, aluminium silicon compound, lanthanum silicon compound, zinc silicon compound.Metal-semiconductor compounds have metallic character, have compared with
Low resistance is able to suppress the rising of contact resistance when carving incomplete subsequent time.
When preparing fin contact etching stop layer using the material same or similar with epitaxial layer, process made above can
To carry out in same CVD chamber and be completed using identical or essentially identical reaction gas, without increasing additional step, simply
It is convenient.
In more excellent technical solution of the invention, the thickness of fin contact etching stop layer is less than 200 angstroms.Above with a thickness of
The thickness for the not etched fin contact etching stop layer being originally formed, and it is thick for the film layer of epi-layer surface above fin
Degree.The film layer should not be too thick, to prevent the thickness finally retained excessive, causes the influence to contact resistance.
It is further comprising the steps of after forming fin contact etching stop layer in more excellent technical solution of the invention:
It returns and carves the fin contact etching stop layer.After forming continuous fin contact etching stop layer, which will cover whole
A source and drain areas, although playing the role of barrier metal enters gap, simultaneously also epitaxial layer and metal contact between shape
At dead resistance, it is unfavorable for the reduction of the contact resistance of source and drain areas.Therefore, it is increased in this more excellent technical solution additional
Is carried out back to the fin contact etching stop layer, since fin contact etching stop layer during the growth process can be in phase the step of carving
Position between adjacent fin merges, and the thickness (i.e. fin adjacent position) of combined region is greater than direct growth district (i.e. fin
Top position film layer) thickness, therefore in subsequent time quarter step, even if the stop-layer above fin is etched completely, by
In the reason of the difference in thickness, the interstitial site between fin still remaining can be filled with certain thickness stop-layer, in subsequent step
In play the role of stop contact etching.Therefore, the parameter of step is carved by rationally adjusting this time, can be stopped guaranteeing film layer
While corrasion, inhibit the rising of contact resistance, improves device performance.
Further, it in more excellent technical solution of the invention, in epitaxial growth chamber, is returned and is carved using HCl reaction gas
The fin contact etching stop layer.The technical program makes technical staff that can complete epitaxial growth, excessively raw in the same chamber
It grows and returns and carve step, simplify the technological process of production.
Further, in more excellent technical solution of the invention, step is carved to returning for the fin contact etching stop layer
Using dry etching.After growing film layer using isotropic depositing step, reusing anisotropic dry etching time quarter should
The connection effect of remaining film layer can be effectively ensured in film layer.In addition, in the present invention return carve step to selection ratio requirement also compared with
It is low, same or similar epitaxial layer even can be used in some embodiments and stop layer material, therefore be more suitble to using dry
Method etching.
Further, in more excellent technical solution of the invention, the etching gas of dry etching uses HBr, Cl2、
HCl、SO2、Ar、O2、CF4、CHF3、CH2F2、CH3F、He、H2、CH4One or more of combination.
Further, in more excellent technical solution of the invention, through Hui Kehou, the fin on the multiple fin is connect
Touch etching stop layer with a thickness of -100~100 angstroms, the thickness of the fin contact etching stop layer between the multiple fin
It is 0~200 angstrom.In this more excellent technical solution, the negative value in fin contact etching stop layer thickness refers to, carves in step returning,
Fin contact etching stop layer is etched completely not only, has also etched certain thickness epitaxial layer.By the fin contact between fin
Etching stop layer is etched to 0~100 angstrom, or epitaxial layer is exposed, and advantageously reduces the contact between metal and epitaxial layer
Resistance improves device performance；Need to retain certain thickness fin contact etching stop layer between fin simultaneously, to ensure between fin
Gap is not stayed, prevents Metal deposition from entering.
In more excellent technical solution of the invention, the manufacturing method of the N-type fin formula field effect transistor further includes following
Step: interlayer dielectric layer is formed on the fin contact etching stop layer；The interlayer of contact etching at least part active area
Dielectric layer；Wherein, in the interlayer dielectric layer of contact etching at least part active area, the interlayer dielectric layer and the fin
Contact etching stop layer has the selection ratio of 5:1 or more, preferably 10:1 or more or 20:1 or more.In this more excellent technical solution,
By selecting the requirement of ratio, equipment, the parameter selection of material and contact etching to fin contact etching stop layer are defined,
Contact etching is stopped at stop-layer in time, improves blocking effect.
The present invention also provides a kind of N-type fin formula field effect transistor, which includes multiple fins
Epitaxial layer in portion and fin, position of the epitaxial layer between fin adjacent to each other have gap, fin are provided on epitaxial layer
Portion's contact etching stop layer, the fin contact etching stop layer cover the gap between fin adjacent to each other.Existing N-type fin field
Effect transistor uses the phosphorous doped silicon epitaxial layer of small size, and there are gap between different fins, such gap may induce leakage
The generation of electricity point, reduces device performance.The present invention eliminates electric leakage by the way that fin contact etching stop layer is arranged on epitaxial layer
The generation of point, improves properties of product and yield.
In more excellent technical solution of the invention, epitaxial layer is phosphorous doped silicon epitaxial layer, and the fin contact etching stops
Layer is the silicon layer or metal-semiconductor compounds layer that undoped, phosphorus is lightly doped, adulterates in phosphorus.Undoped, phosphorus be lightly doped or
The silicon layer adulterated in phosphorus not only can preferably be combined with phosphorous doped silicon epitaxial layer, but also with inter-level dielectric oxide subsequent
Selection ratio with higher, can be improved blocking effect, prevents from cutting through in contact etching step.In addition, this more excellent technical solution
In epitaxial layer and fin contact etching stop layer due to using identical or essentially identical material be made, in preparation process
In can be formed in the same chamber, and without increasing additional step, greatly facilitate product preparation.
In more excellent technical solution of the invention, the fin contact etching stop layer of interstitial site with a thickness of 0~200
Angstrom, fin contact etching stop layer on multiple fins with a thickness of 0~100 angstrom.Fin contact etching stop layer between fin
Thickness is limited in 0~100 angstrom or directly exposes epitaxial layer, advantageously reduces the contact electricity between metal and epitaxial layer
Resistance improves device performance；The position between fin retains certain thickness fin contact etching stop layer simultaneously, to ensure between fin
Gap is not stayed, prevents Metal deposition from entering.
Detailed description of the invention
FIG. 1 to FIG. 3 is the forming process schematic diagram of p-type fin formula field effect transistor in the prior art；
Fig. 4~Fig. 5 is the forming process schematic diagram of N-type fin formula field effect transistor in the prior art；
Fig. 6~Figure 12 is the forming process schematic diagram of N-type fin formula field effect transistor in one embodiment of the invention.
Specific embodiment
Outside it can be seen from background technology that, existing N-type fin formula field effect transistors using small size, discontinuous phosphorous doped silicon
Prolong layer preparation, will be cut through when gap is in contact etching, become leakage point of electricity, damages device performance and product yield.
In order to clearly illustrate the gap of prior art epitaxial layers is how to induce N-type fin formula field effect transistor
The generation of leakage point of electricity, below in conjunction with attached drawing respectively to the forming process of p-type in the prior art and N-type fin formula field effect transistor
It is analyzed, passes through the origin cause of formation of comparative analysis leakage point of electricity.
For p-type fin formula field effect transistor, forming process is as shown in Figure 1-Figure 3.
As shown in Figure 1, the forming process of p-type fin formula field effect transistor includes: firstly, substrate 100 is provided, in substrate
Multiple discrete fins 101 are formed on 100 and fill separation layer 102；After forming gate structure (not shown), need in fin
One Germanium-doped silicon epitaxial layer 103 of growth regulation in portion 101.In order to apply higher compression stress to fin 101, separate
One Germanium-doped silicon epitaxial layer 103 is unable to satisfy volume requirement, it is therefore desirable to which the second Germanium-doped silicon of continued growth epitaxial layer 104 makes
First Germanium-doped silicon epitaxial layer 103 is connected to each other.
Then, as shown in Fig. 2, postchannel process can form place contact etching stop layer 105 on the basis of existing structure
(Contact Etch Stop Layer, CESL) and first layer interlayer dielectric layer 106, deposit the interlayer dielectric layer 106 of formation
The gap 108 of 101 adjacent positions of fin will be filled, but since adjacent position gap 108 is smaller, which can not tegillum
Between medium fill up, and in interlayer dielectric layer 106 formed hole 107.
With continued reference to Fig. 3, M0 bit line contacting window 109 is etched, and fills M0 metal.It is etched in M0 bit line contacting window 109
Cheng Zhong, the second Germanium-doped silicon epitaxial layer 104 and place contact etching stop layer 105 all can be used as stop-layer protection and tie below
Structure is unaffected.Therefore, for p-type fin formula field effect transistor, even if forming hole 107, M0 metal will not be with fin 101
It is in electrical contact, therefore, not will cause the formation of leakage point of electricity.
For N-type fin formula field effect transistor, with reference to Fig. 4, forming process includes: firstly, offer substrate 200, is serving as a contrast
Multiple discrete fins 201 are formed on bottom 200 and fill separation layer 202；After forming gate structure (not shown), need
One layer of phosphorous doped silicon epitaxial layer 203 is grown on fin 201, since N-type fin formula field effect transistor utilizes phosphorous doped silicon epitaxial layer
The characteristics of 203 pairs of fins 201 apply tensile stress are as follows: when the small volume of usual phosphorous doped silicon epitaxial layer 203, for fin
The effect of 201 application tensile stresses is preferable.Thus it is common to use small size, phosphorous doped silicon epitaxial layer 203 separate, different
There are gaps 208 between phosphorous doped silicon epitaxial layer 203 on fin 201.Since the spacing between fin 201 is minimum, give birth to thereon
The size in the gap 208 between long phosphorous doped silicon epitaxial layer 203 is also minimum, and the very small dimensions in the gap 208 will make deposition steps
Contact etching stop layer 204 and interlayer dielectric layer 205 are more difficult from the entrance of the position in gap 208 in rapid, cause in gap 208
Contact etching stop layer 204 and interlayer dielectric layer 205 be difficult to be filled up completely, and form hole 206.
Relatively incompletely due to the filling of contact etching stop layer 204 between fin 201 it is difficult to play normal with continued reference to Fig. 5
Barrier effect, the hole 206 having inside interlayer dielectric layer 205 is further degrading the situation, therefore, connects in M0 bit line
In the etching process for touching window 207,208 rectangular structure of gap of fin 201 is easy to be cut through, when leading to depositing contact metal,
It contacts metal to enter from gap 208, directly be contacted with fin 201 after deposition, become the leakage point of electricity in device, damage device
Can, influence product yield.
Hereinafter, generaling description the preferred embodiment of the present invention on one side referring to attached drawing while.In addition, embodiment party of the invention
Formula is not limited to following embodiments, can be using various embodiment party within the scope of the technical concept of the present invention
Formula.
Structural schematic diagram such as Fig. 6 to Figure 12 of fin n type field effect transistor forming process provided in an embodiment of the present invention
It is shown.
Step S1: referring to Fig. 6,300 be substrate in figure, forms several isolated fins 301 on 300 surface of substrate,
And separation layer 302 is formed on 300 surface of substrate, 301 top of fin is lower than at the top of the separation layer 302, and be covered in fin
The partial sidewall surface in portion 301.
The substrate 300 can be silicon or silicon-on-insulator (SOI), and the substrate is also possible to germanium, germanium silicon, GaAs
Or germanium on insulator, the material of substrate 300 described in the present embodiment are silicon.It can reduce to be formed as substrate using silicon substrate
The cost of fin formula field effect transistor, and it is compatible with the manufacture craft of existing planar transistor.
P-well is formed in the substrate 300.Adjusting thresholds injection can also be carried out to the substrate 300, it is subsequent to adjust
The threshold voltage of the fin formula field effect transistor of formation.And it anneals to the substrate 300, to activate the substrate 300
Interior Doped ions.
The material of the fin 301 can be monocrystalline silicon or nano wire silicon.In the present embodiment, the fin 301 is to use
Dry etching method etches what an initial substrate was formed, forms the fin 301. of protrusion on 300 surface of substrate
In other embodiments of the present invention, can also be after substrate surface form semiconductor epitaxial layers, then etch described half
Conductor epitaxial layer forms fin 301, and the semiconductor epitaxial layers can be monocrystalline silicon layer.
As one embodiment, the forming step of the fin 301 are as follows: initial substrate is provided；In the initial substrate table
Face forms patterned mask layer, and the patterned mask layer defines the position for being subsequently formed fin 301；With patterned
Mask layer is exposure mask, using reactive ion etching process, the initial substrate of etched portions thickness to forming substrate 300, while
300 surface of substrate forms several discrete fins 301.
In other embodiments, fin 301 can also be formed using double-pattern exposure method, specifically, forming fin
Processing step include: offer initial substrate；Patterned sacrificial layer is formed in the initial substrate surface；Formation is covered in institute
State the initial side wall film of sacrificial layer surface and initial substrate surface；It returns and carves the initial side wall film, formed in sacrificial layer side wall
Initial side wall layer；Remove the sacrificial layer；Using the initial side wall layer as exposure mask, the initial substrate shape of etching removal segment thickness
Several discrete fins 301 are formed at substrate 300, while on 300 surface of substrate.
The material of the separation layer 302 can be the insulating dielectric materials such as silica, silicon nitride or silicon oxide carbide, it is described every
Absciss layer 302 as the isolation structure between adjacent fin 301, and between the gate structure being subsequently formed and substrate 300 every
From structure.
The forming method of the separation layer 302 includes: the depositing isolation material on the substrate 300, the isolated material
Fin 301 is covered, and fills the groove between the adjacent fin 301 of full phase；Stopped using at the top of the fin 301 as grinding
Layer carries out planarization process to the isolated material using chemical mechanical milling tech, and formation is flushed with 301 top surface of fin
Spacer material layer；Then, the spacer material layer carve, decline the apparent height of the spacer material layer, shape
It is lower than the separation layer 302 of 301 top surface of fin at surface.
Step S2: being developed across the gate structure of at least one fin 301 on 302 surface of separation layer, described
The atop part surface of gate structure covering fin 301 and sidewall surfaces, schematic diagram basically illustrate source in the embodiment of the present invention
The structure of drain region, therefore gate structure is not shown in the diagram.
In the present embodiment, the gate structure be dummy gate structure, dummy gate structure include gate dielectric layer and be located at grid
The material of the pseudo- grid of dielectric layer surface, the gate dielectric layer and pseudo- grid can be the same or different；Wherein, the gate dielectric layer
Material be silica, it is described puppet grid material be polysilicon.It is subsequent to use rear grid technique, gold is formed after removing dummy gate structure
Belong to gate structure.
As one embodiment, the gate structure can also be including gate dielectric layer and positioned at the gate dielectric layer surface
Grid conductive layer.It is done by taking metal gate structure as an example exemplary illustrated.Wherein, the material of the gate dielectric layer is hafnium oxide, oxidation
The high K dielectric material such as zirconium, aluminium oxide, silicon hafnium oxide or silicon zirconium oxide, the material of the grid conductive layer are aluminium, tungsten, titanium, oxidation
The gate metals material such as titanium, tantalum or tantalum carbide, grid of the gate structure as finally formed fin formula field effect transistor
Structure.
In other embodiments, the gate structure can be polysilicon gate construction, wherein the material of gate dielectric layer is
Silica, the material of grid conductive layer are the polysilicon of polysilicon or doping.
In the present embodiment, the gate structure is across multiple fins 301, so as to increase the ditch below gate structure
The area in road region.In other embodiments, according to actual process requirements, gate structure can be across one or more fins
301。
As one embodiment, the forming step of the gate structure includes: to form grid on 302 surface of separation layer to be situated between
The material bed of material, the gate dielectric material layer cover 302 surface of separation layer, 301 top surface of fin and sidewall surfaces；Institute
It states gate dielectric material layer surface and forms grid conductive material layer；Patterned mask layer is formed in the grid conductive material layer surface；
Using the patterned mask layer as exposure mask, the graphical grid conductive material layer and gate dielectric material layer are developed across fin
The gate structure in portion 301；Remove the patterned mask layer.
Step S3: gate structure two sides sidewall surfaces formed offset side wall, and to the fin of gate structure two sides 301 into
Injection is lightly doped in row, forms lightly doped district.
As one embodiment, the forming step of the offset side wall includes: deposition offset side wall material layer；Using it is each to
Anisotropic dry etch process etch bias spacer material layer forms offset side wall in gate structure two sides sidewall surfaces.
The material of the offset side wall is the insulating materials such as silicon nitride, silica or silicon oxynitride, described in the present embodiment
The material selection silicon nitride of offset side wall.The lightly doped district reduces hot current-carrying for reducing the transverse electric field intensity of source-drain area
Sub- effect.
As one embodiment, the formation process of the lightly doped district are as follows: using gate structure and offset side wall as exposure mask, In
Implanting impurity ion in the semiconductor substrate of gate structure two sides forms lightly doped district.In the present embodiment, the fin field effect
Transistor is N-type, and used injection ion is As or P, and the energy of the ion implanting is 1keV~4keV, and dosage is
2E14atom/cm2~1E15atom/cm2, injection angle is 0~20 degree.
Step S4: referring to Fig. 7, adjusting growth time, forms epitaxial layer 303 in the top position of fin 301.
The present embodiment by the material of the epitaxial layer 303 using phosphorus doping silicon materials (SiP) for do it is exemplary illustrated,
The epitaxial layer 303 can generate action of pulling stress to the fin 301 as channel region below gate structure, to improve
Electron mobility in channel region improves the performance of N-type fin field effect pipe.
The epitaxial layer 303 is formed in 301 top surface of fin using selective epitaxial process.The extension reaction temperature
It is 400~800 DEG C, SiP is formed using silicon source and phosphorus source gas reaction, wherein silicon source gas is SiH4And SiH2Cl2, phosphorus source gas
Body is PH3, further include H2And HCl, wherein silicon source gas, phosphorus source gas, HCl flow be 1sccm~1000sccm, H2
Flow be 0.1slm~50slm.
By the way that epitaxial growth obtains epitaxial layer 303 respectively on different fins 301, the epitaxial layer 303 on each fin 301
Crystal structure is all had, since the growth rate of each crystal orientation is different, finally formed crystal structure has class as shown in Figure 7
Diamond shape (diamond-like) structure.The epitaxial layer 303 has gap 308 between adjacent fin 301.
Although in the present embodiment, for the epitaxial layer 303 using the silicon epitaxy of phosphorus doping, technical staff can be according to reality
Situation, selects other kinds of epitaxial material, such as carbon doping silicon epitaxy or carbon phosphorus doping silicon epitaxy, as long as it can be to fin
Channel in portion 301 applies the tensile stress of suitable size and Orientation.
Step S5: referring to Fig. 8, on the crystal face of the epitaxial layer 303 formed continue epitaxial lateral overgrowth and obtain fin to connect
Touch etching stop layer 304, the fin contact etching stop layer 304 being capable of gap inside filling step S4 epitaxial layers 303
308, so that epitaxial structure is become continuous film.
As one embodiment, epitaxial layer 303 and fin contact etching stop layer 304 use identical or essentially identical material
Material is made." essentially identical material " refers to that material type is identical herein, but certain component ratio or atomic composition ratios are slightly not
Together.For example, in the present embodiment, the material of the epitaxial layer 303 is the silicon materials of phosphorus doping, the fin contact etching stops
Elementary silicon can be used in layer 304, phosphorus is lightly doped or the silicon materials of middle doping are made.Correspondingly, step S5 and step S4 can
To be recurred in same chemical vapor deposition chamber, i.e. chemical vapor deposition processes since epitaxial growth epitaxial layer 303,
Until cut-off is completed in the outgrowth of fin contact etching stop layer 304.If the fin contact etching stop layer 304 using with it is outer
Prolong the different material of 303 each component ratio of layer, if the silicon materials of elementary silicon or various concentration phosphorus doping are made, then can react
Cheng Zhong realizes the growth of fin contact etching stop layer 304 by adjusting the concentration ratio of reaction gas.
In the present embodiment, undoped, phosphorus be lightly doped or phosphorus in the silicon layer that adulterates not only can be with phosphorous doped silicon epitaxial layer
Preferably combine, and with inter-level dielectric oxide in subsequent contact etching step selection ratio with higher, Neng Gouti
High impedance effect prevents from cutting through.In addition, epitaxial layer 303 and fin contact etching stop layer 304 choose it is identical or essentially identical
Material can deposit formation in the same chamber during the preparation process, without increasing additional step, enormously simplify product
Preparation process.
Certainly, in other preferred embodiments of the invention, technical staff can also use according to the needs of actual process
The fin contact etching stop layer 304 is made in different materials, for example, stopping when in subsequent step for the fin contact etching
Only layer 304 return carve thickness it is smaller when, in order to reduce contact resistance, gold is can be used in the material of fin contact etching stop layer 304
Belong to semiconducting compound, such as titanium-silicon compound, aluminium silicon compound, lanthanum silicon compound, zinc silicon compound.As long as the fin connects
Touch etching stop layer 304 material can in subsequent contact etching step can with interlayer dielectric layer 306 compared with compared with
High selection is than (usual the selection ratio be set greater than 5:1, preferably 10:1 or 20:1), and to the tensile stress of epitaxial layer 303
Influential effect is smaller.
Similarly, the extension reaction temperature is 400~800 DEG C, forms SiP using silicon source and phosphorus source gas reaction,
Middle silicon source gas is SiH4Or SiH2Cl2, phosphorus source gas is PH3, further include H2And HCl, wherein silicon source gas, phosphorus source gas,
The flow of HCl be 1sccm~
1000sccm, H2Flow be 0.1slm~50slm, by adjust the epitaxial growth reaction time, it is finally formed
The thickness of fin contact etching stop layer is less than 200 angstroms.The thickness of the film layer can not be too thin, to prevent growth time too short, nothing
Method connects the epitaxial layer 303 at different 301 tops of fin.Meanwhile the film layer also should not be too thick, with prevent from finally retaining
Thickness is excessive, causes the influence to contact resistance.
Step S6: referring to Fig. 9, returning and carve fin contact etching stop layer 304, through Hui Kehou, 303 top of epitaxial layer and upside
The contact etching stop layer 304 of wall surface is thinned, and the contact etching stop layer 304 at lateral connection be then able to maintain it is adjacent
Connection between fin 301.
After forming continuous fin contact etching stop layer, which will cover entire source and drain areas, although rising
The effect that barrier metal enters gap has been arrived, but has also formd dead resistance between epitaxial layer and metal contact simultaneously, it is unfavorable
In the reduction of the contact resistance of source and drain areas.Therefore, it is increased in the present embodiment additional to fin contact etching stopping
Layer carries out back the step of carving, and under the premise of guaranteeing film layer barrier effect, reduces the rising of contact resistance, improves device performance.
In the present embodiment, described time quarter step uses anisotropic dry etching.Etching gas used in the dry etching
Body uses HBr, Cl2、HCl、SO2、Ar、O2, fluoro-gas (such as CF4、CHF3、CH2F2、CH3F etc.), He, H2、CH4Gaseous mixture.
As one embodiment, described time quarter step occurs in the chamber of epitaxial growth, is directly returned using HCl reaction gas
The fin contact etching stop layer 304 is carved, further, the formation step of epitaxial layer 303, fin contact etching stop layer 304
It is rapid and return and carve step and occur in the same chamber, and front and back recurs, which is remarkably improved fin contact
The formation quality of etching stop layer 304, avoids the generation of leakage point of electricity, while improving production efficiency.
In other preferred embodiments of the invention, described time quarter step can also using wet etching complete.
Referring to Figure 10, during depositing fin contact etching stop layer 304, when neighbouring fin contact etching
Stop-layer 304 is grown into merging, and the thickness T for merging position (adjacent position i.e. between fin 301) will be much larger than single
The thickness d or l of a growth position (position i.e. above fin).Therefore, no matter using anisotropic dry etching or using each
To the wet etching of the same sex, as long as rationally control etch period and speed, preferably by etch thicknesses control between d, l and T,
Due to difference in thickness, 308 position of gap between fin remaining can be filled with certain thickness stop-layer always, subsequent
Play the role of stopping contact etching in step.Therefore, the parameter of step is carved by rationally adjusting this time, can guarantee film layer
While stopping corrasion, inhibit the rising of contact resistance, improves device performance.
In the present embodiment, through Hui Kehou, the thickness l of the fin contact etching stop layer 304 of 301 top of fin is -100~
100 angstroms, the thickness T of the fin contact etching stop layer 304 between fin 301 is 0~200 angstrom.Fin between fin is contacted and is carved
Erosion stop-layer 304 is etched to 0~100 angstrom, or epitaxial layer 303 is exposed, and advantageously reduces the contact metal that rear road is formed
With the contact resistance between epitaxial layer 303, device performance is improved；Retain certain thickness fin contact etching between fin simultaneously to stop
Only layer 304 prevent Metal deposition from entering to ensure not stay gap between fin.
Step S7: referring to Figure 11, side wall is formed；Complete source and drain injection, annealing；Dummy grid is removed, metal gates are formed；Shape
At place contact etching stop layer 305；Inter-level dielectric is filled, interlayer dielectric layer 306 is formed；Finally formed source and drain areas section
Structure is as shown in figure 11.
Step S8: referring to Figure 12, M0 bit line etches and deposits M0 tungsten, forms contact metal layer 307.
In M0 bit line etch step, since 303 surface of the present embodiment epitaxial layers and gap location are covered with fin contact
Etching barrier layer 304, the barrier layer have the etching selection with the about 20:1 of interlayer dielectric layer 306 in M0 bit line etch step
Than.Therefore, contact etching step is generally difficult to cut through the barrier layer.In this way, in subsequent M0 metal deposition step, tungsten
It will not be contacted with fin and form leakage point of electricity.
In conclusion present embodiments providing a kind of forming method of N-type fin formula field effect transistor.By existing outer
Prolong and continue epitaxial lateral overgrowth on layer, fill the gap between multiple fins, epitaxial layer originally separate is connected.Rear
In continuous contact etching step, the film layer of gap location prevents fin gap location from being cut through as fin contact etching stop layer, from
And the generation of leakage point of electricity after deposit metal is avoided, improve product yield.In addition, the forming method in the present embodiment also passes through
It returns and carves fin contact etching stop layer, reduce the contact resistance of source and drain areas, improve device performance.
2 are continued to refer to figure 1, the present embodiment additionally provides a kind of N-type fin formula field effect transistor structure.The N-type fin field
Effect transistor includes the epitaxial layer 303 on separation layer 302 and fin between substrate 300, multiple fins 301, fin 301, should
The position between fin adjacent to each other of epitaxial layer 303 has gap 308, and the stopping of fin contact etching is provided on epitaxial layer 303
Layer 304, which covers the gap 308 between multiple fins.
In the present embodiment, the substrate 300 is silicon substrate.In other embodiments, the substrate can also for germanium substrate,
The semiconductor substrates such as silicon-Germanium substrate or silicon-on-insulator substrate.
In the present embodiment, the material of the fin 301 is silicon.In other embodiments, the material of the fin 301 may be used also
Think germanium or SiGe.
In the present embodiment, the material of the separation layer 302 is silica.In other embodiments, the material of the separation layer
Material can also be the dielectric materials such as silicon nitride, silicon oxide carbide.
In the present embodiment, the material of the epitaxial layer 303 is SiP.In the present embodiment, epitaxial layer 303 is outside phosphorous doped silicon
Prolong layer, fin contact etching stop layer 304 is the silicon layer that phosphorus is lightly doped.In other embodiments, the material of the epitaxial layer 303
It can also be SiCP or SiC etc., the material of the fin contact etching stop layer 304 can also be to be adulterated in undoped or phosphorus
Silicon layer or the metal-semiconductor compounds such as titanium-silicon compound, aluminium silicon compound, lanthanum silicon compound, zinc silicon compound.
Fin contact etching stop layer 304 between multiple fins 301 with a thickness of 0~200 angstrom, multiple 301 tops of fins
Fin contact etching stop layer 304 with a thickness of 0~100 angstrom.
Existing N-type fin formula field effect transistor uses the phosphorous doped silicon epitaxial layer of small size, exists between different fins
Gap, such gap are filled with metal as leakage point of electricity, reduce device performance.The present invention on epitaxial layer by being arranged fin
Contact etching stop layer 304 eliminates the generation of leakage point of electricity, improves properties of product and yield.And epitaxial layer 303 and fin connect
Touching etching stop layer 304, during the preparation process can be same due to being made using identical or essentially identical material
It is formed in chamber, and without increasing additional step, greatly facilitates product preparation.Fin contact etching between fin 301 stops
304 thickness of layer are limited in 0~100 angstrom or directly expose epitaxial layer 303, advantageously reduce contact metal layer 307 and outer
Prolong the contact resistance between layer 303, improves device performance；The position between fin 301 retains certain thickness fin contact simultaneously
Etching stop layer 304 prevents Metal deposition from entering to ensure not stay gap between fin.
So far, it has been combined attached drawing and describes technical solution of the present invention, still, skilled addressee readily understands that
It is that protection scope of the present invention is expressly not limited to these specific embodiments.Under the premise of without departing from the principle of the present invention,
Those skilled in the art can make equivalent change or replacement to the relevant technologies feature, the technology after these changes or replacement
Scheme will fall within the scope of protection of the present invention.
Claims (17)
1. a kind of forming method of N-type fin formula field effect transistor, the fin formula field effect transistor has multiple discrete fins
Portion, which comprises the following steps:
Epitaxial layer is formed on multiple fins, the epitaxial layer has gap between the fin adjacent to each other；
Form fin contact etching stop layer on said epitaxial layer there, the fin contact etching stop layer can fill it is described between
Gap.
2. the forming method of N-type fin formula field effect transistor as described in claim 1, which is characterized in that in the formation fin
In the step of portion's contact etching stop layer, the fin contact etching stop layer is outer by continuing on the crystal face of the epitaxial layer
Prolong outgrowth to obtain.
3. the forming method of N-type fin formula field effect transistor as claimed in claim 2, which is characterized in that use chemical gaseous phase
Deposition method forms the fin contact etching stop layer.
4. the forming method of N-type fin formula field effect transistor as claimed in claim 3, which is characterized in that use chemical gaseous phase
When deposition method forms the fin contact etching stop layer, cavity temperature is 400-800 DEG C.
5. the forming method of N-type fin formula field effect transistor as claimed in claim 3, which is characterized in that use chemical gaseous phase
When deposition method forms the fin contact etching stop layer, the reaction gas of use includes at least SiH4、SiH2Cl2、PH3、H2、
HCl。
6. the forming method of N-type fin formula field effect transistor as described in claim 1, which is characterized in that the epitaxial layer is
Phosphorous doped silicon epitaxial layer.
7. the forming method of N-type fin formula field effect transistor as claimed in claim 6, which is characterized in that using it is undoped,
Phosphorus be lightly doped or phosphorus in the silicon materials that adulterate or metal-semiconductor compounds the fin contact etching stop layer is made.
8. the forming method of N-type fin formula field effect transistor as described in claim 1, which is characterized in that the fin contact
The thickness of etching stop layer is less than 200 angstroms.
9. the forming method of N-type fin formula field effect transistor as described in claim 1, which is characterized in that forming the fin
It is further comprising the steps of after portion's contact etching stop layer:
It returns and carves the fin contact etching stop layer.
10. the forming method of N-type fin formula field effect transistor as claimed in claim 9, which is characterized in that in extension growth chamber
Interior is returned using HCl reaction gas and carves the fin contact etching stop layer.
11. the forming method of N-type fin formula field effect transistor as claimed in claim 9, which is characterized in that connect to the fin
It touches returning for etching stop layer and carves step using dry etching.
12. the forming method of N-type fin formula field effect transistor as claimed in claim 11, which is characterized in that the dry method is carved
The etching gas of erosion uses HBr, Cl2、HCl、SO2、Ar、O2、CF4、CHF3、CH2F2、CH3F、He、H2、CH4One of or it is more
The combination of kind.
13. the forming method of N-type fin formula field effect transistor as claimed in claim 9, which is characterized in that through Hui Kehou, institute
State the fin contact etching stop layer on multiple fins with a thickness of -100~100 angstroms, the fin of the interstitial site
Portion's contact etching stop layer with a thickness of 0~200 angstrom.
14. the forming method of N-type fin formula field effect transistor as described in claim 1, which is characterized in that further include following step
It is rapid:
Interlayer dielectric layer is formed on the fin contact etching stop layer；
Interlayer dielectric layer described in contact etching；
Wherein, when the interlayer dielectric layer described in contact etching, the interlayer dielectric layer and the fin contact etching stop layer have
There is the selection ratio of 5:1 or more.
15. a kind of N-type fin formula field effect transistor, including the epitaxial layer on multiple discrete fins and fin, the epitaxial layer
There is gap between the fin adjacent to each other, which is characterized in that further include fin contact etching stop layer, the fin connects
Touching etching stop layer is set on the epitaxial layer, fills the gap.
16. N-type fin formula field effect transistor as claimed in claim 15, which is characterized in that the epitaxial layer is phosphorous doped silicon
Epitaxial layer, the fin contact etching stop layer are the silicon layer or metal semiconductor that undoped, phosphorus is lightly doped, adulterates in phosphorus
Close nitride layer.
17. N-type fin formula field effect transistor as claimed in claim 15, which is characterized in that the fin of the interstitial site
Portion's contact etching stop layer with a thickness of 0~200 angstrom, the thickness of the fin contact etching stop layer on the multiple fin
It is 0~100 angstrom.
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| CN103187304A (en) * | 2012-01-03 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Methods of manufacturing semiconductor devices and transistors |
| CN103972236A (en) * | 2013-02-05 | 2014-08-06 | 格罗方德半导体公司 | Integrated circuits including finfet devices and methods for fabricating the same |
| CN105845725A (en) * | 2015-01-12 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method therefor, and electronic device |
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| CN103187304A (en) * | 2012-01-03 | 2013-07-03 | 台湾积体电路制造股份有限公司 | Methods of manufacturing semiconductor devices and transistors |
| CN103972236A (en) * | 2013-02-05 | 2014-08-06 | 格罗方德半导体公司 | Integrated circuits including finfet devices and methods for fabricating the same |
| CN105845725A (en) * | 2015-01-12 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method therefor, and electronic device |
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| CN113658918A (en) * | 2021-08-17 | 2021-11-16 | 福建省晋华集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
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