CN101136372A - 形成半导体器件的方法 - Google Patents

形成半导体器件的方法 Download PDF

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CN101136372A
CN101136372A CNA2007101455748A CN200710145574A CN101136372A CN 101136372 A CN101136372 A CN 101136372A CN A2007101455748 A CNA2007101455748 A CN A2007101455748A CN 200710145574 A CN200710145574 A CN 200710145574A CN 101136372 A CN101136372 A CN 101136372A
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朴真何
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DB HiTek Co Ltd
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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Abstract

本发明的实施方式涉及形成90nm半导体器件的方法，包括在其中限定有pMOS区域和nMOS区域的半导体衬底内形成绝缘膜。通过采用约0.7至0.75μm厚度的DUV光刻胶而形成第一掩模以遮蔽nMOS区域。离子注入到pMOS区域中以形成p型阱。通过采用约0.7至0.75μm厚度的DUV光刻胶而形成第二掩模以遮蔽pMOS区域。离子注入到nMOS区域中以形成n型阱。在半导体衬底之上形成栅氧化物膜和栅极。通过使用栅极作为掩模注入低浓度的杂质，可形成LDD区域。在栅极的两个侧壁上形成侧壁间隔垫。通过使用侧壁间隔垫作为掩模而注入高浓度杂质，形成源/漏区。

Description

形成半导体器件的方法
本申请要求享有(2006年8月31日递交)韩国专利申请No.10-2006-0083920在35 U.S.C.119下的优先权，在此引入其全部内容作为参考。
技术领域
本发明涉及形成半导体器件的方法，其中DUV PR厚度可用于具有亚90nm(sub-90nm)或更小器件的LDD注入光刻工艺(PEP)中。
背景技术
为了半导体器件小型化、大容量和高集成的目的，在半导体器件的晶体管、位线和电容器等形成之后，需要形成用于电连接元件的多层金属线的工序。晶体管包括具有短沟道长度的MOS晶体管。为了防止短沟道效应，可形成晶体管的源/漏区以具有轻掺杂漏极(LDD)区和重掺杂漏极(HDD)区。CMOS器件是指在一个半导体衬底上具有pMOS晶体管和nMOS晶体管两者的器件。
图1a和图1b所示为形成130nm半导体器件的现有方法的工艺横截面视图。参照图1a，在半导体衬底1上形成用于隔离元件的浅沟槽隔离(STI)区2。半导体衬底1涂覆有通过曝光和显影构图的光刻胶，形成第一掩模30，通过该第一掩模30而暴露pMOS区域。磷(P)或其它n型杂质注入到pMOS区域中以连续形成n型阱3和n型场截止(field stop)层4。在去除第一掩模30之后，如图1b所示，再次涂覆光刻胶。该光刻胶通过曝光和显影进行构图以形成第二掩模31，通过该第二掩模31而暴露nMOS区域。利用第二掩模31，P型杂质注入到暴露的nMOS区域，形成p型阱5和p型场截止层6。光刻胶可涂覆在第一掩模30和第二掩模31上至约0.85μm的厚度以在130nm器件中用作中红外(MUV)光刻胶(PR)。
在按照以上所述方法形成的现有130nm器件中，用作LDD注入掩模的光刻胶采用具有0.85μm厚度的MUVPR。当LDD注入的设计规则适于90nm工艺时，注入层的有源区域(暴露以执行实际注入的部分)相对于130nm器件显著减小。用于90nm和130nm工艺中的PR不能交替使用。以前，没有方案可以解决该问题。
发明内容
本发明的实施方式涉及形成半导体器件的技术并且更具体地涉及形成半导体器件的方法，其适于在具有90nm或更小特征的器件中使用用于轻掺杂漏极(LDD)注入的光刻胶。
本发明的实施方式涉及形成半导体器件的方法，在该半导体器件中深紫外(DUV)PR厚度可以用于具有90nm或更小特征的器件中的LDD注入光刻工艺(PEP)中。
本发明的实施方式涉及形成半导体器件的方法，在该半导体器件中约0.7至0.75μm厚度的DUVPR可以用于具有90nm或更小特征的器件中的LDD注入PEP中。
本发明的实施方式涉及形成半导体器件的方法，在该半导体器件中通过替代在二次离子质谱(SIMS)中的几种注入条件可使用具有适当厚度的光刻胶，以在具有90nm或更小特征的器件中应用DUV PR厚度到LDD注入PEP工艺。
本发明的实施方式涉及形成90nm半导体器件的方法，包括在其中限定pMOS区域和nMOS区域的半导体衬底内形成绝缘膜。通过使用约0.7至0.75μm厚度的DUV光刻胶，形成第一掩模以遮蔽nMOS区域。离子注入到pMOS区域中以形成p型阱。通过使用约0.7至0.75μm厚度的DUV光刻胶，形成第二掩模以遮蔽pMOS区域。离子注入到nMOS区域中以形成n型阱。栅氧化物膜和栅极在半导体衬底之上形成。通过采用栅极作为掩模，可注入低浓度杂质。形成LDD区域。在栅极的两个侧壁之上形成侧壁间隔垫。通过使用侧壁间隔垫作为掩模，注入高浓度杂质，形成源/漏区。
根据实施方式，随着器件尺寸变化到90nm，PR工艺也从MUV变化到DUV。为了遵循更小设计的规则，当转换PR到DUVPR(对于高集成的半导体器件，诸如64MB或更大的DRAM)时，选择适于亚90nm器件的PR厚度。
附图说明
图1a和图1b所示为形成130nm半导体器件的现有方法的工艺横截面视图；
图2a至图2d所示为根据实施方式形成90nm半导体器件的方法的工艺横截面视图；
图3示出了根据实施方式的注入分离的SIMS测试结果。
具体实施方式
如实施例图2a中所示，用于隔离元件的STI区域12形成在半导体衬底11中。光刻胶可涂覆在半导体衬底11上，并且随后可通过曝光和显影进行构图，形成第一掩模50，通过该第一掩模50暴露pMOS区域。磷(P)或其它n型杂质可注入到pMOS区域中以形成n型阱13和n型场截止层14。去除第一掩模50，以及如图2b所示，再次涂覆光刻胶。通过曝光和显影对光刻胶进行构图以形成第二掩模51，通过该第二掩模51暴露nMOS区域。通过采用第二掩模51，p型杂质可注入到暴露的nMOS区域中，形成p型阱15和p型场截止层16。光刻胶可涂覆在第一掩模50和第二掩模51上至约0.7到0.75μm厚度以用作90nm器件中的DUV PR。
可去除第二掩模51。如在实施例图2c中所示，可在半导体衬底11的所选区域之上形成栅氧化物膜17、栅极18和栅氮化物膜19。可通过全面离子注入(blanketion implant)方法在整个表面之上注入低浓度n型杂质，在nMOS晶体管区域中形成n型LDD区域21。
如实施例图2d中所示，在整个表面沉积氧化物膜之后，执行回蚀工艺(etch-back process)以在栅极18的侧壁上形成侧壁间隔垫22。可同时回蚀栅氮化物膜19和栅氧化物膜17。然后可将高浓度的p型杂质注入到pMOS晶体管区域的半导体衬底中以形成p型源/漏区23。高浓度的n型杂质可注入到nMOS晶体管区域的半导体衬底中以形成n型源/漏区24。
如上所述，可形成具有约0.7至0.75μm厚度的DUV PR。为了得到具有精确厚度的DUV PR，可执行数种注入条件。SIMS分析可用于确定是否已经达到PR厚度。在以下表格中列出了具有约0.7μm厚度的DUV PR的实施方式。
表1
  注入条件
  掺杂   能量   掺杂   倾斜/扭曲   7   8   9   10   11   12
LDDPR0.75μm   剂   量
  11B+   10 5.00E+15   0/0
  11B+   30   0/0
  49BF2+   50   0/0
  31P+   15   0/0
  31P+   30   0/0
  31P+   60   0/0
  SIMS   11B   11B   49BF2   31P   31P   31P
表1示出了评估LDD注入PR0.7μm的注入分离条件。实施例图3示出了根据实施方式的注入分离条件的SIMS测试结果。实施例图3示出了作为SIMS结果的PR厚度裕量(margin)取决于注入工艺中的变化。如果取代表格中的数种注入状态条件，如果LDD DUV约为0.7μmPR，则对于用作pMOS LDD并且约30KeV或更小的掺杂剂11B+可以作为阻挡层(barrier)(其中，PR最大损失(Top Loss)约250nm或更小)，以及对于用作nMOS LDD并且约30KeV或更小的掺杂剂31P+可以作为阻挡层(其中PR最大损失约300nm或更小)。
如上所述，根据实施方式，当器件朝向90nm工艺变化时，PR工艺也从MUV转向DUV。为了遵循更小的设计规则，当转换到DUV PR时，可通过数种注入条件和SIMS分析得到适于90nm器件的PR厚度。
根据实施方式，由于器件的尺寸变化到90nm，光刻胶工艺也可从MUV转换到DUV。为了遵循更小的设计规则，需要转换到DUV。可通过SIMS结果容易地确定适于LDD注入条件的PR厚度。因此，在显影工艺中可节省时间和成本。
对于本领域的普通技术人员来说对在此公开的实施方式进行各种修改和改进是显而易见的。因此，本发明旨在覆盖所有落入所附权利要求及其等效物范围内的对本发明进行的修改和改进。

Claims (20)

1.一种方法，包括：
在限定pMOS区域和nMOS区域的半导体衬底内形成绝缘膜；
通过使用约0.7至0.75μm厚度的深紫外光刻胶，形成第一掩模以遮蔽nMOS区域，以及注入离子到所述pMOS区域中以形成p型阱；
通过使用约0.7至0.75μm厚度的深紫外光刻胶，形成第二掩模以遮蔽pMOS区域，以及注入离子到所述nMOS区域中以形成n型阱。
2.根据权利要求1所述的方法，其特征在于，基于注入状态条件和二次离子质谱分析设置所述深紫外光刻胶的厚度。
3.根据权利要求2所述的方法，其特征在于，所述注入状态条件包括掺杂剂、能量、掺杂量和倾斜/扭曲变化信息的至少其中之一。
4.根据权利要求3所述的方法，其特征在于，所述第一掩模适于在关于掺杂剂11B+在约30KeV或更少能量下作为阻挡层。
5.根据权利要求3所述的方法，其特征在于，所述第一掩模用于pMOS轻掺杂漏极。
6.根据权利要求3所述的方法，其特征在于，所述光刻胶的最大损失量为约250nm或更少。
7.根据权利要求3所述的方法，其特征在于，所述第一掩模适于在关于掺杂剂31P+在约30KeV或更小能量下作为阻挡层。
8.根据权利要求3所述的方法，其特征在于，所述第一掩模用于nMOS轻掺杂漏极。
9.根据权利要求1所述的方法，其特征在于，所述器件方法遵循90nm设计规则以形成90nm半导体器件。
10.根据权利要求1所述的方法，其特征在于，包括在所述半导体衬底上形成栅氧化物膜和栅极。
11.根据权利要求10所述的方法，其特征在于，包括通过使用所述栅极作为掩模注入低浓度杂质，形成轻掺杂漏区。
12.根据权利要求11所述的方法，其特征在于，包括在所述栅极的两个侧壁之上形成侧壁间隔垫。
13.根据权利要求12所述的方法，其特征在于，包括通过使用所述侧壁间隔垫作为掩模注入高浓度杂质，形成源/漏区。
14.根据权利要求1所述的方法，其特征在于，包括在nMOS区域中形成p型场截止层。
15.根据权利要求1所述的方法，其特征在于，包括在pMOS区域中形成n型场截止层。
16.一种器件，包括：
在半导体衬底内形成的绝缘膜，其中在该半导体衬底中限定有pMOS区域和nMOS区域；
通过利用约0.7至0.75μm厚度的深紫外光刻胶，形成第一掩模以遮蔽所述nMOS区域之后，注入离子到所述pMOS区域中而形成的p型阱；
通过利用约0.7至0.75μm厚度的深紫外光刻胶，形成第二掩模以遮蔽所述pMOS区域之后，注入离子到所述nMOS区域中而形成的n型阱。
17.根据权利要求16所述的器件，其特征在于，包括在所述半导体衬底上形成的栅氧化物膜和栅极。
18.根据权利要求17所述的器件，其特征在于，包括轻掺杂漏区，该轻掺杂漏区通过采用所述栅极作为掩模注入低浓度杂质而形成。
19.根据权利要求18所述的器件，其特征在于，包括在所述栅极的两个侧壁之上形成的侧壁间隔垫。
20.根据权利要求19所述的器件，其特征在于，包括通过采用所述侧壁间隔垫作为掩模注入高浓度的杂质而形成的源/漏区。
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CN102904055A (zh) * 2011-07-29 2013-01-30 深圳光启高等理工研究院 一种超材料的微结构及其制备方法
CN104851801A (zh) * 2014-02-13 2015-08-19 北大方正集团有限公司 一种源漏轻掺杂方法和装置

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CN102074476B (zh) * 2009-11-20 2012-08-22 中芯国际集成电路制造(上海)有限公司 Nmos晶体管的形成方法
CN102904055A (zh) * 2011-07-29 2013-01-30 深圳光启高等理工研究院 一种超材料的微结构及其制备方法
CN102904055B (zh) * 2011-07-29 2017-11-28 深圳光启高等理工研究院 一种超材料的微结构及其制备方法
CN104851801A (zh) * 2014-02-13 2015-08-19 北大方正集团有限公司 一种源漏轻掺杂方法和装置

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