CN101131934A - Process for preparing vertical thin-film transistor - Google Patents
Process for preparing vertical thin-film transistor Download PDFInfo
- Publication number
- CN101131934A CN101131934A CNA2006101214709A CN200610121470A CN101131934A CN 101131934 A CN101131934 A CN 101131934A CN A2006101214709 A CNA2006101214709 A CN A2006101214709A CN 200610121470 A CN200610121470 A CN 200610121470A CN 101131934 A CN101131934 A CN 101131934A
- Authority
- CN
- China
- Prior art keywords
- aforementioned
- film transistor
- manufacture method
- source
- vertical thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention discloses a manufacturing method of vertical thin film transistor, using baffle light mask to make vertical structural elements. This method includes the following steps. First, a metal layer is made as a convex rib and the gate layer. Then, baffles light mask is installed on the gate layer. Baffle light mask is directly used as the mask to form the source layer, the organic semiconductor layer and the drain layer. In this way, the process could be simplified. Because it need not to use after lithography etching technology after the formation of organic semiconductor layer, so the damage of organic semiconductor layer can be avoided, and the vertical thin-film transistor components with good element characteristic could be obtained.
Description
Technical field
The present invention relates to a kind of semiconductor element, and particularly relate to a kind of manufacture method of vertical thin-film transistor.
Background technology
Along with the maturation of technology, lighter, thinner, portability, the display of deflection such as the attention that electronic paper has attracted numerous people, many major companies also add the research and development ranks one after another.OTFT (OTFT) is to utilize organic molecule material to develop the thin-film transistor that is fit to be applied to electronic product, its great advantage is that element can make at low temperatures, and the transistor unit characteristic still can be kept when panel bending, reach normal video picture mass effect, this application can be quickened the realization of bendable electronic product such as display.
The advantage of the OTFT of vertical stratification is that it can have higher mobility (Mobility), can be used for the element application than higher-frequency, and lower working bias voltage is arranged.Yet upward degree of difficulty is higher in making for the vertical stratification OTFT.Generally speaking, utilize traditional semiconductor technology to make the element of vertical stratification, need carry out multiple tracks coating process and Patternized technique, therefore need to make the multiaspect photomask.Not only on technology, make comparatively complexity, manufacturing cost is risen.And, all destroy to some extent through the organic semiconductor characteristic after the photoengraving carving technology, and make and can't obtain good element characteristic through the OTFT of the vertical stratification of method made thus.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of vertical thin-film transistor is being provided, and can simplify the OTFT technology of vertical stratification.
A further object of the present invention provides a kind of manufacture method of vertical thin-film transistor, the OTFT of can low temperature process making vertical stratification.
Another purpose of the present invention provides a kind of manufacture method of vertical thin-film transistor, makes OTFT have lower working bias voltage, and obtains preferred element characteristic.
The present invention proposes a kind of manufacture method of vertical thin-film transistor, comprises the following steps.At first, provide substrate, be formed with the grid layer of patterning in this substrate.Baffle light mask is set on grid layer, and this baffle light mask has the part substrate that opening exposes grid layer one side.Then, be mask with the baffle light mask, in the substrate that opening exposed, form first source, semiconductor layer and second source in regular turn.After removing baffle light mask, between stack layer that constitutes by first source, semiconductor layer and second source and grid layer, form gate dielectric layer.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the material of aforementioned first source and second source is an electric conducting material.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the formation method of aforementioned first source and aforementioned second source is for carrying out physical gas-phase deposition.Aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the material of aforesaid semiconductor layer is organic semiconducting materials or inorganic semiconductor material.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the aforesaid semiconductor layer is to be selected from one of them of N type, P type, micromolecule or high molecular organic semiconducting materials; And zinc oxide or inorganic semiconductor material through mixing.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the formation method of aforesaid semiconductor layer is for carrying out physical gas-phase deposition or spraying coating process.Aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the formation method of aforementioned gate dielectric layer comprises one of them of carrying out chemical vapour deposition technique, method for printing, method of spin coating, ink-jet method, infusion method or vapour deposition method.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, aforementioned substrates comprises silicon substrate, flexible base plate or glass substrate.
In the manufacture method of vertical OTFT of the present invention, owing to define grid layer earlier, and then make first source, semiconductor layer and second source with baffle light mask.Because grid layer has the function of fin (Rib), after baffle light mask is put, can accurately control the plated film area of first source, semiconductor layer and second source, can prevent its short circuit.
And, thickness by accurate control grid layer, can control the coating film area of first source, semiconductor layer and second source accurately, therefore after gate dielectric layer forms, not having short circuit condition between grid layer and the stack layer takes place, have simultaneously thin gate dielectric layer thickness again, thereby can reduce the operation bias voltage of element, also have bigger firing current simultaneously.
In addition, in the manufacture method of above-mentioned vertical OTFT, after forming semiconductor layer, do not use the photoengraving carving technology, therefore can avoid semiconductor layer to wreck yet, and can obtain good element characteristic.
The present invention proposes a kind of manufacture method of vertical thin-film transistor again, comprises the following steps.At first, provide substrate, and first baffle light mask is set in substrate, this first baffle light mask has first opening and exposes the part substrate.Then, be mask with first baffle light mask, in the substrate that first opening is exposed, form the stack layer that constitutes by first source, semiconductor layer and second source.After removing first baffle light mask, in substrate, form gate dielectric layer.Then, the second baffle photomask is set in substrate, this second baffle photomask has second opening and exposes stack layer one side.Then, be mask with the second baffle photomask, form grid layer in stack layer one side.Afterwards, remove the second baffle photomask.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the material of aforementioned first source and aforementioned second source is an electric conducting material.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the formation method of aforementioned first source and aforementioned second source is for carrying out physical gas-phase deposition.Aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the material of aforesaid semiconductor layer is organic semiconducting materials or inorganic semiconductor material.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the aforesaid semiconductor layer is to be selected from one of them of N type, P type, micromolecule or high molecular organic semiconducting materials; And zinc oxide or inorganic semiconductor material through mixing.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the formation method of aforesaid semiconductor layer is for carrying out physical gas-phase deposition or spraying coating process.Aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, the formation method of aforementioned gate dielectric layer comprises one of them of carrying out chemical vapour deposition technique, method for printing, method of spin coating, ink-jet method, infusion method or vapour deposition method.
According to the manufacture method of the described vertical thin-film transistor of the preferred embodiments of the present invention, aforementioned substrates comprises silicon substrate, flexible base plate or glass substrate.
In the manufacture method of the vertical OTFT of the present invention, owing to make first source, semiconductor layer and second source with first baffle light mask, therefore can accurately control the plated film area and the thickness of first source, semiconductor layer and second source.
And, after gate dielectric layer formation finishes, make grid layer with the second baffle photomask again.Therefore, do not have short circuit condition between grid layer and the stack layer and take place, have thin gate dielectric layer thickness simultaneously again, thereby can reduce the operation bias voltage of element, and make element have bigger firing current.
In addition, in the manufacture method of above-mentioned vertical OTFT, after forming semiconductor layer, do not use the photoengraving carving technology, therefore can avoid semiconductor layer to wreck yet, and can obtain good element characteristic.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A～Fig. 1 D is the local top view that illustrates the making flow process of the vertical OTFT in the first embodiment of the invention;
Fig. 2 A～Fig. 2 D is for illustrating among Figure 1A～Fig. 1 D the part sectioned view along A-A ' line respectively; And
Fig. 3 A～Fig. 3 D is the part sectioned view that illustrates the making flow process of the vertical OTFT in the second embodiment of the invention.
The simple symbol explanation
100,200: substrate
102,218: grid layer.
104,202,214: baffle light mask
106,203,216: opening
108,114,204,208: source
110: the gap
112,206: semiconductor layer
116,210: stack layer
118,212: gate dielectric layer
Embodiment
First embodiment
Figure 1A～Fig. 1 D is the local top view of making flow process that illustrates the vertical OTFT of first embodiment of the invention.Fig. 2 A～Fig. 2 D is for illustrating among Figure 1A～Fig. 1 D the part sectioned view along A-A ' line respectively.
Please refer to Figure 1A and Fig. 2 A, substrate 100 at first is provided.Plastic base, silicon substrate, flexible base plate or transparent glass substrate that this substrate 100 for example is a flexible.
Then, in substrate 100, form the grid layer 102 of patterning.The material of the grid layer 102 of patterning comprises conductor material, for example is metal (alloy of aluminium, copper, molybdenum, chromium or previous materials etc.) or doped polycrystalline silicon etc.The formation method of grid layer 102 for example is to adopt baffle light mask (not illustrating), cooperate physical gas-phase deposition and the grid layer 102 of patterning directly can be formed on the substrate 100, and physical gas-phase deposition for example is sputtering technology or evaporation process.In addition, the formation method of grid layer 102 also can be general photoengraving carving technology, that is be after forming one deck conductor material layer (not illustrating) on prior to substrate 100, the patterning photoresist layer (not illustrating) that utilization is formed on the conductor material layer cooperates etch process, with the grid layer 102 that defines patterning.The grid layer 102 of patterning for example is to arrange into strips, and can make the employed baffle light mask of technology (shadow mask) of follow-up formation source and semiconductor layer placed thereon.Certainly, in another preferred embodiment, the grid layer 102 of patterning also can be to be column, is arranged in the array kenel in substrate 100.
Please refer to Figure 1B and Fig. 2 B, on grid layer 102, place baffle light mask 104.Baffle light mask also can be arranged on the grid layer 102 in the mode of fitting.Baffle light mask 104 has the part substrate 100 that opening 106 exposes grid layer 102 1 sides.The material of baffle light mask 104 for example is stalloy, silicon wafer or acrylic plate or the like.
With baffle light mask 104 is mask, forms source 108 in the substrate 100 that opening 106 is exposed.Has gap 110 between source 108 and the grid layer 102.The material of source 108 comprises electric conducting material, for example is metal (alloy of aluminium, copper, molybdenum, chromium or previous materials etc.).The formation method of source 108 comprises carries out physical gas-phase deposition, and physical gas-phase deposition for example is sputtering technology or evaporation process.
Please refer to Fig. 1 C and Fig. 2 C, is mask with baffle light mask 104, forms semiconductor layer 112 on the source 108 that opening 106 is exposed.The material of semiconductor layer 112 comprises N type, P type, micromolecule or high molecular organic semiconducting materials, for example be pentacene (pentacene) or poly-(3-hexyl thiophene) (poly-(3-hexylthiophene), P3HT) etc.The material of semiconductor layer 112 also can be zinc oxide or the inorganic semiconductor material through mixing.The formation method of semiconductor layer 112 is for carrying out physical gas-phase deposition or spraying coating process.Physical gas-phase deposition comprises sputtering technology or evaporation process.
Then, be mask with baffle light mask 104, on the semiconductor layer 112 that opening 106 is exposed, form source 114.The material of source 114 comprises electric conducting material, for example is metal (alloy of aluminium, copper, molybdenum, chromium or previous materials etc.).The formation method of source 114 comprises carries out physical gas-phase deposition, and physical gas-phase deposition for example is sputtering technology or evaporation process.Source 108, semiconductor layer 112 constitute stack layer 116 with source 114.Between stack layer 116 and grid layer 102, has gap 110 equally.
Please refer to Fig. 1 D and Fig. 2 D, remove baffle light mask 104 after, gap between stack layer 116 and grid layer 102 110 forms gate dielectric layers 118.And gate dielectric layer 118 also covers the end face and the sidewall of substrate 100, grid layer 102 and stack layer 116 comprehensively and continuously.The material of gate dielectric layer 118 for example is silica, silicon nitride or organic dielectric layer.The formation method of gate dielectric layer 118 for example is to carry out chemical vapour deposition technique, method for printing, method of spin coating, ink-jet method, infusion method or vapour deposition method.
In the manufacture method of the vertical OTFT of the first embodiment of the present invention, because definition grid layer 102 and outside line (not illustrating) earlier, and then make source 108, semiconductor layer 112 and source 114 with baffle light mask.Because grid layer 102 has the function of fin (Rib), after baffle light mask is put, can accurately control the plated film area of source 108, semiconductor layer 112 and source 114, can prevent its short circuit.
And, thickness by accurate control grid layer 102, can control the coating film area of source 108, semiconductor layer 112 and source 114 accurately, therefore after gate dielectric layer 118 forms, not having short circuit condition between grid layer 102 and the stack layer 116 takes place, have simultaneously thin gate dielectric layer 118 thickness again, thereby can reduce the operation bias voltage of element, and make element have bigger firing current.
And, in the manufacture method of above-mentioned vertical OTFT, after forming semiconductor layer, do not use the photoengraving carving technology, therefore also can avoid semiconductor layer to wreck, and can obtain good element characteristic.
Second embodiment
Fig. 3 A～Fig. 3 D is the part sectioned view that illustrates the making flow process of the vertical OTFT in the second embodiment of the invention.
Please refer to Fig. 3 A, substrate 200 at first is provided.Plastic base, silicon substrate, flexible base plate or transparent glass substrate that this substrate 200 for example is a flexible.
Then, baffle light mask 202 is set in substrate 200.Baffle light mask 202 has opening 203 expose portion substrates 200.The material of baffle light mask 202 for example is stalloy, silicon wafer or acrylic plate or the like.
With baffle light mask 202 is mask, forms source 204 in the substrate 100 that opening 203 is exposed.The material of source 204 comprises electric conducting material, for example is metal (alloy of aluminium, copper, molybdenum, chromium or previous materials etc.).The formation method of source 204 comprises carries out physical gas-phase deposition, and physical gas-phase deposition for example is sputtering technology or evaporation process.
Please refer to Fig. 3 B, is mask with baffle light mask 202, forms semiconductor layer 206 on the source 204 that opening 202 is exposed.The material of semiconductor layer 206 comprises N type, P type, micromolecule or high molecular organic semiconducting materials, for example be pentacene (pentacene) or poly-(3-hexyl thiophene) (poly-(3-hexylthiophene), P3HT) etc.The material of semiconductor layer 206 also can be zinc oxide or the inorganic semiconductor material through mixing.The formation method of semiconductor layer 206 is for carrying out physical gas-phase deposition or spraying coating process.Physical gas-phase deposition comprises sputtering technology or evaporation process.
Then, be mask with baffle light mask 202, on the semiconductor layer 206 that opening 203 is exposed, form source 208.The material of source 208 comprises electric conducting material, for example is metal (alloy of aluminium, copper, molybdenum, chromium or previous materials etc.).The formation method of source 208 comprises carries out physical gas-phase deposition, and physical gas-phase deposition for example is sputtering technology or evaporation process.Source 208, semiconductor layer 206 constitute stack layer 210 with source 204.
Please refer to Fig. 3 C, remove baffle light mask 202 after, in substrate 200, form gate dielectric layer 212.And gate dielectric layer 212 also covers the end face and the sidewall of stack layer 210 comprehensively and continuously.The material of gate dielectric layer 118 for example is silica, silicon nitride or organic dielectric layer.The formation method of gate dielectric layer 118 for example is to carry out chemical vapour deposition technique, method for printing, method of spin coating, ink-jet method, infusion method or vapour deposition method.
Please refer to Fig. 3 D, baffle light mask 214 is set on stack layer 210.Baffle light mask 214 has the side that opening 216 exposes stack layer 210.With baffle light mask 214 is mask, in the side formation grid layer 218 of stack layer 210.The material of grid layer 218 comprises conductor material, for example is metal (alloy of aluminium, copper, molybdenum, chromium or previous materials etc.).The formation method of grid layer 218 comprises carries out physical gas-phase deposition, and physical gas-phase deposition for example is sputtering technology or evaporation process.Afterwards, remove baffle light mask 214 again.
In the manufacture method of the vertical OTFT of the second embodiment of the present invention, owing to make source 204, semiconductor layer 206 and source 208 with baffle light mask 202, therefore can accurately control the plated film area and the thickness of source 204, semiconductor layer 206 and source 208.
And, after gate dielectric layer 212 formation finish, make grid layers 218 with baffle light mask 214 again.Therefore, do not have short circuit condition between grid layer 218 and the stack layer 210 and take place, have thin gate dielectric layer 212 thickness simultaneously again, thereby can reduce the operation bias voltage of element, and make element have bigger firing current.
In addition, in the manufacture method of above-mentioned vertical OTFT, after forming semiconductor layer, do not use the photoengraving carving technology, therefore can avoid semiconductor layer to wreck yet, and can obtain good element characteristic.
In sum, the manufacture method of vertical OTFT of the present invention is owing to utilize single photo mask definition drain electrode, semiconductor layer and source electrode.Except can technology oversimplifying, it can be applied to component integration and large tracts of landization simultaneously, can be used for display.And the OTFT of can low temperature process making vertical stratification makes OTFT have lower working bias voltage, and obtains preferred element characteristic.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (20)
1. the manufacture method of a vertical thin-film transistor comprises:
Substrate is provided, has been formed with the grid layer of patterning on the aforementioned substrates;
On aforementioned grid layer baffle light mask is set, the said baffle photomask has the part aforementioned substrates that opening exposes aforementioned grid layer one side;
With aforementioned baffle light mask is mask, forms first source, semiconductor layer and second source on the aforementioned substrates that aforementioned opening exposed in regular turn;
Remove the said baffle photomask; And
Between stack layer that constitutes by aforementioned first source, aforesaid semiconductor layer and aforementioned second source and aforementioned grid layer, form gate dielectric layer.
2. the manufacture method of vertical thin-film transistor as claimed in claim 1, the material of wherein aforementioned first source and aforementioned second source comprises electric conducting material.
3. the manufacture method of vertical thin-film transistor as claimed in claim 2, the formation method of wherein aforementioned first source and aforementioned second source comprises carries out physical gas-phase deposition.
4. the manufacture method of vertical thin-film transistor as claimed in claim 1, wherein aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
5. the manufacture method of vertical thin-film transistor as claimed in claim 1, wherein the material of aforesaid semiconductor layer comprises organic semiconducting materials or inorganic semiconductor material.
6. the manufacture method of vertical thin-film transistor as claimed in claim 1, wherein the aforesaid semiconductor layer is for being selected from N type, P type, micromolecule or high molecular organic semiconducting materials; And one of them of zinc oxide or inorganic semiconductor material through mixing.
7. the manufacture method of vertical thin-film transistor as claimed in claim 5, wherein the formation method of aforesaid semiconductor layer is for carrying out physical gas-phase deposition or spraying coating process.
8. the manufacture method of vertical thin-film transistor as claimed in claim 7, wherein aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
9. the manufacture method of vertical thin-film transistor as claimed in claim 1, wherein the formation method of aforementioned gate dielectric layer comprises one of them of carrying out chemical vapour deposition technique, method for printing, method of spin coating, ink-jet method, infusion method or vapour deposition method.
10. the manufacture method of vertical thin-film transistor as claimed in claim 1, wherein aforementioned substrates comprises silicon substrate, flexible base plate or glass substrate.
11. the manufacture method of a vertical thin-film transistor comprises:
Substrate is provided;
First baffle light mask is set on aforementioned substrates, and aforementioned first baffle light mask has first opening and exposes the part aforementioned substrates;
With aforementioned first baffle light mask is mask, forms the stack layer that is made of first source, semiconductor layer and second source on the aforementioned substrates that aforementioned first opening is exposed;
Remove aforementioned first baffle light mask;
On aforementioned substrates, form gate dielectric layer;
The second baffle photomask is set on aforementioned substrates, and aforementioned second baffle photomask has second opening and exposes aforementioned stack layer one side;
With aforementioned second baffle photomask is mask, forms grid layer in aforementioned stack layer one side; And
Remove aforementioned second baffle photomask.
12. the manufacture method of vertical thin-film transistor as claimed in claim 11, the material of wherein aforementioned first source and aforementioned second source comprises electric conducting material.
13. comprising, the manufacture method of vertical thin-film transistor as claimed in claim 12, the formation method of wherein aforementioned first source and aforementioned second source carry out physical gas-phase deposition.
14. the manufacture method of vertical thin-film transistor as claimed in claim 11, wherein aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
15. the manufacture method of vertical thin-film transistor as claimed in claim 11, wherein the material of aforesaid semiconductor layer comprises organic semiconducting materials or inorganic semiconductor material.
16. the manufacture method of vertical thin-film transistor as claimed in claim 11, wherein the aforesaid semiconductor layer is to be selected from one of them of N type, P type, micromolecule or high molecular organic semiconducting materials; And zinc oxide or inorganic semiconductor material through mixing.
17. the manufacture method of vertical thin-film transistor as claimed in claim 15, wherein the formation method of aforesaid semiconductor layer comprises and carries out physical gas-phase deposition or spraying coating process.
18. the manufacture method of vertical thin-film transistor as claimed in claim 17, wherein aforementioned physical gas-phase deposition comprises sputtering technology or evaporation process.
19. the manufacture method of vertical thin-film transistor as claimed in claim 11, wherein the formation method of aforementioned gate dielectric layer comprises one of them of carrying out chemical vapour deposition technique, method for printing, method of spin coating, ink-jet method, infusion method or vapour deposition method.
20. the manufacture method of vertical thin-film transistor as claimed in claim 11, wherein aforementioned substrates comprises silicon substrate, flexible base plate or glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101214709A CN100505186C (en) | 2006-08-24 | 2006-08-24 | Process for preparing vertical thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101214709A CN100505186C (en) | 2006-08-24 | 2006-08-24 | Process for preparing vertical thin-film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101131934A true CN101131934A (en) | 2008-02-27 |
| CN100505186C CN100505186C (en) | 2009-06-24 |
Family
ID=39129133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101214709A Expired - Fee Related CN100505186C (en) | 2006-08-24 | 2006-08-24 | Process for preparing vertical thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100505186C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655403A (en) * | 2014-12-03 | 2016-06-08 | 业鑫科技顾问股份有限公司 | Vertical type film transistor and manufacture method thereof |
| CN108281452A (en) * | 2017-02-03 | 2018-07-13 | 思特威电子科技（美国）有限公司 | Pixel unit and forming method and imaging system components |
| WO2019114112A1 (en) * | 2017-12-12 | 2019-06-20 | 深圳市华星光电技术有限公司 | Method for preparing display panel |
-
2006
- 2006-08-24 CN CNB2006101214709A patent/CN100505186C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655403A (en) * | 2014-12-03 | 2016-06-08 | 业鑫科技顾问股份有限公司 | Vertical type film transistor and manufacture method thereof |
| CN105655403B (en) * | 2014-12-03 | 2019-01-25 | 鸿富锦精密工业（深圳）有限公司 | A kind of vertical-type thin film transistor and its manufacturing method |
| CN108281452A (en) * | 2017-02-03 | 2018-07-13 | 思特威电子科技（美国）有限公司 | Pixel unit and forming method and imaging system components |
| CN108281452B (en) * | 2017-02-03 | 2022-04-15 | 思特威(上海)电子科技股份有限公司 | Pixel unit, forming method and imaging system assembly |
| WO2019114112A1 (en) * | 2017-12-12 | 2019-06-20 | 深圳市华星光电技术有限公司 | Method for preparing display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100505186C (en) | 2009-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7588971B2 (en) | Method of fabricating vertical thin film transistor | |
| US7198885B2 (en) | Circuit fabrication method | |
| CN101488459B (en) | Production method for self-aligned metallic oxide thin-film transistor | |
| CN102709234B (en) | Thin-film transistor array base-plate and manufacture method thereof and electronic device | |
| KR20070103050A (en) | Flexible active matrix display backplane and method | |
| CN103119699B (en) | Thin film transistor (TFT) and manufacture method thereof and image display device | |
| US9219238B2 (en) | Organic thin film transistor array substrate and method for manufacturing the same, and display device | |
| US20170110587A1 (en) | Array substrate and manufacturing method thereof, display panel, display device | |
| CN112435962B (en) | Display substrate preparation method, display substrate and display device | |
| US20120138909A1 (en) | Stacked structure and organic thin film transistor and array having the same | |
| US20060157690A1 (en) | Organic insulator, organic thin film transistor array panel including organic insulator, and manufacturing method therefor | |
| US7968368B2 (en) | Method of manufacturing a field effect transistor having an oxide semiconductor | |
| CN101419944B (en) | Flat display and manufacturing method thereof | |
| CN100505186C (en) | Process for preparing vertical thin-film transistor | |
| CN101625977B (en) | Method for manufacturing film transistor | |
| CN104409635A (en) | Organic thin film transistor and manufacturing method thereof, array substrate, and display unit | |
| CN100380634C (en) | Method for making picture element structure | |
| CN102437195A (en) | Thin film transistor and method of manufacturing the same | |
| JP5617214B2 (en) | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE | |
| WO2013174105A1 (en) | Array substrate, manufacturing method thereof, display panel, and display device | |
| US7808569B2 (en) | Method for manufacturing pixel structure | |
| CN100362413C (en) | Method for making electronic apparatus | |
| CN102104112A (en) | Preparation method of top contact structure organic field effect transistor | |
| CN100464404C (en) | Making method of pixel structure | |
| JP2006245372A (en) | Manufacturing method of thin film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090624 Termination date: 20170824 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |