CN101131515A - Thin-film transistor array substrate and LCD device - Google Patents
Thin-film transistor array substrate and LCD device Download PDFInfo
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- CN101131515A CN101131515A CNA2006101261019A CN200610126101A CN101131515A CN 101131515 A CN101131515 A CN 101131515A CN A2006101261019 A CNA2006101261019 A CN A2006101261019A CN 200610126101 A CN200610126101 A CN 200610126101A CN 101131515 A CN101131515 A CN 101131515A
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- film transistor
- contact hole
- line component
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- liquid crystal
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Abstract
A kind of film transistor array base applied to the liquid display device, has at least two memory capacitance wire in electric connection. The memory capacitance wire which uses the electric connection of the electric conduction contact hole and electric conduction belongs to the twain adjacent image element of the scanning beam side, it can eliminate the landscape orientation string shadow of the liquid display device.
Description
Technical field
The relevant a kind of thin-film transistor array base-plate of the present invention, the thin-film transistor array base-plate that particularly provides a kind of liquid crystal indicator and utilized.
Background technology
In recent years, the display of portable type communication apparatus and PC is essentially liquid crystal panel.For the display of the next century, liquid crystal panel, organic electroluminescence panel (organic electroluminescentpanel) are all attracted attention with inorganic electroluminescence panel (inorganic electroluminescence panel).The panel of the above-mentioned type generally all has the pixel that is arranged in matrix, and by two kinds of drive systems: initiatively or the passive-matrix drive systems.
One of important problem of relevant aforementioned display device is level or the generation of shadow (crosstalk) of vertically going here and there.String shadow phenomenon is in one when for example a static pattern of form shows, the phenomenon of brightness disproportionation is arranged on specific direction.Brightness disproportionation descends relevant with electrode wires voltage.For instance, the shadow of laterally going here and there betides on the LCD of bright dark fringe background and black rectangle pattern usually, and it is derived from the decline of common electrode current potential.Therefore, how reducing the string shadow is one of important problem of liquid crystal indicator with the taste (grade) that increases display panel.
Summary of the invention
In order to solve the above problems, one embodiment of the invention provide a kind of pel array of liquid crystal indicator.Utilize the design that electrically connects the capacitor storage beam that is positioned at neighbor, the voltage that can eliminate common electrode descends.
The purpose of this invention is to provide a kind of thin-film transistor array base-plate, be applied on the liquid crystal indicator.Have the capacitor storage beam of electric connection with the sweep trace adjacent pixels, and it is distributed on the whole front panel at random mode.
Another object of the present invention provides a kind of liquid crystal indicator, and it has capacitor storage beam design of electric connection, and this capacitor storage beam design distributes in the mode of a pattern distribution, so can keep the aperture opening ratio of liquid crystal indicator.
Another purpose of the present invention provides a kind of liquid crystal indicator that improves contrast, and a conductive layer partly covers a capacitor storage beam, so as to preventing light leak.
For achieving the above object, the invention provides a kind of thin film transistor (TFT) array, comprise a plurality of data lines and intersect to define a plurality of pixel regions with a plurality of sweep traces.A plurality of capacitor storage beam are arranged in the pixel region, and wherein each capacitor storage beam comprises the direction setting of one first its parallel scan lines of line component, and the direction setting of one second line component panel data line.A plurality of pixel electrode correspondences are arranged at pixel region, and electrically connect corresponding thin film transistor (TFT).A plurality of contact holes, each contact hole is arranged at the end points of second line component, and a conductive layer connects second line component of two adjacent pixels, and electrically connects by the contact hole and second line component.
Description of drawings
Figure 1 shows that perspective diagram according to a substrate embodiment of the present invention.
Figure 2 shows that the diagrammatic cross-section according to a flat-panel screens embodiment of the present invention, this flat-panel screens has along the thin-film transistor array base-plate of the AA ' hatching line of Fig. 1.
Embodiment
Fig. 1 is the front schematic view according to one embodiment of the invention.One thin-film transistor array base-plate (thinfilm transistor array substrate) comprises a plurality of sweep traces 12, data line 14, thin film transistor (TFT) 16, capacitor storage beam 18, pixel electrode 20 and a conductive layer 22.Sweep trace 12 also can be described as gate line (gate line), and it is on a direction, and for example figure goes up on the X-direction and arranges.Data line 14 also can be described as source electrode line (source line), goes up on the Y direction in figure and arranges in the mode of crossing over sweep trace 12, and wherein a pixel region is defined by two adjacent sweep traces 12 and two adjacent data lines 14.Thin film transistor (TFT) 16 is positioned on the position that sweep trace 12 and data line 14 intersect, and each thin film transistor (TFT) 16 corresponding each pixel region, and each pixel electrode 20 is arranged in each corresponding pixel region, and electrically connects corresponding thin film transistor (TFT) 16.
Secondly, capacitor storage beam 18 forms in the mode of extending on the pixel region of a plurality of sweep traces 12.In an embodiment, each capacitor storage beam 18 comprises one first line component 181 (first linecomponent) and forms in the upwardly extending mode in the side of sweep trace 12, and one second line component 182 is along the direction of data line 14 and be arranged in each pixel region.In this embodiment, first line component 181 and two second line components 182 are formed corresponding each pixel region in unit of capacitor storage beam 18.Moreover an extension 183 is positioned at the end of second line component 182, and this second line component 182 is than the thin film transistor (TFT) 16 of another second line component 182 away from correspondence.
According to spirit of the present invention, conduction contact hole 184 is positioned at the extension 183 on part second line component 182.In present embodiment, two conduction contact holes 184 can be distributed in on two the second adjacent line components 182 of one scan line 12.Moreover, for thin-film transistor array base-plate, the conduction contact hole 184 can with at random or the mode of design distribute.For instance, if when the several regions of a LCD can be observed significantly diatropism string shadow (lateral crosstalk) phenomenon, can design conduction contact hole 184 and be distributed in those specific zones.In addition, when observing tangible diatropism string shadow, also can mode at random distribute conduction contact hole 184 to guarantee to show taste (display grade).Moreover the distribution of conduction contact hole 184 can be considered brightness and is unlikely to be subjected to tangible influence to guarantee brightness, and for example brightness reduces by 0.7% o'clock human eye and can not experience its difference.
In present embodiment, the function of conduction contact hole 184 is to match with the design of conductive layer 22.For for adjacent wantonly two pixel regions of sweep trace 12, described conductive layer 22 is arranged on two second line components 182 with corresponding conduction contact hole 184, so as to electrically connecting two second line components 182.According to above-mentioned, described conductive layer 22 is also crossed over the sweep trace 12 between the conduction contact hole 184, promptly crosses over the sweep trace 12 between the two adjacent pixels.Though, transmit with transmitting for the waveform of sweep trace 12 and can't produce visible influence because that the leap of conductive layer 22 may cause the load of sweep trace 12 to increase is about 5%.Moreover one of feature of the present invention is that pixel electrode 20 and part second line component 182 are overlapping, so as to increasing the contrast of LCD.According to above-mentioned, the design of pixel electrode 20 can be applied to the display base plate of different types, twisted-nematic (Twisted Nematic for example, TN) type, wide viewing angle multi-domain vertical alignment (Multi-domain Vertically Align, MVA) type or wide viewing angle multiple domain homogeneity alignment-type (Multi-domain Homeotropic Align, MHA).
Fig. 2 is according to one embodiment of the invention, illustrates that a LCD has along the diagrammatic cross-section of the thin-film transistor array base-plate of the AA ' of Fig. 1.One LCD comprises the thin-film transistor array base-plate of a colored optical filtering substrates structure 26 and subtend, and a liquid crystal layer 28 falls between.In an embodiment, colored optical filtering substrates structure 26 can comprise a chromatic filter layer 262, a protective seam 263, a common electrode 264 and a polyimide (polyimide) alignment film 265 and be formed on the glass substrate 261.On the other hand, for thin-film transistor array base-plate, a first metal layer is formed on the glass substrate 101, and then carries out the pattern transfer to form sweep trace 12 and capacitor storage beam.Afterwards, an insulation course 103 is formed on sweep trace 12 and the capacitor storage beam.According to spirit of the present invention, insulation course 103 is transferred with the contact hole on second line component that forms capacitor storage beam through pattern.One conductive layer is inserted in the contact hole forming conduction contact hole 184, and conductive layer is covered on the insulation course 103.Carry out lithography step to form the pixel electrode 20 and the conductive layer 22 of patterning for conductive layer.According to above-mentioned, conductive layer 22 is crossed over sweep trace 12 to electrically connect two capacitor storage beam.
Above-described embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes person skilled in the art scholar can understand content of the present invention and is implementing according to this, when not limited claim of the present invention, every variation that is equal to or modification of doing according to disclosed spirit must be encompassed in the application's the claim scope.
Claims (16)
1. thin-film transistor array base-plate comprises:
A plurality of sweep traces;
A plurality of data lines intersect to define a plurality of pixel regions with described a plurality of sweep traces;
A plurality of thin film transistor (TFT)s are positioned on the position that described a plurality of sweep trace and described a plurality of data lines intersect;
A plurality of capacitor storage beam are to be arranged in each described pixel region, and wherein, each described capacitor storage beam comprises one first line component, and the direction setting of its parallel described sweep trace, and one second line component are the direction settings of parallel described data line;
A plurality of pixel electrodes, its correspondence is arranged at described pixel region, and electrically connects corresponding described thin film transistor (TFT);
A plurality of contact holes, each described contact hole are to be arranged on the end points of described second line component; And
One conductive layer, it connects described second line component of two adjacent pixels, and electrically connects by described contact hole and described second line component.
2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that described a plurality of conduction contact hole is distributed in described a plurality of pixel region at random mode.
3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that described a plurality of conduction contact hole is distributed in described a plurality of pixel region in a kind of mode of pattern.
4. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that for arbitrary described second line component with described corresponding conduction contact hole an extension is positioned at the terminal of described second line component and in order to the conduction contact hole of ccontaining described correspondence.
5. thin-film transistor array base-plate as claimed in claim 1 is characterized in that also crossing over described sweep trace between the described two adjacent pixels at the described conductive layer of described second line component with described corresponding conduction contact hole.
6. thin-film transistor array base-plate as claimed in claim 1 is characterized in that two described second line components are oppositely arranged, and is arranged in each described pixel region.
7. thin-film transistor array base-plate as claimed in claim 6 is characterized in that for each described pixel region, and described second line component with described corresponding conduction contact hole is away from described corresponding thin film transistor (TFT).
8. thin-film transistor array base-plate as claimed in claim 6, it is characterized in that described pixel electrode also between described two second line components and with the part described two second line components overlapping.
9. liquid crystal indicator comprises:
One first board structure;
One second board structure is in the face of described first board structure, and wherein said second board structure comprises:
A plurality of sweep traces;
A plurality of data lines intersect to define a plurality of pixel regions with described a plurality of sweep traces;
A plurality of capacitor storage beam, it is arranged in each described pixel region, and wherein, each described capacitor storage beam comprises one first line component, the direction setting of its parallel described sweep trace, and one second line component, the direction setting of its parallel described data line;
A plurality of pixel electrodes, its correspondence is arranged at described pixel region, and electrically connects corresponding described thin film transistor (TFT);
A plurality of conduction contact holes, each described contact hole are to be arranged on the end points of described second line component; And
One conductive layer, it connects described second line component of two adjacent pixels, and electrically connects by described contact hole and described second line component; And
One liquid crystal layer is between described first board structure and described second board structure.
10. liquid crystal indicator as claimed in claim 9 is characterized in that described second board structure also comprises a plurality of thin film transistor (TFT)s and is positioned on the position that described a plurality of sweep trace and described a plurality of data lines intersect.
11. liquid crystal indicator as claimed in claim 9 is characterized in that described conduction contact hole is distributed in described a plurality of pixel region at random mode.
12. liquid crystal indicator as claimed in claim 9 is characterized in that described a plurality of conduction contact hole is distributed in described a plurality of pixel region in a kind of mode of pattern.
13. liquid crystal indicator as claimed in claim 9 is characterized in that also crossing over described sweep trace between the described two adjacent pixels at the described conductive layer of described second line component with described corresponding conduction contact hole.
14. liquid crystal indicator as claimed in claim 9 is characterized in that described first board structure comprises:
One glass substrate;
One chromatic filter layer is positioned at described glass substrate;
One common electrode is positioned on the described chromatic filter layer; And
One alignment film is positioned on the described common electrode.
15. liquid crystal indicator as claimed in claim 9 is characterized in that described a plurality of sweep trace and described a plurality of capacitor storage beam form with the same metal layer on a glass substrate.
16. liquid crystal indicator as claimed in claim 9 is characterized in that described pixel electrode and described conductive layer are to form with an indium tin oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101261019A CN101131515B (en) | 2006-08-21 | 2006-08-21 | Thin-film transistor array substrate and LCD device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101261019A CN101131515B (en) | 2006-08-21 | 2006-08-21 | Thin-film transistor array substrate and LCD device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101131515A true CN101131515A (en) | 2008-02-27 |
| CN101131515B CN101131515B (en) | 2010-06-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101261019A Expired - Fee Related CN101131515B (en) | 2006-08-21 | 2006-08-21 | Thin-film transistor array substrate and LCD device |
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| CN (1) | CN101131515B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887198A (en) * | 2010-07-07 | 2010-11-17 | 友达光电股份有限公司 | Pixel array |
| CN101017302B (en) * | 2006-02-06 | 2010-12-15 | 三星电子株式会社 | Liquid crystal display and manufacturing method thereof |
| US8953111B2 (en) | 2010-06-29 | 2015-02-10 | Au Optronics Corporation | Pixel array |
| CN109240011A (en) * | 2018-11-16 | 2019-01-18 | 成都中电熊猫显示科技有限公司 | array substrate and liquid crystal display panel |
| CN109254464A (en) * | 2018-11-16 | 2019-01-22 | 成都中电熊猫显示科技有限公司 | array substrate and liquid crystal display panel |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5367179A (en) * | 1990-04-25 | 1994-11-22 | Casio Computer Co., Ltd. | Thin-film transistor having electrodes made of aluminum, and an active matrix panel using same |
| JPH10142633A (en) * | 1996-11-15 | 1998-05-29 | Mitsubishi Electric Corp | Thin film transistor integrated device, manufacture thereof, and liquid crystal display device |
| CN1195243C (en) * | 1999-09-30 | 2005-03-30 | 三星电子株式会社 | Film transistor array panel for liquid crystal display and its producing method |
| KR100539833B1 (en) * | 2002-10-21 | 2005-12-28 | 엘지.필립스 엘시디 주식회사 | array circuit board of LCD and fabrication method of thereof |
| KR100900541B1 (en) * | 2002-11-14 | 2009-06-02 | 삼성전자주식회사 | Thin film transistor array panel for a liquid crystal display |
-
2006
- 2006-08-21 CN CN2006101261019A patent/CN101131515B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017302B (en) * | 2006-02-06 | 2010-12-15 | 三星电子株式会社 | Liquid crystal display and manufacturing method thereof |
| US8953111B2 (en) | 2010-06-29 | 2015-02-10 | Au Optronics Corporation | Pixel array |
| CN101887198A (en) * | 2010-07-07 | 2010-11-17 | 友达光电股份有限公司 | Pixel array |
| CN101887198B (en) * | 2010-07-07 | 2013-07-03 | 友达光电股份有限公司 | Pixel array |
| CN109240011A (en) * | 2018-11-16 | 2019-01-18 | 成都中电熊猫显示科技有限公司 | array substrate and liquid crystal display panel |
| CN109254464A (en) * | 2018-11-16 | 2019-01-22 | 成都中电熊猫显示科技有限公司 | array substrate and liquid crystal display panel |
| CN109240011B (en) * | 2018-11-16 | 2019-08-13 | 成都中电熊猫显示科技有限公司 | Array substrate and liquid crystal display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101131515B (en) | 2010-06-16 |
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Granted publication date: 20100616 Termination date: 20200821 |