CN101131515B - Thin film transistor array substrate and liquid crystal display device - Google Patents

Abstract

A thin film transistor array substrate for a liquid crystal display device has at least two storage capacitor lines electrically connected to each other. The storage capacitor lines electrically connected to the conductive layer by a conductive contact hole belong to two adjacent pixels on both sides of a scanning line, which can eliminate the lateral crosstalk of the liquid crystal display device.

Description

Thin film transistor array substrate and liquid crystal display device

technical field

The present invention relates to a thin film transistor array substrate, and in particular provides a thin film transistor array substrate used in a liquid crystal display device.

Background technique

In recent years, the displays of portable communication devices and personal computers are basically liquid crystal panels. For displays in the next century, liquid crystal panels, organic electroluminescence panels and inorganic electroluminescence panels are all attracting attention. Panels of the above types generally have pixels arranged in a matrix and are driven by two types of drive systems: active or passive matrix drive systems.

One of the important issues related to the above displays is the occurrence of horizontal or vertical crosstalk. Cross-shadowing is a phenomenon in which there is uneven brightness in a specific direction when a static pattern such as a window is displayed. The uneven brightness is related to the voltage drop of the electrode line. For example, horizontal cross-image usually occurs on a liquid crystal display with a bright and dark striped background and a black rectangle pattern, which is caused by a drop in the potential of the common electrode. Therefore, how to reduce the cross-image to increase the grade of the display panel is one of the important issues of the liquid crystal display device.

Contents of the invention

In order to solve the above problems, an embodiment of the present invention provides a pixel array of a liquid crystal display device. The voltage drop of the common electrode can be eliminated by using the design of electrically connecting the storage capacitor lines located in adjacent pixels.

The object of the present invention is to provide a thin film transistor array substrate applied to a liquid crystal display device. Pixels adjacent to the scan line have electrically connected storage capacitor lines, which are randomly distributed on the entire panel.

Another object of the present invention is to provide a liquid crystal display device having electrically connected storage capacitor lines, and the storage capacitor lines are distributed in a pattern distribution, so that the aperture ratio of the liquid crystal display device can be maintained.

Another object of the present invention is to provide a liquid crystal display device with improved contrast. A conductive layer partially covers a storage capacitor line to prevent light leakage.

To achieve the above object, the present invention provides a thin film transistor array, which includes a plurality of data lines intersecting with a plurality of scan lines to define a plurality of pixel regions. A plurality of storage capacitor lines are arranged in the pixel area, wherein each storage capacitor line includes a first line component arranged parallel to the direction of the scan line, and a second line component arranged parallel to the direction of the data line. A plurality of pixel electrodes are correspondingly arranged in the pixel area, and are electrically connected to corresponding thin film transistors. A plurality of contact holes, each contact hole is arranged at the terminal of the second line component, and a conductive layer connects the second line component of two adjacent pixels, and is electrically connected with the second line component through the contact hole. The storage capacitor line and the plurality of scan lines are of the same film layer, and the storage capacitor line and the pixel electrode are of different film layers.

Description of drawings

FIG. 1 is a schematic perspective view of an embodiment of a substrate according to the present invention.

FIG. 2 is a schematic cross-sectional view of an embodiment of a flat-panel display according to the present invention. The flat-panel display has a thin film transistor array substrate along line AA' in FIG. 1 .

Detailed ways

FIG. 1 is a schematic front view of an embodiment according to the present invention. A thin film transistor array substrate includes a plurality of scan lines 12 , data lines 14 , thin film transistors 16 , storage capacitor lines 18 , pixel electrodes 20 and a conductive layer 22 . The scan lines 12, also called gate lines, are arranged in one direction, such as the X-axis direction in the figure. Data lines 14, also called source lines (source lines), are arranged across the scan lines 12 in the direction of the Y-axis in the figure, wherein one pixel area consists of two adjacent scan lines 12 and two adjacent data lines. Defined by line 14. The thin film transistor 16 is located at the intersection of the scanning line 12 and the data line 14, and each thin film transistor 16 corresponds to each pixel area, and each pixel electrode 20 is arranged in each corresponding pixel area, and is electrically connected to the corresponding thin film Transistor 16.

Secondly, the storage capacitor line 18 is formed to extend along the pixel area of the plurality of scan lines 12 . In one embodiment, each storage capacitor line 18 includes a first line component 181 (first line component) formed in a manner extending in the direction of the scan line 12, and a second line component 182 positioned along the direction of the data line 14 in each pixel area. In this embodiment, the first line element 181 and the two second line elements 182 form a unit of the storage capacitor line 18 corresponding to each pixel area. Furthermore, an extension portion 183 is located at the end of the second wire component 182 , and the second wire component 182 is farther away from the corresponding thin film transistor 16 than the other second wire component 182 .

According to the spirit of the present invention, the conductive contact hole 184 is located on the extension portion 183 of part of the second wire assembly 182 . In this embodiment, two conductive contact holes 184 may be distributed on two second line elements 182 adjacent to one scan line 12 . Furthermore, for the thin film transistor array substrate, the conductive contact holes 184 may be distributed in a random or patterned manner. For example, if a relatively obvious lateral crosstalk phenomenon can be observed in several areas of a liquid crystal display, the conductive contact holes 184 can be designed to be distributed in those specific areas. Additionally, the conductive contact holes 184 may be distributed in a random manner to ensure display grade even when no significant lateral cross-image is observed. Furthermore, the distribution of the conductive contact holes 184 can take into account the brightness to ensure that the brightness will not be significantly affected, for example, human eyes will not feel the difference when the brightness decreases by 0.7%.

In this embodiment, the function of the conductive contact hole 184 is to match the design of the conductive layer 22 . For any two pixel regions adjacent to the scan line 12 , the conductive layer 22 is disposed on the two second line components 182 having corresponding conductive contact holes 184 , so as to electrically connect the two second line components 182 . According to the above, the conductive layer 22 spans the scan line 12 between the conductive contact holes 184 , that is, spans the scan line 12 between two adjacent pixels. Although the load of the scan line 12 may increase by about 5% due to the crossover of the conductive layer 22 , it does not have any visible impact on the waveform transmission and transmission of the scan line 12 . Furthermore, one of the features of the present invention is that the pixel electrode 20 overlaps part of the second line assembly 182, so as to increase the contrast of the liquid crystal display. According to the above, the design of the pixel electrode 20 can be applied to different types of display substrates, such as twisted nematic (Twisted Nematic, TN) type, wide viewing angle multi-domain vertical alignment (Multi-domain Vertically Align, MVA) type or wide viewing angle multi-domain Domain homogeneous alignment (Multi-domain Homeotropic Align, MHA).

FIG. 2 is a schematic cross-sectional view illustrating a liquid crystal display having a TFT array substrate along line AA' of FIG. 1 according to an embodiment of the present invention. A liquid crystal display includes a color filter substrate structure 26 and an opposite thin film transistor array substrate, and a liquid crystal layer 28 is interposed therebetween. In one embodiment, the color filter substrate structure 26 may include a color filter layer 262 , a protection layer 263 , a common electrode 264 and a polyimide alignment film 265 formed on a glass substrate 261 . On the other hand, for the thin film transistor array substrate, a first metal layer is formed on a glass substrate 101, and then the pattern transfer is performed to form the scanning lines 12 and the storage capacitor lines. Afterwards, an insulating layer 103 is formed on the scan line 12 and the storage capacitor line. According to the spirit of the present invention, the insulating layer 103 is pattern transferred to form a contact hole on the second line assembly of the storage capacitor line. A conductive layer is filled into the contact hole to form the conductive contact hole 184 , and the conductive layer covers the insulating layer 103 . A photolithography step is performed on the conductive layer to form the patterned pixel electrode 20 and the conductive layer 22 . According to the above, the conductive layer 22 straddles the scan line 12 to electrically connect the two storage capacitor lines.

The embodiments described above are only to illustrate the technical ideas and characteristics of the present invention, and its purpose is to enable those familiar with the technology to understand the content of the present invention and implement it accordingly. The equivalent changes or modifications made by the disclosed spirit of the invention shall still fall within the scope of the claims of the present application.

Claims (16)

1. thin-film transistor array base-plate comprises:

A plurality of sweep traces;

A plurality of data lines intersect to define a plurality of pixel regions with described a plurality of sweep traces;

A plurality of thin film transistor (TFT)s are positioned on the position that described a plurality of sweep trace and described a plurality of data lines intersect;

A plurality of capacitor storage beam are to be arranged in each described pixel region, and wherein, each described capacitor storage beam comprises one first line component, and the direction setting of its parallel described sweep trace, and one second line component are the direction settings of parallel described data line;

A plurality of pixel electrodes, its correspondence is arranged at described pixel region, and electrically connects corresponding described thin film transistor (TFT);

A plurality of contact holes, each described contact hole are to be arranged on the end points of described second line component; And

One conductive layer, it connects described second line component of two adjacent pixels, and electrically connects by described contact hole and described second line component,

Wherein said capacitor storage beam and described a plurality of sweep traces are that identical rete and described capacitor storage beam and described pixel electrode are different retes.

2. thin-film transistor array base-plate as claimed in claim 1 is characterized in that described a plurality of conduction contact hole is distributed in described a plurality of pixel region at random mode.

3. thin-film transistor array base-plate as claimed in claim 1 is characterized in that described a plurality of conduction contact hole is distributed in described a plurality of pixel region in a kind of mode of pattern.

4. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that for arbitrary described second line component with described corresponding conduction contact hole an extension is positioned at the terminal of described second line component and in order to the conduction contact hole of ccontaining described correspondence.

5. thin-film transistor array base-plate as claimed in claim 1 is characterized in that also crossing over described sweep trace between the described two adjacent pixels at the described conductive layer of described second line component with described corresponding conduction contact hole.

6. thin-film transistor array base-plate as claimed in claim 1 is characterized in that two described second line components are oppositely arranged, and is arranged in each described pixel region.

7. thin-film transistor array base-plate as claimed in claim 6 is characterized in that for each described pixel region, and described second line component with described corresponding conduction contact hole is away from described corresponding thin film transistor (TFT).

8. thin-film transistor array base-plate as claimed in claim 6, it is characterized in that described pixel electrode also between described two second line components and with the part described two second line components overlapping.

9. liquid crystal indicator comprises:

One first board structure;

One second board structure is in the face of described first board structure, and wherein said second board structure comprises:

A plurality of sweep traces;

A plurality of data lines intersect to define a plurality of pixel regions with described a plurality of sweep traces;

A plurality of capacitor storage beam, it is arranged in each described pixel region, and wherein, each described capacitor storage beam comprises one first line component, the direction setting of its parallel described sweep trace, and one second line component, the direction setting of its parallel described data line;

A plurality of pixel electrodes, its correspondence is arranged at described pixel region, and electrically connects corresponding described thin film transistor (TFT);

A plurality of conduction contact holes, each described contact hole are to be arranged on the end points of described second line component; And

One conductive layer, it connects described second line component of two adjacent pixels, and electrically connects by described contact hole and described second line component,

Wherein said capacitor storage beam and described a plurality of sweep traces are that identical rete and described capacitor storage beam and described pixel electrode are different retes; And

One liquid crystal layer is between described first board structure and described second board structure.

10. liquid crystal indicator as claimed in claim 9 is characterized in that described second board structure also comprises a plurality of thin film transistor (TFT)s and is positioned on the position that described a plurality of sweep trace and described a plurality of data lines intersect.

11. liquid crystal indicator as claimed in claim 9 is characterized in that described conduction contact hole is distributed in described a plurality of pixel region at random mode.

12. liquid crystal indicator as claimed in claim 9 is characterized in that described a plurality of conduction contact hole is distributed in described a plurality of pixel region in a kind of mode of pattern.

13. liquid crystal indicator as claimed in claim 9 is characterized in that also crossing over described sweep trace between the described two adjacent pixels at the described conductive layer of described second line component with described corresponding conduction contact hole.

14. liquid crystal indicator as claimed in claim 9 is characterized in that described first board structure comprises:

One glass substrate;

One chromatic filter layer is positioned at described glass substrate;

One common electrode is positioned on the described chromatic filter layer; And

One alignment film is positioned on the described common electrode.

15. liquid crystal indicator as claimed in claim 9 is characterized in that described a plurality of sweep trace and described a plurality of capacitor storage beam form with the same metal layer on a glass substrate.

16. liquid crystal indicator as claimed in claim 9 is characterized in that described pixel electrode and described conductive layer are to form with an indium tin oxide.

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