CN101123670A

CN101123670A - Optical sensor and solid imaging part

Info

Publication number: CN101123670A
Application number: CNA2006101149061A
Authority: CN
Inventors: 须川成利; 赤羽奈奈; 足立理
Original assignee: 东北大学
Priority date: 2006-08-09
Filing date: 2006-08-09
Publication date: 2008-02-13
Anticipated expiration: 2026-08-09
Also published as: CN101123670B

Abstract

The present invention relates to a solid imaging device, which includes a plurality of pixels which are stored according to one-dimension or two-dimension array, and each of the plurality of pixels includes a photodiode for receiving lights and generating photo-electrons, a blooming gate which is coupled with the photodiode and transfers the photo-electrons spilled over the photodiode in the period of storage operation, and a storage capacitor unit which is used to store the photo-electrons transferring through the blooming gate in the period of storage operation.

Description

Optical pickocff and solid imaging device

Technical field

The present invention relates to a kind of optical pickocff and estimate image device, particularly, relate to the one dimension or the two-dimensional solid image device of a kind of CMOS or ccd sensor, and a kind of method of operation of above-mentioned solid imaging device.

Background technology

For example the imageing sensor of CMOS (complementary metal oxide semiconductors (CMOS)) imageing sensor and CCD (charge coupled device) imageing sensor improves to some extent on performance, and is widely used in digital camera, has in the cell phone, scanner etc. of video camera.

Yet, also require the improvement of other performance of imageing sensor.One of them is dynamic range expanded.The dynamic range of the imageing sensor that tradition is used remains on the magnitude of for example 3 to 4 (60 to 80dB), therefore expect the high-quality image-position sensor that realization has at least 5 to 6 (100 to 120dB) dynamic ranges, can compare with bore hole or silver hailde film.

As a kind of technology that improves the picture quality of above-mentioned imageing sensor, for example, in order to realize high sensitivity and high S/N ratio, S.Inoue et al., " IEEE Workshop on CCDsand Advanced Image Sensor 2001; pp.16-19 " (below be called " non-patent literature 1 ") has proposed a kind of technology, be used for by read in noise signal that the floating region adjacent with the photodiode of each pixel produce and with the noise signal of light signal addition, and obtain difference between the two, reduce noise.Yet even by this method, attainable dynamic range is the highest on the magnitude of 80dB.Require to realize wideer dynamic range.

In addition, for example as shown in Figure 1, open (JP-A) No.2003-134396 of Japanese Unexamined Patent Application (below be called " patent documentation 1 ") discloses a kind of technology, be used for by making the floating region that is positioned at high sensitivity and low-light (level) one side and being positioned at muting sensitivity and the floating region with large capacitor C2 of high illumination one side links to each other with photodiode PD with small capacitor C1, and export low-light (level) one side output OUT1 and high illumination one side output OUT2 respectively, come dynamic range expanded.

In addition, as shown in Figure 2, Japanese Unexamined Patent Application open (JP-A) No.2000-165754 (below be called " patent documentation 2 ") discloses that a kind of capacitor CS in diffusion (FD) district of floating is variable to come dynamic range expanded technology by making.In addition, there is another kind of public technology, be used for by imaging being divided into imaging with at least two different exposure time sections, comprising having with the imaging of the corresponding short exposure time section of high illumination one side and having imaging with the corresponding long time for exposure section of low-light (level) one side, come dynamic range expanded.

In addition, as shown in Figure 3, Japanese Unexamined Patent Application (JP-A) No.2002-77737 (below be called " patent documentation 3 ") and Y.Muramatsu et al., IEEE Journalof Solid-State Circuits, Vol.38, No.1, pp.16-19 (below be called " non-patent literature 2 ") discloses a kind of technology, be used for by between photodiode PD and capacitor C, transistor switch T being set, actuating switch T in the first time for exposure section so as with the light signal charge storage in photodiode PD and capacitor C, and cutoff switch T in the second time for exposure section on the charge stored, comes dynamic range expanded so that optical charge is stored among the photodiode PD in the first time for exposure section.Herein, these documents disclose therein: when the rayed that exceeds its saturation value is provided, discharge excessive electric charge by reset transistor R.

In addition, as shown in Figure 4, Japanese Unexamined Patent Application open (JP-A) No.5-90556 (below be called " patent documentation 4 ") discloses a kind of technology, is used for by using the capacitor greater than traditional capacitor, as photodiode PD, allow to solve high illumination imaging problem.

In addition, as shown in Figure 5, The Journal of the Institute of ImageInformation and Television Engineers, Vol.57,2003 (below be called " non-patent literature 3 ") disclose a kind of technology, be used for by by the logarithmic transformation circuit formed of combination MOS transistor logarithmically in the switching signal, storage and output come dynamic range expanded from the photo-signal of photodiode PD.

Above-mentioned

patent documentation

1,2 and 3 and non-patent literature 2 in the method that proposes, perhaps be used for utilizing two or more different exposure time sections to come imaging method, carry out the imaging of low-light (level) one side and the imaging of high illumination one side in the time that differs from one another.This problem that causes is time of occurrence interval between the imaging time of described at least two imagings, thereby has damaged the quality of moving image.

In addition, in the method that in above-mentioned

patent documentation

4 and 3, proposes, can be by the dynamic range that for example realizes broad, still as long as pay close attention to the imaging of low-light (level) one side with the corresponding imaging of high illumination one side, then undesirably can cause muting sensitivity and low S/N ratio, thus infringement picture quality.

As mentioned above, in the imageing sensor of for example cmos image sensor, be difficult to when keeping high sensitivity and high S/N ratio, realize the dynamic range of broad.Foregoing is not only applicable to the imageing sensor that pixel is arranged according to the two-dimensional matrix row, and is applicable to that pixel is according to the linear transducer of one-dimensional array arrangement and the optical pickocff that does not have a plurality of pixels.

Summary of the invention

Therefore, the purpose of this invention is to provide a kind of solid imaging device, can be dynamic range expanded when keeping high sensitivity and high S/N ratio.

According to solid imaging device of the present invention, can be by in low-light-level imaging, keeping high sensitivity and high S/N ratio by the photodiode that receives light and generation and storage optical charge, and, realize the dynamic range of broad by being stored in and carrying out high illumination imaging in the holding capacitor by overflowing a optical charge that door overflows photodiode.

According to an aspect of the present invention, provide a kind of optical pickocff.Described optical pickocff comprises: photodiode receives light and produces optical charge; Overflow door, be coupled, and during storage operation, shift the optical charge that overflows photodiode with photodiode; And storage capacitor cells, storage is by overflowing the optical charge of a transfer during storage operation.

Optical pickocff also comprises the transfering transistor that is coupled with photodiode and floating region, and wherein, transfering transistor is transferred to floating region with optical charge from photodiode.

Overflowing door can be made of junction transistor.In this case, preferably form junction transistor grid semiconductor regions and the surface region that forms photodiode semiconductor regions and with form photodiode and link to each other with the well region that overflows door.

The desired depth place that can form the substrate that overflows door therein forms overflows door.In this case, preferably overflow the semiconductor layer that door has and overflow the raceway groove identical conduction type of door, described semiconductor layer reduces potential barrier so that break-through in overflowing door.

Storage capacitor cells can comprise: the semiconductor regions as bottom electrode is formed in the surface layer part of the Semiconductor substrate that has wherein formed optical pickocff; Capacitor insulating film is formed on the semiconductor regions; And top electrode, be formed on the capacitor insulating film.

Storage capacitor cells can comprise: bottom electrode is formed on the substrate that has wherein formed optical pickocff; Capacitor insulating film is formed on the bottom electrode; And top electrode, be formed on the capacitor insulating film.

Storage capacitor cells can comprise: the semiconductor regions as bottom electrode, be formed in the inwall of groove, and described groove forms and has formed therein in the Semiconductor substrate of optical pickocff; Capacitor insulating film is formed on the inwall of groove; And top electrode, be formed on the capacitor insulating film and embed groove.

A kind of solid imaging device that comprises a plurality of pixels of arranging according to one dimension or two-dimensional matrix is provided, and wherein each pixel has above-mentioned optical pickocff.

Overflowing door can be made of MOS transistor or junction transistor.

The another kind of solid imaging device that comprises a plurality of block of pixels also is provided.In this device, each of described a plurality of block of pixels comprises a plurality of pixels and single floating region.Each of described a plurality of pixels comprises: photodiode receives light and produces optical charge; Overflow door, be coupled, and during storage operation, shift the optical charge that overflows photodiode with photodiode; Storage capacitor cells, storage is by overflowing the optical charge of a transfer during storage operation; And transfering transistor, be coupled with photodiode and single floating region.

Transfering transistor can be to imbed channel transistor, have with the raceway groove identical conduction type of transfering transistor, from the surface of the substrate that wherein formed transfering transistor or near surface up to the formed semiconductor layer of desired depth.

Comprise that the solid imaging device that a plurality of pixels, each pixel have an above-mentioned optical pickocff can also comprise: reset transistor, be coupled with floating region, be used for discharging the signal charge of storage capacitor cells and floating region; Transistor is arranged between floating region and the storage capacitor cells; Amplifier transistor is used for reading the signal charge in floating region or floating region and the storage capacitor cells, as voltage; Select transistor, be coupled, be used to select pixel with amplifier transistor.

Solid imaging device can also comprise: reset transistor, be coupled with storage capacitor cells, and be used for discharging the signal charge of storage capacitor cells and floating region; Transistor is arranged between floating region and the storage capacitor cells; Amplifier transistor is used for reading the signal charge in floating region or floating region and the storage capacitor cells, as voltage; Select transistor, be coupled, be used to select pixel with amplifier transistor.

Comprise that the solid imaging device that a plurality of pixels, each pixel have an above-mentioned optical pickocff can also comprise: noise cancelling arrangement, be used to obtain two differences between the voltage signal, one of two voltage signals are from transferring to floating region or transferring to floating region and the voltage signal that optical charge obtained of storage capacitor cells; Another voltage signal is the voltage signal at the reset level place of floating region or floating region and storage capacitor cells.

Solid imaging device can also comprise: storage device is used for storing the voltage signal at floating region and storage capacitor cells reset level place.

According to other aspects of the invention, provide a kind of method from the optical pickocff output signal that comprises photodiode and storage capacitor cells.Described method comprises step: before photodiode is saturated, store first optical charge that photodiode produced into photodiode; After saturated, store second optical charge that photodiode produced into storage capacitor cells; And, come output signal according to first and second optical charges.

Overflowing door can be made of the MOS transistor that is coupling between photodiode and the holding capacitor, and the gate electrode of MOS transistor receives the signal of determining storage operation.

Description of drawings

Fig. 1 is and patent documentation 1 corresponding equivalent circuit diagram;

Fig. 2 is and patent documentation 2 corresponding equivalent circuit diagrams;

Fig. 3 is and patent documentation 3 corresponding equivalent circuit diagrams;

Fig. 4 is and patent documentation 4 corresponding equivalent circuit diagrams;

Fig. 5 right and wrong patent documentation 3 corresponding equivalent circuit diagrams;

Fig. 6 is the equivalent circuit diagram according to the pixel in the solid imaging device of first embodiment of the invention;

Fig. 7 is the schematic plan view according to the pixel in the solid imaging device of first embodiment of the invention;

Fig. 8 A be expression according to the photodiode PD1 of the pixel in the solid imaging device of first embodiment of the invention, overflow the schematic section in the zone of a LO4 and holding capacitor CS5.

Fig. 8 B is the schematic section of expression according to the zone of photodiode PD1, transfering transistor T2, floating region FD3, memory transistor S7 and the holding capacitor CS5 of the pixel in the solid imaging device of first embodiment of the invention;

Fig. 9 is the driving timing figure according to the solid imaging device of first embodiment of the invention;

Figure 10 is the block diagram according to the solid imaging device of first embodiment of the invention;

Figure 11 is the equivalent circuit diagram according to the pixel in the solid imaging device of second embodiment of the invention;

Figure 12 is the schematic plan view according to the pixel in the solid imaging device of second embodiment of the invention;

Figure 13 is the driving timing figure according to the solid imaging device of second embodiment of the invention;

Figure 14 is the equivalent circuit diagram according to the pixel in the solid imaging device of third embodiment of the invention, and this equivalence circuit diagram is corresponding with the equivalent circuit diagram of first embodiment;

Figure 15 is the schematic plan view according to the pixel in the solid imaging device of third embodiment of the invention, and this plane graph is corresponding with the plane graph of first embodiment;

Figure 16 is the equivalent circuit diagram according to the pixel in the solid imaging device of third embodiment of the invention, and this equivalence circuit diagram is corresponding with the equivalent circuit diagram of second embodiment;

Figure 17 is the schematic plan view according to the pixel in the solid imaging device of third embodiment of the invention, and this plane graph is corresponding with the plane graph of second embodiment;

Figure 18 is the sectional view according to the pixel in the solid imaging device of third embodiment of the invention;

Figure 19 is the sectional view according to the pixel in the solid imaging device of fourth embodiment of the invention;

Figure 20 is the sectional view according to the pixel in the solid imaging device of fourth embodiment of the invention;

Figure 21 is the sectional view according to the pixel in the solid imaging device of fourth embodiment of the invention;

Figure 22 is the equivalent circuit diagram according to two pixels in the solid imaging device of fifth embodiment of the invention;

Figure 23 is the schematic plan view according to two pixels in the solid imaging device of fifth embodiment of the invention;

Figure 24 is the driving timing figure according to the solid imaging device of fifth embodiment of the invention;

Figure 25 is the equivalent circuit diagram according to four pixels in the solid imaging device of sixth embodiment of the invention;

Figure 26 is the schematic plan view according to four pixels in the solid imaging device of sixth embodiment of the invention;

Figure 27 is the driving timing figure according to the solid imaging device of sixth embodiment of the invention;

Figure 28 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 29 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 30 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 31 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 32 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 33 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 34 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 35 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 36 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 37 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 38 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 39 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention;

Figure 40 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention; And

Figure 41 is the sectional view according to the pixel in the solid imaging device of seventh embodiment of the invention.

Embodiment

Below, the solid imaging device according to the embodiment of the invention is described with reference to the accompanying drawings.In whole accompanying drawings, identical reference symbol is represented identical or equivalent part.

First embodiment

Fig. 6 shows the equivalent electric circuit according to the pixel in the solid imaging device of first embodiment of the invention, and Fig. 7 is its schematic plan view.

Each pixel comprises: photodiode PD1 receives light, and produces and the storage optical charge; Transfering transistor T2 is arranged near photodiode PD1 place, and shifts optical charge; Floating region (floating region) FD3 links to each other with photodiode PD1 through transfering transistor T2; Overflow a LO4, be arranged on, and during storage operation, shift the optical charge that overflows photodiode PD1 near photodiode PD1 place; Holding capacitor CS5, storage is by overflowing the optical charge that a LO4 overflows photodiode PD1 during storage operation; Reset transistor R6, FD3 links to each other with floating region, is used for discharging the signal charge of holding capacitor CS5 and floating region FD3; Memory transistor S7 is arranged between floating region FD3 and the holding capacitor CS5; Amplifier transistor SF8 is used for reading the signal charge among floating region FD3 or floating region FD3 and the holding capacitor CS5, as voltage; And selecting transistor X9, SF8 links to each other with amplifier transistor, is used to select pixel or block of pixels.

In solid imaging device according to present embodiment, store a plurality of pixels according to two dimension or one-dimensional array, each of described a plurality of pixels has above-mentioned setting.In each pixel, drive wire φ _LO10, φ _T11, φ _S12 and φ _R13 link to each other with the gate electrode that overflows a LO4, transfering transistor T2, memory transistor S7 and reset transistor R6 respectively.In addition, the pixel selection line φ that drives by line shift register _X14 link to each other with the gate electrode of selecting transistor X9.In addition, output line OUT15 links to each other with the outlet side source electrode of selecting transistor X9, and by column shift register control, in order to produce output.

Formation according to solid imaging device of the present invention is unrestricted, as long as can make the voltage of floating region FD3 be fixed on suitable value, so that can carry out the selection operation or the non-selected operation of pixel.Therefore, also can omit selection transistor X9 and drive wire φ _X14.

Fig. 8 A be expression according to the photodiode PD1 of the pixel in the solid imaging device of present embodiment, overflow the schematic section in the zone of a LO4 and holding capacitor CS5, Fig. 8 B is the schematic section in the zone of photodiode PD1, transfering transistor T2, floating region FD3, memory transistor S7 and holding capacitor CS5 in the remarked pixel.

For example, on n type silicon semiconductor substrate (n-sub) 20, form p type trap (p-well) 21, and, be used to separate each pixel, and form holding capacitor CS by formation unit separating

insulation films

22,23,24 and 25 such as LOCOS methods.In addition, form p+ type separated

region

26,27,28 and 29 at the p type trap 21 that is used under the unit separating insulation film of discrete pixels.In p type trap 21, form n N-type semiconductor N zone 30, and on its superficial layer, form p+ N-type semiconductor N zone 31.Logical this pn knot has constituted electric charge and has shifted built-in photodiode PD.When light LT enters when pn knot being applied the depletion layer that suitable biasing produces, produce optical charge by photoelectric effect.

There is the zone that is formed for leaving p+ N-type semiconductor N zone 31 in end in n N-type semiconductor N zone 30, and apart from this preset distance place, zone, forms n+ N-type semiconductor N zone 32 in the superficial layer of p type trap 21.

In addition, there is another zone that is formed for leaving p+ N-type semiconductor N zone 31 in end in n N-type semiconductor N zone 30, and in the position apart from described another regional preset distance place, in the superficial layer of p type trap 21, form n+ N-type semiconductor N zone 33, as floating region FD.In addition, at described another the regional preset distance place of distance, form n+ N-type semiconductor N zone 34.

Herein, with zone that n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 32 are associated in, through the gate insulating film 35 that constitutes by silica, on the upper surface of p type trap 21, form the gate electrode of forming by polysilicon etc. 36, and the LO that overflows with channel formation region territory is set in the superficial layer of p type trap, and wherein n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 32 are as source/drain.

In addition, with zone that n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 33 are associated in, through the gate insulating film 37 that constitutes by silica etc., on the upper surface of p type trap 21, form the gate electrode of forming by polysilicon etc. 38, and the transfering transistor T with channel formation region territory is set in the superficial layer of p type trap, and wherein n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 33 are as source/drain.

In addition, with zone that n+ N-type semiconductor N zone 33 and n+ N-type semiconductor N zone 34 are associated in, through the gate insulating film 39 that constitutes by silica etc., on the upper surface of p type trap 21, form the gate electrode of forming by polysilicon etc. 40, and the memory transistor S with channel formation region territory is set in the superficial layer of p type trap, and wherein n+ N-type semiconductor N zone 33 and n+ N-type semiconductor N zone 34 are as source/drain.

In addition, in by unit separating

insulation film

22 and 23 separate areas, in the superficial layer of p type trap, form p+ N-type semiconductor N zone 41, as bottom electrode, and on this layer,, form the top electrode of forming by polysilicon etc. 43 through the capacitor insulating film 42 that constitutes by silica etc.These have constituted holding capacitor CS.

The dielectric film 44 that formation is made of silica etc. overflows a L0, transfering transistor T, memory transistor S and holding capacitor CS so that cover.Opening portion is set, and this opening portion passes through n+ N-type semiconductor N zone 34 up to top electrode 43 from n+ N-type semiconductor N zone 32 and n+ N-type semiconductor N zone 33.In addition, be provided with make wiring 45 that n+ N-type semiconductor N zone 32 links to each other with top electrode 43 and with regional 33 wirings that link to each other 46 of n+ N-type semiconductor N.

Drive wire φ _TLink to each other with the gate electrode 38 of transfering transistor T, and drive wire φ _SLink to each other with the gate electrode 40 of memory transistor S.

Drive wire φ _LOLink to each other with the gate electrode 36 that overflows a LO.Drive wire φ _LOCan be applied in drive pulse signal, perhaps, link to each other with zero potential alternatively just as under the situation of p type trap 21.The threshold voltage that overflows a LO is set to be lower than the threshold voltage of transfering transistor T, therefore makes the excessive charge of the saturation value that exceeds photodiode PD flow into holding capacitor CS effectively by overflowing a LO effectively.When making the threshold voltage that overflows a LO and dedicated transistor T identical, the value that electromotive force is set to be higher than zero potential can make the excessive charge of the saturation value that exceeds photodiode PD flow into holding capacitor CS effectively by overflowing a LO.

Constitute the unit about other, i.e. reset transistor R, floating amplifier transistor SF, selection transistor X, drive wire φ _RAnd φ _XAnd output line OUT, on the not shown zone on the Semiconductor substrate shown in Fig. 8 A and the 8B 20, constitute these unit, make wiring 46 link to each other, so structure is embodied as the structure shown in Fig. 6 equivalent electrical diagram with amplifier transistor SF (not shown).

Photodiode PD constitutes the capacitor C with relative more shallow electromotive force, and floating region FD constitutes the capacitor C with relative dark electromotive force respectively with holding capacitor CS _FDAnd C _CS

Herein, description is according to the method for operation of the solid imaging device of the embodiment shown in Fig. 6,7,8A and the 8B.Fig. 9 is the driving timing figure according to the solid imaging device of present embodiment.

At first, in exposure storage (exposure storage) before, memory transistor S is set to conducting, and transfering transistor T and reset transistor R are set to end.At this moment, photodiode PD is in complete spent condition.Next, turns on reset transistor R is in order to floating region FD and the holding capacitor CS (time: t of resetting ₁).Then, the reset noise at (FD+CS) that catch immediately after reset transistor R is read as the noise signal N2 (time: t ₂).Herein, noise signal N2 comprises the variation in the threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).(the time: t during the memory cycle ₃), in the state of memory transistor S, transfering transistor T, reset transistor R and selection transistor X, store saturated preceding optical charge by photodiode PD, and be stored among the holding capacitor CS through overflowing a LO above saturated excessive optical charge.This operation is feasible to effectively utilize the electric charge that overflows photodiode PD, and does not abandon these electric charges.In this manner, before saturated and in the time period afterwards, in identical memory time section,, carry out storage operation by receiving light by identical photodiode PD for each pixel.

(the time: t after finishing storage ₄), transistor X is selected in conducting.Then, turns on reset transistor R is in order to the floating region FD (time: t that resets ₅), and the reset noise of the FD that catches immediately after resetting is read as the noise signal N1 (time: t ₆).Herein, noise signal N1 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).

Next, conducting transfering transistor T transfers to the floating region FD (time: t fully in order to the light signal that will be stored among the photodiode PD ₇), and signal is read as (S1+N1).Then, also conducting memory transistor S transfers to floating region FD and holding capacitor CS (time: t fully in order to the optical charge that will be stored among the photodiode PD ₈).The electric charge that is stored among photodiode PD, floating region FD and the holding capacitor CS is mixed, and signal is read as (S1+S2+N1).

Figure 10 is the block diagram according to the solid imaging device of present embodiment.At the peripheral 100-103 of the pel array of two-dimensional arrangements, be provided with line shift register (VSR) 104, column shift register (HSR) 105, signal/noise and preserve part 106 and output circuit 107., show the pel array example of (2 pixels * 2 pixels) in order to simplify, but the number of pixel is not limited to this herein.

The signal of reading from each pixel pointwise is noise signal N1 and (light signal of changing through charge/voltage before saturated, among FD)+(noise signal) (i.e. (S1+N1)); Noise signal N2 and (before saturated and afterwards in FD and CS through the summation light signal of charge/voltage conversion)+(noise signal) (i.e. (S1+S2+N2)).By subtraction circuit, carry out noise-removal operation about the signal before saturated: [(S1+N1)-N1].This has removed random noise component and fixing pattern noise component(s).On the other hand, after beginning to store, read the noise N2 of supersaturation side immediately, when removing the random noise component and fixedly during the pattern noise component(s), immediately noise N2 being stored in the frame memory, by subtraction circuit carry out noise-removal operation thereafter: [(S1+N1)-N1].Therefore, can obtain to have removed the saturated front signal S1 and the supersaturation side signal (S1+S2) of noise.Can on image sensor chip, form subtraction circuit and frame memory, perhaps form it into individual chips.

The electric capacity of supposing floating region FD and holding capacitor CS is respectively C _FDAnd C _CS, then can be by (C _FD+ C _CS)/C _FDThe amplification ratio of generally representing dynamic range.Yet, in fact, compare with the situation of the floating region FD that resets, under the situation of (FD+CS) that resets, the clock feedthrough at reset transistor R place has less influence, and the saturation voltage of supersaturation side signal S2 becomes and is higher than the voltage of saturated front signal S1, so dynamic range is exaggerated with the amplification ratio greater than above-mentioned ratio.For dynamic range expanded effectively when keeping the high-NA of photodiode and do not increase Pixel Dimensions, hope can form the big storage capacitance with high area efficiency.

One of saturated front signal S1 that can be by selecting to have removed noise and supersaturation signal (S1+S2), dynamic range signal synthetic of realizing broad.After the signal output voltage that can switch reference voltage and S1 at S1/ (S1+S2) that will be default is compared, select signal S1 and one of (S1+S2), realize S1 and (S1+S2) between selection.Recommendation is switched reference voltage and is set to the saturation voltage less than S1, to avoid switching the influence of the variation in the saturation voltage that reference voltage is subjected to saturated front signal S1, and simultaneously, it is set to high voltage at switching point, so that keep the high S/N ratio of supersaturation side signal (S1+S2).Ratio (C is multiply by in the gain of supersaturation side signal (S1+S2) herein, _FD+ C _CS)/C _FD, make this gain consistent with the gain of saturated front signal S1.Therefore, all be linear signal by optionally making up up to high illumination from low-light (level), can obtain to have the picture signal of the dynamic range of amplification.

Apparent from aforesaid operations, in this solid imaging device, because saturated front signal electric charge and supersaturation side signal charge are mixed to supersaturation side signal (S1+S2), so signal (S1+S2) comprises near the signal charge of saturated front signal S1 PD is saturated at least.This has strengthened the tolerance limit for the noise component(s) such as the low dark current of reset noise and supersaturation side.Utilize the enhancing noise margin of supersaturation side (S1+S2) signal, by after reset floating region FD and holding capacitor CS, in field (for example N2 ') subsequently, reading electromotive force immediately, and obtain difference about (S1+S2+N2) in the previous field (i.e. (S1+S2+N2)-N2 '), in order to remove fixedly pattern noise component(s), even near the selection switching point between saturated front signal and the supersaturation signal, also can guarantee enough S/N ratios.

The read operation of saturated front signal (S1+N1) and noise signal N1 comprises removes floating region (FD) reset noise, and carry out the correction of the variations in threshold voltage of cd amplifier, therefore, in the low-light (level) zone, can realize high sensitivity and high S/N than (low noise) character, and afterimage (afterimage) can not occur.In the operation of supersaturation side, through overflowing after stored charge that a LO will overflow photodiode PD is stored in holding capacitor CS, the signal of carrying out the low-light (level) side reads in identical memory time section.After end is read, at time t ₈Mix the saturated front signal electric charge that remains among the floating region FD, and read the electric charge of mixing at the place with the supersaturation signal charge.In addition, at this time t ₈The place, when conducting memory transistor S, floating region FD links to each other with the holding capacitor CS with big electric capacity, and electromotive force (FD+CS) changes to positive direction.Therefore, efficiently the optical charge of photodiode PD is transferred to (FD+CS) fully, even photodiode PD is in saturation condition, so even near PD is saturated, also afterimage can not occur.

In addition, even become when saturated, can come effectively excessive charge to be discharged into power vd D by regulating the threshold voltage of reset transistor R and memory transistor S at holding capacitor CS.Therefore, even when using p type silicon semiconductor substrate, also can suppress blooming (blooming).Herein, can reset transistor R and the downside electromotive force of memory transistor S be set to the value higher than zero potential.

In this manner, in the unsaturated low-light-level imaging of photodiode, can keep high sensitivity and high S/N ratio by the saturated preceding charge signal (S1) that obtains by the counteracting noise.In addition, in the saturated high illumination imaging of photodiode PD, be stored among the holding capacitor CS by the optical charge that will overflow photodiode PD, catch these optical charges, and can keep high S/N ratio, thus on high illumination side by by offsetting the dynamic range that signal (charge signal and supersaturation signal sum (S1+S2) before being saturated) that noise obtains is realized broad similarly.

As mentioned above, increased the sensitivity of high illumination side according to the solid imaging device of present embodiment, and do not reduced the sensitivity of low-light (level) side, thereby realized relative broad range, in addition, this device does not use the supply voltage that exceeds the common scope of application.This makes this solid imaging device solve the problem of the miniaturization of imageing sensor in the future.In addition, because make the interpolation of unit be reduced to minimum, so can not cause the Pixel Dimensions that increases.

In addition, different with realization than the conventional image sensor of wide dynamic range, present embodiment is at identical section stored optical charge memory time, and do not divide section memory time between high illumination side and low-light (level) side, promptly do not have analysis frames (straddling frames).Even this has been avoided the deterioration of image quality in the imaging of moving image.

In addition, about the leakage current that from floating region FD, leaks, in the imageing sensor according to present embodiment, minimum signal (S1+S2) becomes the saturated charge of photodiode PD, so imageing sensor can be handled the quantity of electric charge greater than the quantity of electric charge of the leakage current of floating region FD.This provides the advantage that makes imageing sensor not be subjected to the influence of FD leakage.

Second embodiment

Solid imaging device according to present embodiment is the device of having revised according to the circuit arrangement of the pixel in the solid imaging device of first embodiment.Figure 11 is the equivalent circuit diagram of a pixel in the present embodiment, and Figure 12 is its schematic plan view.

Each pixel comprises: photodiode PD receives light, and produces and the storage optical charge; Transfering transistor T2 is arranged near photodiode PD1 place, and shifts optical charge; Floating region FD3 links to each other with photodiode PD1 through transfering transistor T2; Overflow a LO4, be arranged on, and during storage operation, shift the optical charge that overflows photodiode PD1 near photodiode PD1 place; Holding capacitor CS5, storage is by overflowing the optical charge that a LO4 overflows photodiode PD1 during storage operation; Reset transistor R6, CS5 links to each other with holding capacitor, is used for discharging the signal charge of holding capacitor CS5 and floating region FD3; Memory transistor S7 is arranged between floating region FD3 and the holding capacitor CS5; Amplifier transistor SF8 is used to read the signal charge of floating region FD3, perhaps reads the signal charge of floating region FD3 and holding capacitor CS5, as voltage; And selecting transistor X9, SF8 links to each other with amplifier transistor, is used to select pixel or block of pixels.

Identical with the situation of above-mentioned first embodiment, in solid imaging device, store a plurality of pixels according to two dimension or one-dimensional array according to present embodiment, each pixel has above-mentioned setting.In each pixel, drive wire φ _LO10, φ _T11, φ _S12 and φ _R13 respectively with overflow a LO4, transfering transistor T2, memory transistor S7 and reset transistor R6 and link to each other.In addition, the pixel selection line φ that drives by line shift register _X14 link to each other with the gate electrode of selecting transistor X9.In addition, output line OUT15 links to each other with the outlet side source electrode of selecting transistor X9, and by column shift register control, in order to produce output.

Identical with the situation of above-mentioned first embodiment, unrestricted according to the formation of the solid imaging device of present embodiment, as long as can make the voltage of floating region FD3 be fixed on suitable value, so that can carry out the selection operation or the non-selected operation of pixel.Therefore, also can omit selection transistor X9 and drive wire φ _X14.

In solid imaging device according to present embodiment, photodiode PD1 in the remarked pixel, overflow a LO4 and the zone of holding capacitor CS5 schematic section and first embodiment in identical shown in Fig. 8 A, therefore, for fear of repetition, omit describing to this figure.In addition, therefore the schematic section of photodiode PD1, transfering transistor T2, floating region FD3, memory transistor S7 and this solid imaging device in the zone of holding capacitor CS5 identical with shown in Fig. 8 B also omit describing this figure in the remarked pixel.

Herein, description is according to the method for operation of the solid imaging device of the present embodiment shown in Figure 11 and 12.Figure 13 is the driving timing figure according to the solid imaging device of present embodiment.

At first, before storage, memory transistor S is set to conducting, and transfering transistor T and reset transistor R are set to end.At this moment, photodiode PD is in complete spent condition.

Next, turns on reset transistor R is in order to floating region FD and the holding capacitor CS (time: t of resetting ₁').Then, the reset noise at (the floating region FD+ holding capacitor CS) that catch immediately after reset transistor R is read as the noise signal N2 (time: t ₂').Herein, noise signal N2 comprises the variation in the threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).(the time: t during the memory time section ₃'), in the state of memory transistor S, transfering transistor T, reset transistor R and selection transistor X, by the saturated optical charge before of photodiode PD storage, and will be stored among the holding capacitor CS through overflowing a LO above saturated excessive optical charge.This operation makes can use the electric charge that overflows photodiode PD effectively, and does not abandon these electric charges.In this manner, before saturated and in the time period afterwards, in identical memory time section,, carry out storage operation by receiving light by identical photodiode PD for each pixel.

(the time: t after finishing storage ₄'), transistor X is selected in conducting, reads the noise signal that is stored among the photodiode PD then.Herein, noise signal N1 comprises the variation in the threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).Next, conducting transfering transistor T is so that the light signal that will be stored among the photodiode PD is transferred to the floating region FD (time: t fully ₅'), and signal is read as (S1+N1).Then, go back the conducting memory transistor S (time: t ₆'), and the signal charge that will be stored among the photodiode PD is transferred to floating region FD and holding capacitor CS fully.Herein, the electric charge that is stored among photodiode PD, floating region FD and the holding capacitor CS is mixed, and signal is read as (S1+S2+N2).

In first embodiment, during the reset operation of floating region FD, at time t ₆The place has abandoned a part that is stored in the noise signal N2 among floating region FD and the holding capacitor CS.The semaphore that abandon this moment is the CFD/ (C that is stored in the noise signal among floating region FD and the holding capacitor CS _FD+ C _CS) doubly.On the contrary, in solid imaging device, can not abandon the part noise signal according to present embodiment.

According to shown in Figure 10 identical among the block diagram of the solid imaging device of present embodiment and first embodiment,, omit describing to this figure therefore for fear of repetition.Identical with described in first embodiment of the signal that pointwise is read from pixel in the present embodiment, the amplification ratio of dynamic range and broad dynamic range signal synthetic.

Identical with the situation of first embodiment, increase the sensitivity of high illumination side according to the solid imaging device of present embodiment, and do not reduced the sensitivity of low-light (level) side, thereby realized the scope of broad, in addition, this device does not use the supply voltage that exceeds the common scope of application.This makes this solid imaging device can solve the problem of the miniaturization of imageing sensor in the future.In addition, because make the interpolation of unit be reduced to minimum, so can not cause Pixel Dimensions to increase.

In addition, and realize differently than the conventional image sensor of wide dynamic range, present embodiment is at identical section stored optical charge memory time, and do not divide section memory time between high illumination side and low-light (level) side, promptly do not have analysis frames.Even this has been avoided the deterioration of image quality in the imaging of moving image.

In addition, about the leakage current that from floating region FD, leaks, in imageing sensor, by the minimum signal that electric capacity read of floating region FD and holding capacitor CS (i.e. (C according to present embodiment _FD+ C _CS)) become (supersaturation electric charge)+(from the saturated charge of photodiode PD), so imageing sensor can be handled the quantity of electric charge greater than the quantity of electric charge of the leakage current of floating region FD.This provides the advantage that makes imageing sensor not be subjected to the influence of FD leakage.

The 3rd embodiment

Solid imaging device according to present embodiment is to have revised according to the present invention the device of the circuit arrangement of the pixel in the solid imaging device of first and second embodiment.Figure 14 and 15 is respectively the equivalent circuit diagram and the schematic plan view of the pixel in the present embodiment, and these two figure are corresponding with the corresponding figures of first embodiment.In addition, Figure 16 and 17 is respectively the equivalent circuit diagram and the schematic plan view of the pixel in the present embodiment, and these two figure are corresponding with the corresponding figures of second embodiment.

Each pixel comprises: photodiode PD receives light, and produces and the storage optical charge; Transfering transistor T2 is arranged near photodiode PD1 place, and shifts optical charge; Floating region FD3 links to each other with photodiode PD1 through transfering transistor T2; Overflow a LO4', be arranged on, and during storage operation, shift the optical charge that overflows photodiode PD1 near photodiode PD1 place; Holding capacitor CS5, storage is by overflowing the optical charge that a LO4' overflows photodiode PD1 during storage operation; Reset transistor R6, CS5 links to each other with holding capacitor, is used for discharging the signal charge among floating region FD3 (Figure 14) or the holding capacitor CS5 (Figure 16); Memory transistor S7 is arranged between floating region FD3 and the holding capacitor CS5; Amplifier transistor SF8 is used to read the signal charge of floating region FD3, perhaps reads the signal charge of floating region FD3 and holding capacitor CS5, as voltage; And selecting transistor X9, SF8 links to each other with amplifier transistor, is used to select pixel or block of pixels.

Identical with the situation of above-mentioned first and second embodiment, in solid imaging device, store a plurality of pixels according to two dimension or one-dimensional array according to present embodiment, each pixel has above-mentioned setting.In each pixel, drive wire φ T11, φ _S12 and φ _R13 link to each other with transfering transistor T2, memory transistor S7 and reset transistor R6 respectively.In addition, the pixel selection line φ that drives by line shift register _X14 link to each other with the gate electrode of selecting transistor X9.In addition, output line OUT15 links to each other with the outlet side source electrode of selecting transistor X9, and by column shift register control, in order to produce output.

Figure 18 be according to the pixel in the solid imaging device of the 3rd embodiment photodiode PD1, overflow the schematic section of a LO4 and holding capacitor CS5.Herein, with zone that n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 32 are associated in, on the upper surface of p type trap 21, form p+ semiconductor regions 50, and constitute a LO that overflows of junction transistor type, wherein n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 32 be as source/drain, and p+ semiconductor regions 50 is as grid.Other structure is identical with structure among above-mentioned first embodiment.Therefore, p+ semiconductor regions 50 is electrically connected with p+ semiconductor regions 31 and p type trap 21.

Identical according among the method for operation of the solid imaging device of present embodiment and first and second embodiment.According to shown in Figure 10 identical among the block diagram of the solid imaging device of present embodiment and first embodiment,, omit describing to this figure therefore for fear of repetition.Identical with described in first embodiment of the signal that pointwise is read from each pixel in the present embodiment, the amplification ratio of dynamic range and broad dynamic range signal synthetic.

According to the solid imaging device of present embodiment given play to first and second embodiment in the identical effect of solid imaging device, in addition, because p+ semiconductor regions 50 is electrically connected with p+ semiconductor regions 31 and p type trap 21, so compare with first and second embodiment, the number of the wiring of drive signal can be reduced according to the solid imaging device of present embodiment, and highdensity pixel can be realized.

The 4th embodiment

Solid imaging device according to present embodiment is to compare with above-mentioned the 3rd embodiment, is configured to move more smoothly during charge storage the device of the electric charge that overflows photodiode.

Figure 19 is the sectional view of the example of solid imaging device, wherein, overflowing a LO is to imbed channel transistor, have with the raceway groove identical conduction type of transfering transistor, from the surface of the substrate that constitutes transfering transistor or near surface up to the formed semiconductor layer of desired depth.Figure 19 represents photodiode PD, overflows the zone of a LO and holding capacitor CS.

Herein, the surface of the substrate under the p+ semiconductor regions that overflows a LO or near surface form n N-type semiconductor N zone 51 up to desired depth, so that overlapping n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 32.N type semiconductor zone 51 is the low n type zones of effective doping content than n N-type semiconductor N zone 30 and n+ N-type semiconductor N zone 32.

Said structure has reduced the potential barrier between photodiode PD and the holding capacitor CS.This makes the electric charge that can will overflow photodiode PD during charge storage smoothly move to holding capacitor CS.

Solid imaging device shown in Figure 20 and 21 be configured to have desired depth place at substrate, with the grid that overflows a LO under the semiconductor layer that forms of part parallel ground, and the reduction potential barrier is with break-through between photodiode PD and holding capacitor CS.

Figure 20 is the sectional view according to the example of the solid imaging device of present embodiment, expression photodiode PD, the zone of overflowing a LO and holding capacitor CS., under the gate electrode 50 that overflows a LO, in the zone at desired depth place, form n N-type semiconductor N zone 52 herein, so that link to each other with n N-type semiconductor N zone 30.

Said structure has reduced potential barrier so that break-through in overflowing a LO.Constituted overflow path along feedthrough path from photodiode PD to holding capacitor CS from the tilted direction in 52 to n+ N-type semiconductor N zones 32, n N-type semiconductor N zone, thereby make the electric charge break-through of overflowing photodiode PD, thereby smoothly electric charge is moved to holding capacitor CS at charge storage device.

Figure 21 is the sectional view according to the example of the solid imaging device of present embodiment.Identical with the situation of solid imaging device shown in Figure 20, under the gate electrode 50 that overflows a LO, in the zone at desired depth place, form n N-type semiconductor N zone 53, so that link to each other with n N-type semiconductor N zone 30.In the present embodiment, n N-type semiconductor N zone 53 further extends under the n+ N-type semiconductor N zone 32.

Said structure has reduced potential barrier, so that break-through in overflowing a LO.Constituted overflow path along feedthrough path from photodiode PD to holding capacitor CS from the basic vertical direction in 53 to n+ N-type semiconductor N zones 32, n N-type semiconductor N zone, thereby make the electric charge break-through of overflowing photodiode PD, thereby during charge storage, smoothly electric charge is moved to holding capacitor CS.

The 5th embodiment

According to the solid imaging device of present embodiment is the device of having revised according to the circuit arrangement of the solid imaging device of first embodiment.Figure 22 is the equivalent circuit diagram according to two pixels in the solid imaging device of present embodiment, and Figure 23 is its schematic plan view.

According to the solid imaging device of present embodiment is to have the block of pixels be made up of two pixels " a " and " b " device as elementary cell, and each block of pixels comprises two diodes and two holding capacitors.Each block of pixels comprises: photodiode PDa1 and PDb1 ' receive light, and produce and the storage optical charge; Transfering transistor Ta2 and Tb2' are set at respectively near photodiode PDa1 and PDb1 ' and locate, and shift optical charge; A floating region FD3 passes through transfering transistor Ta2 respectively and links to each other with PDb1 ' with photodiode PDa1 with Tb2'; Overflow a LOa4 and LOb4', be set at respectively near photodiode PDa1 and PDb1 ' and locate, be used for during storage operation, shifting the optical charge that overflows each photodiode PDa1 and PDb1 '; Holding capacitor CSa5 and CSb5 ' store respectively during storage operation by each and overflow the optical charge that a LOa4 and LOb4' overflow photodiode PDa1 and PDb1 '; Reset transistor R6 links to each other with each of holding capacitor CSa5 and CSb5', is used for discharging the signal charge of holding capacitor CSa5 and CSb5 ' and floating region FD3; Memory transistor Sa7 and Sb7' are arranged between floating region FD3 and holding capacitor CSa5 and the CSb5 '; Amplifier transistor SF8 is used to read the signal charge of floating region FD3, perhaps reads each signal charge of floating region FD3 and holding capacitor CSa5 and CSb5 ', as voltage; And selecting transistor X9, SF8 links to each other with amplifier transistor, is used to select pixel or block of pixels.In this manner, block of pixels is configured to comprise two photodiodes, two holding capacitors, floating region FD, amplifier transistor SF, reset transistor R and selects transistor X as elementary cell.

In solid imaging device, store a plurality of pixels according to two dimension or one-dimensional array with above-mentioned setting according to present embodiment.In each block of pixels, drive wire φ _LOa, φ _LOb, φ _Ta, φ _Tb, φ _Sa, φ _SbAnd φ _RRespectively with overflow a LOa4 and link to each other with Sb7 ' and reseting capacitor R6 with Tb2', memory transistor Sa7 with LOb4', transfering transistor Ta2.In addition, the pixel selection line φ that drives by line shift register _XLink to each other with the gate electrode of selecting transistor X9.In addition, output line OUT 15 links to each other with the outlet side source electrode of selecting transistor X9, and by column shift register control, in order to produce output.

Identical with the situation of above-mentioned first embodiment, unrestricted according to the formation of the solid imaging device of present embodiment, as long as can make the voltage of floating region FD3 be fixed on appropriate value, so that can carry out the selection operation or the non-selected operation of pixel.Therefore, can omit selection transistor X9 and drive wire φ _X

In solid imaging device according to present embodiment, similar shown in photodiode PDa1 among the pixel of remarked pixel piece " a " and " b " and PDb1 ', the schematic section in zone that overflows a LOa4 and LOb4' and holding capacitor CSa5 and CSb5' and Fig. 8 A among first embodiment, therefore for fear of repetition, omit describing to this figure.In addition, therefore similar shown in the schematic section of this solid imaging device in the zone of photodiode PDa1 in the remarked pixel and PDb1 ', transfering transistor Ta2 and Tb2 ', floating region FD3, memory transistor Sa7 and Sb7 ' and holding capacitor CSa5 and CSb5' and Fig. 8 B of first embodiment also omit describing it.

Herein, description is according to the method for operation of the solid imaging device of the present embodiment shown in Figure 22 and 23.Figure 24 is the driving timing figure according to the solid imaging device of present embodiment.In each block of pixels, when wanting read pixel " a " and " b ",, carry out and read by using identical floating region FD, amplifier transistor SF, reset transistor R and selecting transistor X.

At first, before exposure storage, the memory transistor Sa of pixel " a " is set to conducting, and transfering transistor Ta and reset transistor R are set to end.At this moment, the photodiode PD of pixel " a " is in complete spent condition.Next, turns on reset transistor R is in order to the floating region FD and the holding capacitor CSa (time: t of reset of pixels " a " ₁).Then, read the reset noise of (FD+CSa) that after reset transistor R, catch immediately, as the noise signal N2 (time: t ₂).Herein, noise signal N2 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).(the time: t during the memory time section ₃), the optical charge by photodiode PDa storage before saturated, and through overflowing a LOa the excessive optical charge when saturated is stored among the holding capacitor CSa.This operation makes can use the electric charge that overflows photodiode PD effectively, and does not abandon these electric charges.In this manner, before saturated and in the time period afterwards, in identical memory time section,, carry out storage operation by receiving light by identical photodiode PD for each pixel.

(the time: t after finishing storage ₄), transistor X is selected in conducting.Then, turns on reset transistor R is in order to the floating region FD (time: t that resets ₅), and read in the FD reset noise that resets and catch immediately afterwards, as the noise signal N1 (time: t ₆).Herein, noise signal N1 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).Next, conducting transfering transistor Ta transfers to the floating region FD (time: t fully in order to the light signal that will be stored among the photodiode PD ₇), and signal is read as (S1+N1).Then, go back the conducting memory transistor Sa (time: t ₈), transfer to floating region FD and holding capacitor CSa fully in order to the optical charge that will be stored among the photodiode PDa; Electric charge among photodiode PDa, floating region FD and the holding capacitor CSa is mixed, and signal is read as (S1+S2+N1).Similarly in pixel " b ", before the exposure storage, memory transistor Sb is set to conducting, and transfering transistor Tb and reset transistor R are set to end.Next, turns on reset transistor R, in order to floating region FD and the holding capacitor CSb of resetting, and the reset noise of (FD+CSb) that catch immediately after reset transistor R is read as noise signal N2.Herein, noise signal N2 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise signal.

(the time: t during the memory time section ₉), the optical charge by photodiode PDb storage before saturated, and through overflowing a LOb the excessive optical charge when saturated is stored among the holding capacitor CSb.

(the time: t after finishing storage ₁₀), transistor X is selected in conducting.Then, turns on reset transistor R is in order to the floating region FD (time: t that resets ₁₁), and the FD reset noise of catching immediately after resetting is read as the noise signal N1 (time: t ₁₂).

Next, conducting transfering transistor Tb transfers to the floating region FD (time: t fully in order to the light signal that will be stored among the photodiode PDb ₁₃), and signal is read as (S1+N1).Then, go back the conducting memory transistor Sb (time: t ₁₄), transfer to floating region FD and holding capacitor CSb fully in order to the optical charge that will be stored among the photodiode PDb.The electric charge that is stored among photodiode PDb, floating region FD and the holding capacitor CSb is mixed, and signal is read as (S1+S2+N2).

In solid imaging device, because floating region FD, amplifier transistor SF, reset transistor R are set and select transistor X, so can reduce the elemental area of each pixel with the ratio of one group of per two pixel according to present embodiment.

Except the ratio with one of per two pixel is provided with the output line, shown in Figure 10 identical according among the block diagram of the solid imaging device of present embodiment and first embodiment.Identical with described in first embodiment of the signal that pointwise is read from each pixel in the present embodiment, the amplification ratio of dynamic range and broad dynamic range signal synthetic.

In aforesaid operations, the situation that drives the pixel that is arranged on the block of pixels place successively and use the signal that obtains from all pixels has been described.Yet, as sparse operation (thinning-outoperation), can from each block of pixels, select pixel arbitrarily, so that use the signal that obtains from selected pixel.Alternatively,, can mix and increase the picture element signal in each block of pixels, use this signal then as average operation.

Identical with the situation of first embodiment, increase the sensitivity of high illumination side according to the solid imaging device of present embodiment, and do not reduced the sensitivity of low-light (level) side, thereby realized relative broad range, in addition, this device does not use the supply voltage that exceeds the common scope of application.This makes this solid imaging device solve the problem of the miniaturization of imageing sensor in the future.In addition, because make the interpolation of unit be reduced to minimum, so can not cause the Pixel Dimensions that increases.

The 6th embodiment

According to the solid imaging device of present embodiment is the device of having revised according to the circuit arrangement of the solid imaging device of first embodiment.Figure 25 is the equivalent circuit diagram according to four pixels in the solid imaging device of present embodiment, and Figure 26 is its schematic plan view.

According to the solid imaging device of present embodiment is to have the block of pixels be made up of four pixels " a ", " b ", " c " and " d " device as elementary cell, and each block of pixels comprises four diodes and four holding capacitors.Each block of pixels comprises: photodiode PDa1, PDb1 ', PDc1 " and PDd1 , receive light, and produce and the storage optical charge; Transfering transistor Ta2, Tb2', Tc2 " and Td2 , be set at respectively near photodiode PDa1, PDb1 ', PDc1 " and PDd1  place, and shift optical charge; A floating region FD3 passes through transfering transistor Ta2, Tb2 ', Tc2 respectively " with Td2  and photodiode PDa1, PDb1 ', PDc1 " link to each other with PDd1 ; Overflow a LOa4, LOb4', LOc4  and LOd4 , be set at respectively near photodiode PDa1, PDb1 ', PDc1 " and PDd1  place, be used for during storage operation transfer and overflow each photodiode PDa1, PDb1 ', PDc1 " and the optical charge of PDd1 ; Holding capacitor CSa5, CSb5', CSc5 " and CSd5 , during storage operation, store respectively and overflow a LOa4, LOb4', LOc4' and LOd4  by each and overflow photodiode PDa1, PDb1 ', PDc1 " and the optical charge of PDd1 ; Reset transistor R6 is with holding capacitor CSa5, CSb5', CSc5 " all link to each other with each of CSd5 , be used for discharging holding capacitor CSa5, CSb5', CSc5 " and the signal charge of CDd5  and floating region FD3; Memory transistor Sa7, Sb7', Sc7 " and Sd7 , be arranged on floating region FD3 and holding capacitor CSa5, CSb5', CSc5 " and CSd5  between; Amplifier transistor SF8 is used to read the signal charge of floating region FD3, perhaps reads floating region FD3 and holding capacitor CSa5, CSb5', CSc5 " and each signal charge of CSd5 , as voltage; And selecting transistor X9, SF8 links to each other with amplifier transistor, is used to select pixel or block of pixels.In this manner, block of pixels is configured to comprise four photodiodes, four holding capacitors, floating region FD, amplifier transistor SF, reset transistor R and selects transistor X as elementary cell.

In solid imaging device, store a plurality of pixels according to two dimension or one-dimensional array with above-mentioned setting according to present embodiment.In each block of pixels, drive wire φ _LOa, φ _LOb, φ _LOc, φ _LOd, φ _Ta, φ _Tb, φ _Tc, φ _Td, φ _Sa, φ _Sb, φ _Sc, φ _SdAnd φ _RRespectively with overflow a LOa4, LOb4', LOc4 " with LOd4 , transfering transistor Ta2, Tb2', Tc2 " with Td2 , memory transistor Sa7, Sb7 ', Sc7 " link to each other with Sd7  and reseting capacitor R6.In addition, the pixel selection line φ that drives by line shift register _XLink to each other with the gate electrode of selecting transistor X9.In addition, output line OUT 15 links to each other with the outlet side source electrode of selecting transistor X9, and by column shift register control, in order to produce output.

In solid imaging device according to present embodiment, photodiode PDa1, PDb1 ', PDc1 among the pixel of remarked pixel piece " a " and " b " " and PDd1 , overflow a LOa4, LOb4', LOc4 " and LOd4  and holding capacitor CSa5, CSb5', CSc5 " and the schematic section in the zone of CSd5  and Fig. 8 A among first embodiment shown in similar; therefore for fear of repetition, omit describing to this figure.In addition, with photodiode PDa1, PDb1 ', the PDc1 in the pixel " and PDd1 , transfering transistor Ta2, Tb2', Tc2 " and Td2 , floating region FD3, memory transistor Sa7, Sb7 ', Sc7 " and Sd7  and holding capacitor CSa5, CSb5', CSc5 " and Fig. 8 B of the schematic section of regional corresponding this solid imaging device of CSd5  and first embodiment shown in similar, therefore also omit describing to it.

Herein, description is according to the method for operation of the solid imaging device of the present embodiment shown in Figure 25 and 26.Figure 27 is the driving timing figure according to the solid imaging device of present embodiment.In each block of pixels, when wanting read pixel " a ", " b ", " c " and " d ",, carry out and read by using identical floating region FD, amplifier transistor SF, reset transistor R and selecting transistor X.

At first, before exposure storage, the memory transistor Sa of pixel " a " is set to conducting, and transfering transistor Ta and reset transistor R are set to end.At this moment, the photodiode PD of pixel " a " is in complete spent condition.

Next, turns on reset transistor R is in order to the floating region FD and the holding capacitor CSa (time: t of reset of pixels " a " ₁).Then, read the reset noise of (FD+CSa) that after reset transistor R, catch immediately, as the noise signal N2 (time: t ₂).Herein, noise signal N2 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).

(the time: t during the memory time section ₃), the optical charge by photodiode PDa storage before saturated, and through overflowing a LOa the excessive optical charge when saturated is stored among the holding capacitor CSa.This operation makes can use the electric charge that overflows photodiode PD effectively, and does not abandon these electric charges.In this manner, before saturated and in the time period afterwards, in identical memory time section,, carry out storage operation by receiving light by identical photodiode PD for each pixel.

(the time: t after finishing storage ₄), transistor X is selected in conducting.Then, turns on reset transistor R is in order to the floating region FD (time: t that resets ₅), and read in the FD reset noise that resets and catch immediately afterwards, as the noise signal N1 (time: t ₆).Herein, noise signal N1 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise component(s).

Next, conducting transfering transistor Ta transfers to the floating region FD (time: t fully in order to the light signal that will be stored among the photodiode PD ₇), and signal is read as (S1+N1).Then, go back the conducting memory transistor Sa (time: t ₈), transfer to floating region FD and holding capacitor CSa fully in order to the optical charge that will be stored among the photodiode PDa; Electric charge among photodiode PDa, floating region FD and the holding capacitor CSa is mixed, and signal is read as (S1+S2+N1).Similarly in pixel " b ", before the exposure storage, memory transistor Sb is set to conducting, and transfering transistor Tb and reset transistor R are set to end.Next, turns on reset transistor R, in order to floating region FD and the holding capacitor CSb of resetting, and the reset noise of (FD+CSb) that catch immediately after reset transistor R is read as noise signal N2.Herein, noise signal N2 comprises the variations in threshold voltage of amplifier transistor SF, as fixing pattern noise signal.

(the time: t during the memory time section ₉), the optical charge by photodiode PDb storage before saturated, and through overflowing a LOb the excessive optical charge when saturated is stored among the holding capacitor CSb.(the time: t after finishing storage ₁₀), transistor X is selected in conducting.Then, turns on reset transistor R is in order to the floating region FD (time: t that resets ₁₁), and the FD reset noise of catching immediately after resetting is read as the noise signal N1 (time: t ₁₂).Next, conducting transfering transistor Tb transfers to the floating region FD (time: t fully in order to the light signal that will be stored among the photodiode PDb ₁₃), and signal is read as (S1+N1).Then, go back the conducting memory transistor Sb (time: t ₁₄), transfer to floating region FD and holding capacitor CSb fully in order to the optical charge that will be stored among the photodiode PDb.The electric charge that is stored among photodiode PDb, floating region FD and the holding capacitor CSb is mixed, and signal is read as (S1+S2+N2).About pixel " c " and " d ", repeat identical operations thereafter.

In solid imaging device, because floating region FD, amplifier transistor SF, reset transistor R are set and select transistor X, so can reduce the elemental area of each pixel with the ratio of one group of per four pixel according to present embodiment.

In aforesaid operations, the situation that drives the pixel that is arranged on the block of pixels place successively and use the signal that obtains from all pixels has been described.Yet, as sparse operation, can from each block of pixels, select pixel arbitrarily, so that use the signal that obtains from selected pixel.Alternatively, as average operation, can mix and increase the picture element signal in each block of pixels, in order to use this signal.

Except the ratio with one of per four pixel is provided with the output line, shown in Figure 10 identical according among the block diagram of the solid imaging device of present embodiment and first embodiment.Identical with described in first embodiment of the signal that pointwise is read from each pixel in the present embodiment, the amplification ratio of dynamic range and broad dynamic range signal synthetic.

The 7th embodiment

Solid imaging device according to present embodiment is an example of revising the holding capacitor that is used to store the optical charge that overflows photodiode in above-mentioned first to the 6th embodiment.

When view uses the junction type holding capacitor as holding capacitor, not very high situation even consider its area efficiency, every square of possible μ m electrostatic capacitance is at 0.3 to 3fF/ μ m ²Magnitude on, therefore be difficult to make dynamic range to broaden.

On the other hand, under the situation of plane holding capacitor, when the dielectric film electric field be set to 3 to 4MV/cm or still less, maximum apply voltage be set to 2.5 to 3V and the capacitor insulation film thickness be set to the magnitude of 7nm so that during the dielectric film leakage current of suppression capacitor dielectric film, for relative dielectric constant ε _r=3.9, electrostatic capacitance becomes 4.8fF/ μ m ², for ε _r=7.9, electrostatic capacitance becomes 9.9fF/ μ m ², for ε _r=20, electrostatic capacitance becomes 25fF/ μ m ², and for ε _r=50, electrostatic capacitance becomes 63fF/ μ m ²

Use so-called high k material, for example (ε except that silica _r: 3.9) also have silicon nitride (ε _r: 7.9)), Ta ₂O ₅(ε _r: about 20 to 30), HfO ₂(ε _r: about 30), ZrO ₂(ε _r: about 30) and La ₂O ₃(ε _r: about 40 to 50), make it possible to achieve bigger electrostatic capacitance, thereby, can realize having the imageing sensor of 100 to 200dB dynamic range even under the situation of plane holding capacitor with relative simple structure.

In addition, can be by suppressing the dynamic range that application that occupied area amplifies the structure of for example stack of area under the capacitor or plough groove type makes it possible to achieve 120dB, in addition, being used in combination above-mentioned high k material makes stack or plough groove type can realize the dynamic range of 140dB and 160dB respectively.

Below, the example of the holding capacitor that is applicable to the embodiment of the invention is shown.Figure 28 be with first embodiment in the sectional view of holding capacitor similar planar MOS holding capacitor.For example, this holding capacitor CS is configured to comprise: n+ N-type semiconductor N zone 60, as bottom electrode, be formed in the superficial layer of p type trap, and described p type trap is formed on the substrate 20; By the capacitor insulating film 42 that silica is formed, be formed on the n+ N-type semiconductor N zone 60; And, be formed on the capacitor insulating film 42 by the top electrode 43 that polysilicon etc. is formed.

Figure 29 shows the sectional view of plane MOS and junction type holding capacitor.For example, dispose this holding capacitor CS, make and to form integral body with n+ N-type semiconductor N zone 32 as the source/drain of memory transistor as the n+ N-type semiconductor N 61 of bottom electrode, wherein n+ N-type semiconductor N 61 is formed in the superficial layer of p type trap, and described p type trap is formed on the n N-type semiconductor N substrate 20; And through forms by silica, be arranged on the capacitor insulating film 42 on the n+ N-type semiconductor N zone 61, formation top electrode 43.Herein, supply voltage VDD or ground GND are provided for top electrode 43.

Holding capacitor shown in Figure 30 (sectional view) is and similar planar MOS holding capacitor shown in Figure 28.Yet with shown in Figure 28 different, in this holding capacitor, capacitor insulating film 42 is by for example silicon nitride or Ta ₂O ₅High k material constitute, and make electric capacity greater than electric capacity shown in Figure 28.

Holding capacitor shown in Figure 31 (sectional view) is and similar planar MOS shown in Figure 29 and junction type holding capacitor.Yet with shown in Figure 29 different, in this holding capacitor, capacitor insulating film 42a is by for example silicon nitride or Ta ₂O ₅High k material constitute, and make electric capacity greater than electric capacity shown in Figure 29.

Figure 32 shows the sectional view of stack holding capacitor.For example, this holding capacitor CS is configured to comprise: bottom electrode 63 is formed on the unit separating insulation film 62 that is arranged on the n N-type semiconductor N substrate 20; Capacitor insulating film 64 is formed on the bottom electrode 63; And top electrode 65, be formed on the capacitor insulating film 64.Herein, link to each other with bottom electrode 63 by wiring 45 as the n+ N-type semiconductor N zone 32 of the source/drain of memory transistor.In this case, supply voltage VDD or ground GND are provided for top electrode 65.

Figure 33 shows the sectional view of stack holding capacitor.For example, this holding capacitor CS is configured to comprise: bottom electrode 67 forms so that link to each other with the n+ N-type semiconductor N zone 32 of the source/drain that is used as memory transistor; Capacitor insulating film 68 is formed on the inwall of bottom electrode 67; And top electrode 69, form through capacitor insulating film 68, so that embed the inside of bottom electrode 67.Herein, supply voltage VDD or ground GND are provided for top electrode 69.The structure that forms the top electrode 69 of being convenient to embed bottom electrode 67 and bottom electrode 67 inside can be bigger than common stack in the relative area that forms electrostatic capacitance.

Figure 34 shows the sectional view of the compound holding capacitor that obtains by combined planar type and stack.According to this example, can form big electric capacity with high area efficiency.

Figure 35 shows the sectional view of plough groove type holding capacitor.This holding capacitor CS is configured to comprise: groove TC forms so that the p type trap 21 that passes on the n N-type semiconductor N substrate 20 arrives n N-type semiconductor N substrate 20; N+ N-type semiconductor N zone 70 as bottom electrode is formed on the inwall of groove TC; Capacitor insulating film 71 forms so that cover the inwall of TC; And top electrode 72, form so that embed groove TC through capacitor insulating film 71.Herein, 45 link to each other by connecting up as the n+ N-type semiconductor N zone 32 of the source/drain of holding capacitor and top electrode 72.

Figure 36 shows the sectional view of the plough groove type holding capacitor with knot.Dispose this holding capacitor CS, make to form groove TC in the p type trap 21 on n N-type semiconductor N substrate 20; In the inwall of groove TC, form integral body with n+ N-type semiconductor N zone 32 as the source/drain of holding capacitor as the n+ N-type semiconductor N zone 73 of bottom electrode; Form capacitor insulating film 74, so that cover the inwall of TC; And form top electrode 75, so that embed groove TC through capacitor insulating film 74.

Figure 37 shows the sectional view of plough groove type holding capacitor.This holding capacitor CS is configured to comprise: groove TC forms so that the p type trap 21 that passes on the n N-type semiconductor N substrate 20 arrives n N-type semiconductor N substrate 2; N+ N-type semiconductor N zone 76 as bottom electrode is formed on the inwall of groove TC, in the zone darker than the degree of depth of groove TC; Capacitor insulating film 77 forms so that cover the inwall of TC; And top electrode 78, form so that embed groove TC through capacitor insulating film 77.Herein, 45 link to each other by connecting up as the n+ N-type semiconductor N zone 32 of the source/drain of memory transistor and top electrode 78.

Figure 38 shows the sectional view of plough groove type holding capacitor.This holding capacitor is configured to comprise: groove TC forms so that the p type trap 21 that passes on the n N-type semiconductor N substrate 20 arrives n N-type semiconductor N substrate 20; P+ N-type semiconductor N zone 79 as bottom electrode is formed on the inwall of groove TC; Capacitor insulating film 80 forms so that cover the inwall of TC; And top electrode 81, form so that embed groove TC through capacitor insulating film 80.Herein, 45 link to each other by connecting up as the n+ N-type semiconductor N zone 32 of the source/drain of memory transistor and top electrode 81.

Figure 39 shows the sectional view of the cmos sensor with the embedded holding capacitor that uses junction capacitor.For example, on p type Si semiconductor (p-sub) 90, form p type epitaxial loayer 91, and cross over p type Si semiconductor 90 and p type epitaxial loayer 91, form n+ N-type semiconductor N zone 92.That is, in conjunction with n type (first conduction type) semiconductor regions and p type (second conduction type) semiconductor regions is embedded in the Semiconductor substrate that constitutes solid imaging device the calm embedded holding capacitor that uses junction capacitor that forms.In addition, in p type Si semiconductor (p-sub) 90 and p type epitaxial loayer 91, form p+ type separated region 93.On p type epitaxial loayer 91, form p type silicon semiconductor layer 94.Identical with the situation of the foregoing description, about p type silicon semiconductor layer 94, be provided with photodiode PD, overflow a LO, transfering transistor T, floating region FD and memory transistor S.For example, forming the n+ N-type semiconductor N zone 92 that forms widely on the zone (be above-mentioned photodiode PD, overflow a LO, transfering transistor T, floating region FD and memory transistor S) as holding capacitor SC.In addition, n+ N-type semiconductor N zone 32 links to each other with the n+ N-type semiconductor N zone 92 that constitutes holding capacitor by vertically extending n+ N-type semiconductor N zone 95 in p type silicon semiconductor layer 94.

Figure 40 shows the sectional view of the cmos sensor with the embedded holding capacitor that uses capacitance insulation film device and junction capacitor.This transducer has and similar structure shown in Figure 39.Yet, in this transducer, go up formation the one p type epitaxial loayer 91a and the 2nd p type epitaxial loayer 91b through dielectric film 90a in p type silicon semiconductor layer 90 (p-sub), thereby constitute SOI (semiconductor-on-insulator) substrate, make on Semiconductor substrate, to form semiconductor layer through dielectric film.Herein, in the zone that has a common boundary, passes through a p type epitaxial loayer 91a and the 2nd p type epitaxial loayer 91b with dielectric film 90a, form n+ N-type semiconductor N zone 92, and use about the dielectric film of centre and the dielectric film between Semiconductor substrate respect to one another and the semiconductor layer forms holding capacitor.In addition, identical with the situation of the holding capacitor of Figure 39, between a p type epitaxial loayer 91a and the 2nd p type epitaxial loayer 91b, form junction capacitor.Other structure is identical with cmos sensor shown in Figure 39.

Figure 41 is the sectional view with cmos sensor of the embedded holding capacitor that uses capacitance insulation film device and junction capacitor.This transducer has the similar structure of Figure 40.Yet, in this transducer, between the n+ N-type semiconductor N zone 92 of n N-type semiconductor N zone 30 that constitutes photodiode PD and formation holding capacitor, form low concentration semiconductor layer (i type) 96.This structure has reduced the potential barrier between n N-type semiconductor N zone 30 and the n+ N-type semiconductor N zone 92, has constituted the overflow path from photodiode PD to holding capacitor CS.The electric charge break-through that should feasible overflow photodiode PD, thus during charge storage, electric charge is moved to holding capacitor CS smoothly.

Above-mentioned various holding capacitor is applicable to any one of above-mentioned first to the 7th embodiment.As mentioned above, one of holding capacitor that has this shape by use is stored the optical charge that overflows photodiode, can realize widening of dynamic range in high illumination side.

Example 1

In solid imaging device according to the present invention,, make the solid imaging device unit according to method for making semiconductor with the wiring of two-layer polysilicon and three-layer metal.Herein, the solid imaging device unit has the pixel of arranging according to two-dimensional matrix, and condition is: number of pixels: 640 (OK) * 480 (row); Pixel size 7.5 μ m ²The floating region capacitor C _FD=4fF; Storage capacitance C _CS=60fF.Each holding capacitor is made up of shunt capacitor, i.e. polysilicon-silica mould-silicon capacitor and polysilicon-silicon nitride mould-polysilicon capacitor.Signal S1 and saturation voltage (S1+S2) are respectively 500mV and 1000mV.After the noise remove in S1 and (S1+S2) residual residual noise voltage be identical value 0.09mV.Switched voltage from S1 to (S1+S2) is set to 400mV, is lower than the saturation voltage of signal S1.

Signal (S1+S2) is higher than 40dB with the S/N ratio of the residual noise at each switching point place, thereby can realize having the solid imaging device of high image quality.Obtain the dynamic range of 100dB.In addition, during utilizing high illumination rayed, can transfer to holding capacitor effectively by overflowing the excessive optical charge that a LO will overflow photodiode PD, make that can suppress excessive optical charge leaks into neighbor, cause the anti-ambiguity (blooming resistance) and the anti-hangover property (smearing resistance) that strengthen.

In this example 1, can when keeping high S/N ratio, realize widening of dynamic range in high illumination side.

Example 2

In solid imaging device according to the present invention, by (number of pixels: 640 (OK) * 240 (row)) the arrangement block of pixels is made solid imaging device according to two-dimensional matrix.By on base pixel piece, arranging photodiode and holding capacitor by twos, constitute each block of pixels herein, with 7 μ m (length) * 3.5 μ m (wide) size.The valid pixel number is 640 (OK) * 480 (row).In each block of pixels, by using plough groove type storage capacitor structures, floating region capacitor C _FDBe set to 3.4fF, storage capacitance C _CSBe set to 100fF.Signal S1 and saturation voltage (S1+S2) are respectively 500mv and 1000mV.After the noise remove in S1 and (S1+S2) residual residual noise voltage be identical value 0.09mV.Switched voltage from S1 to (S1+S2) is set to 400mV, is lower than the saturation voltage of signal S1.

Signal (S1+S2) is higher than 40dB with the S/N ratio of the residual noise at each switching point place, thereby can realize having the solid imaging device of high image quality.Obtain the dynamic range of 110dB.In addition, during utilizing high illumination rayed, can transfer to holding capacitor effectively by overflowing the excessive optical charge that a LO will overflow photodiode PD, make that can suppress excessive optical charge leaks into neighbor, cause the anti-ambiguity (blooming resistance) and the anti-hangover property (smearing resistance) that strengthen.

In this example 2, can when keeping high S/N ratio, realize widening of dynamic range in high illumination side.

Should be understood that the present invention is not limited to the foregoing description.For example, the present invention is not limited to the solid imaging device that is applied among the embodiment; It can be applied to arrange linearly the line sensor of the pixel in each solid imaging device, perhaps be applied to and constitute the optical pickocff that pixel obtains by independent in each solid imaging device, thereby can realize the dynamic range and the high S/N of non-constant width.

In addition, do not limit the shape etc. of holding capacitor especially.Electric capacity for the holding capacitor that increases DRAM (dynamic random access memory) etc. can use the whole bag of tricks of having developed up to now.Structure according to solid imaging device of the present invention is unrestricted, as long as photodiode links to each other through overflowing door with the holding capacitor that is used to store the optical charge that overflows photodiode.Except that cmos image sensor, also be applicable to CCD according to solid imaging device of the present invention.In addition, under the situation that does not break away from the spirit and scope of the present invention, certainly carry out various changes and modification of the present invention.

Imageing sensor be can be applied to require according to solid imaging device of the present invention, digital camera, camera phone, surveillance camera, airborne video camera, scanner etc. are used for than wide dynamic range.

Can be applied to require method of operation according to the method for operation of solid imaging device of the present invention than the imageing sensor of wide dynamic range.

Claims

1. optical pickocff comprises:

Photodiode receives light and produces optical charge;

Overflow door, be coupled, and during storage operation, shift the optical charge that overflows photodiode with photodiode; And

Storage capacitor cells, storage is by overflowing the optical charge of a transfer during storage operation.

2. optical pickocff according to claim 1 also comprises: transfering transistor, be coupled with photodiode and floating region, and wherein, transfering transistor is transferred to floating region with optical charge from photodiode.

3. optical pickocff according to claim 1, wherein:

Overflowing door is made of junction transistor; And

The semiconductor regions that forms the grid of junction transistor links to each other with the well region that overflows door with the semiconductor regions of the surface region that forms photodiode and with the formation photodiode.

4. optical pickocff according to claim 1, wherein:

The desired depth place that has formed the substrate that overflows door therein forms overflows door; And

Overflow the semiconductor layer that door has and overflow the raceway groove identical conduction type of door, described semiconductor layer reduces potential barrier so that break-through in overflowing door.

5. optical pickocff according to claim 1, wherein, storage capacitor cells comprises:

Semiconductor regions as bottom electrode is formed in the surface layer part of the Semiconductor substrate that has wherein formed optical pickocff;

Capacitor insulating film is formed on the semiconductor regions; And

Top electrode is formed on the capacitor insulating film.

6. optical pickocff according to claim 1, wherein, storage capacitor cells comprises:

Bottom electrode is formed on the substrate that has wherein formed optical pickocff;

Capacitor insulating film is formed on the bottom electrode; And

Top electrode is formed on the capacitor insulating film.

7. optical pickocff according to claim 1, wherein, storage capacitor cells comprises:

Semiconductor regions as bottom electrode is formed in the inwall of groove, and described groove forms and formed therein in the Semiconductor substrate of optical pickocff;

Capacitor insulating film is formed on the inwall of groove; And

Top electrode is formed on the capacitor insulating film and embeds groove.

8. a solid imaging device comprises a plurality of pixels of arranging according to one dimension or two-dimensional matrix, and wherein each pixel has optical pickocff according to claim 1 and 2.

9. solid imaging device according to claim 8 wherein, overflows door and is made of MOS transistor or junction transistor.

10. a solid imaging device comprises a plurality of block of pixels,

Each of described a plurality of block of pixels comprises a plurality of pixels and single floating region,

Each of described a plurality of pixels comprises:

Photodiode receives light and produces optical charge;

Overflow door, be coupled, and during storage operation, shift and overflow with photodiode

The optical charge of photodiode;

Storage capacitor cells, storage is by overflowing the light of a transfer during storage operation

Electric charge; And

Transfering transistor is coupling between photodiode and the single floating region.

11. solid imaging device, comprise a plurality of pixels, each pixel has optical pickocff according to claim 2, wherein, transfering transistor is to imbed channel transistor, have with the raceway groove identical conduction type of transfering transistor, from the surface of the substrate that wherein formed transfering transistor or near surface up to the formed semiconductor layer of desired depth.

12. solid imaging device according to claim 10, wherein, transfering transistor is to imbed channel transistor, have with the raceway groove identical conduction type of transfering transistor, from the surface of the substrate that wherein formed transfering transistor or near surface up to the formed semiconductor layer of desired depth.

13. a solid imaging device comprises a plurality of pixels, each pixel has optical pickocff according to claim 2, and described solid imaging device also comprises:

Reset transistor is coupled with floating region, is used for discharging the signal charge of storage capacitor cells and floating region;

Transistor is arranged between floating region and the storage capacitor cells;

Amplifier transistor is used for reading the signal charge in floating region or floating region and the storage capacitor cells, as voltage;

Select transistor, be coupled, be used to select pixel with amplifier transistor.

14. solid imaging device according to claim 10 also comprises:

Transistor is arranged between floating region and the storage capacitor cells;

15. a solid imaging device comprises a plurality of pixels, each pixel has optical pickocff according to claim 2, and described solid imaging device also comprises:

Reset transistor is coupled with storage capacitor cells, is used for discharging the signal charge of storage capacitor cells and floating region;

Transistor is arranged between floating region and the storage capacitor cells;

16. solid imaging device according to claim 10 also comprises:

Transistor is arranged between floating region and the storage capacitor cells;

17. a solid imaging device comprises a plurality of pixels, each pixel has optical pickocff according to claim 2, and described solid imaging device also comprises:

Noise cancelling arrangement is used to obtain the difference between following two voltage signals:

From transferring to floating region or transferring to floating region and the voltage signal that optical charge obtained of storage capacitor cells;

The voltage signal at the reset level place of floating region or floating region and storage capacitor cells.

18. solid imaging device according to claim 10 also comprises:

19. solid imaging device according to claim 17 also comprises: storage device is used for storing the voltage signal at floating region and storage capacitor cells reset level place.

20. solid imaging device according to claim 18 also comprises: storage device is used for storing the voltage signal at floating region and storage capacitor cells reset level place.

21. the method from the optical pickocff output signal that comprises photodiode and storage capacitor cells comprises step:

Before photodiode is saturated, store first optical charge that photodiode produced into photodiode;

After saturated, store second optical charge that photodiode produced into storage capacitor cells; And

According to first and second optical charges, come output signal.

22. optical pickocff according to claim 1 wherein, overflows door and is made of the MOS transistor that is coupling between photodiode and the holding capacitor, the gate electrode of MOS transistor receives the signal of determining storage operation.