JP2006217410A5 - - Google Patents

Description

Optical sensor and solid-state imaging device

  The present invention relates to an optical sensor and a solid-state imaging device, and more particularly to a CMOS or CCD type two-dimensional or one-dimensional solid-state imaging device and a method for operating the solid-state imaging device.

  Image sensors such as CMOS (Complementary Metal-Oxide-Semiconductor) image sensors or CCD (Charge Coupled Device) image sensors have been widely used in applications such as digital cameras, mobile phones with cameras, and scanners, along with their improved characteristics. .

  The above-mentioned image sensor is desired to further improve the characteristics, and one of them is to widen the dynamic range. The dynamic range of image sensors used in the past is, for example, about 3 to 4 digits (60 to 80 dB), and the dynamic range of 5 to 6 digits (100 to 120 dB) or more comparable to the naked eye or a silver salt film. Realization of a high-quality image sensor is desired.

  As a technique for improving the image quality characteristics of the above image sensor, for example, in Non-Patent Document 1 or the like, in order to achieve high sensitivity and high S / N ratio, a noise signal generated in a floating diffusion adjacent to the photodiode of each pixel and the relevant A technique for suppressing noise by reading out a signal obtained by adding an optical signal to a noise signal and taking the difference between the two has been developed. However, even with this method, the dynamic range is about 80 dB or less, and it is desired to have a wider dynamic range.

  For example, in Patent Document 1, as shown in FIG. 37, a low-illuminance low-illuminance side small diffusion C1 floating diffusion and a low-sensitivity high-illuminance large capacitance C2 floating diffusion are connected to a photodiode PD. A technique for widening the dynamic range by outputting the output OUT1 on the side and the output OUT2 on the high illuminance side is disclosed.

  Patent Document 2 discloses a wide dynamic range technique in which the capacitance CS of the floating diffusion FD is variable as shown in FIG. In addition, there is disclosed a technique for widening the dynamic range by dividing an exposure time corresponding to a high illuminance side with a short exposure time and an exposure time of two or more different times corresponding to low illuminance with a long exposure time.

  Further, in Patent Document 3 and Non-Patent Document 2, as shown in FIG. 39, a transistor switch T is provided between the photodiode PD and the capacitor C, and the switch T is turned on in the first exposure period to turn on the optical signal charge. Is stored in both the photodiode PD and the capacitor C, the switch T is turned off at the second exposure time, and the photocharge is stored in the photodiode PD in addition to the former stored charge, thereby widening the dynamic range. It is disclosed. Here, it is disclosed that when there is light irradiation exceeding saturation, excess charge is discharged through the reset transistor R.

  Further, as shown in FIG. 40, Patent Document 4 discloses a technique that can cope with high-illuminance imaging by using a photodiode PD having a larger capacitance C than conventional ones.

  In Non-Patent Document 3, as shown in FIG. 41, a photocurrent signal from a photodiode PD is accumulated and output while logarithmically converting it by a logarithmic conversion circuit configured by combining MOS transistors. A technique for widening the dynamic range is disclosed.

JP 2003-134396 A JP 2000-165754 A JP 2002-77737 A JP-A-5-90556 S. Inoue et al., IEEE Workshop on CCDs and Advanced Image Sensor 2001, pp.16-19. Y. Muramatsu et al., IEEE Journal of Sold-state Circuits, Vol.38, No.1, 2003. The Journal of the Institute of Image Information and Media Studies, Vol. 57, 2003.

  However, in the method described in Patent Documents 1, 2, 3 and Non-Patent Document 2 described above, or the method of imaging with different exposure times of two or more, low-illuminance imaging and high-illuminance side imaging are performed at different times. As a result, there is a problem in that the imaging time varies and the image quality of moving image imaging is impaired.

  In addition, the methods described in Patent Document 4 and Patent Document 3 can achieve a wide dynamic range so as to correspond to imaging on the high illuminance side, but have low sensitivity and low S / N for imaging on the low illuminance side. There is a problem that the image quality is deteriorated.

  As described above, in an image sensor such as a CMOS image sensor, it has been difficult to achieve a wide dynamic range while maintaining high sensitivity and a high S / N ratio. The above is not limited to an image sensor in which pixels are arranged in a two-dimensional array, and the same applies to a linear sensor in which pixels are arranged one-dimensionally or an optical sensor that does not have a plurality of pixels.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of widening a dynamic range while maintaining high sensitivity and a high S / N ratio, and an operation method thereof. That is.
Another object of the present invention is to provide an optical sensor and / or a solid-state imaging device capable of smoothly moving charges from a photodiode to a storage capacitor during charge accumulation .

  In order to achieve the above object, an optical sensor according to the present invention includes a photodiode that receives light and generates a photoelectric charge, and an overflow gate that is connected to the photodiode and transfers a photoelectric charge that overflows from the photodiode during an accumulation operation. And a storage capacitor element that stores the photocharge transferred by the overflow gate during the storage operation.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a photodiode that receives light to generate a photocharge, and an overflow that is connected to the photodiode and transfers a photocharge overflowing from the photodiode during an accumulation operation. A plurality of pixels each including a gate and a storage capacitor element that stores the photocharge transferred by the overflow gate during the storage operation are integrated in a one-dimensional or two-dimensional array.

  In the solid-state imaging device according to the present invention, preferably, the pixel is connected to the photodiode and transfers the photocharge, and a floating region to which the photocharge is transferred via the transfer transistor. And further.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a photodiode that receives light to generate a photocharge, a transfer transistor that is connected to the photodiode and transfers the photocharge, and a photodiode. A plurality of pixels each having an overflow gate that is connected and transfers a photoelectric charge overflowing from the photodiode during a storage operation, and a storage capacitor element that stores a photoelectric charge transferred by the overflow gate during a storage operation; A plurality of pixel blocks each having one floating region connected to each photodiode via each transfer transistor are integrated in a one-dimensional or two-dimensional array.

  The solid-state imaging device according to the present invention preferably includes a reset transistor connected to the floating region for discharging the storage capacitor and a signal charge in the floating region, and between the floating region and the storage capacitor. And a transistor for reading out the signal charge of the floating region or the signal charge of both the floating region and the storage capacitor as a voltage, and selecting the pixel connected to the amplifier transistor And a selection transistor.

  The solid-state imaging device according to the present invention is preferably connected to the storage capacitor, and is configured to discharge a signal charge in the storage capacitor and the floating region. The floating region and the storage A transistor provided between the capacitor, an amplification transistor for reading out the signal charge of the floating region or the signal charge of both the floating region and the storage capacitor as a voltage, and the pixel connected to the amplification transistor And a selection transistor for selecting.

  In the solid-state imaging device according to the present invention, preferably, the overflow gate is formed of a MOS transistor or a junction transistor.

  In the solid-state imaging device of the present invention, preferably, the overflow gate is formed of a junction transistor, and a semiconductor region that forms the gate of the junction transistor includes a semiconductor region that forms a surface region of the photodiode; And a well region where the photodiode and the overflow gate are formed.

  In the solid-state imaging device according to the present invention, preferably, the transfer transistor is a semiconductor having the same conductivity type as the channel of the transfer transistor formed from the surface of the substrate constituting the transfer transistor or near the surface to a predetermined depth. It is a buried channel type having a layer.

  In the solid-state imaging device of the present invention, preferably, the overflow gate is formed at a predetermined depth of a substrate constituting the overflow gate, and has the same conductivity type as the channel of the overflow gate, and the overflow gate A semiconductor layer that reduces a punch-through barrier.

  In the above-described solid-state imaging device of the present invention, preferably, the storage capacitor element is formed on the semiconductor region as a lower electrode formed on a surface layer portion of a semiconductor substrate constituting the solid-state imaging device, and on the semiconductor region A capacitive insulating film, and an upper electrode formed on the capacitive insulating film.

  In the above-described solid-state imaging device of the present invention, preferably, the storage capacitor element has a lower electrode formed on a substrate constituting the solid-state imaging device, a capacitive insulating film formed on the lower electrode, And an upper electrode formed on the capacitor insulating film.

  In the solid-state imaging device of the present invention, preferably, the storage capacitor element is a semiconductor region serving as a lower electrode formed on an inner wall of a trench formed in a semiconductor substrate constituting the solid-state imaging device, and the trench A capacitor insulating film formed so as to cover the inner wall, and an upper electrode formed by embedding the trench through the capacitor insulating film.

  The solid-state imaging device of the present invention preferably includes a voltage signal obtained from a photocharge transferred to both the floating region or the floating region and the storage capacitor element, and the floating region or the floating region and Noise cancellation means for taking a difference between the reset level voltage signals of both the storage capacitor elements is further included.

The solid-state imaging device of the present invention preferably further includes storage means for storing a voltage signal at a reset level of the floating region and the storage capacitor element.
According to another aspect of the present invention, a photodiode that receives light to generate a photocharge, an overflow gate that is connected to the photodiode and transfers a photocharge overflowing from the photodiode during a storage operation, and a storage operation A storage capacitor element that stores the photoelectric charge transferred by the overflow gate; and a region that lowers a potential barrier between the photodiode and the storage capacitor element between the photodiode and the overflow gate. An optical sensor characterized by this can be obtained.
According to another aspect of the present invention, a photodiode that receives light to generate a photocharge, an overflow gate that is connected to the photodiode and transfers a photocharge overflowing from the photodiode during a storage operation, and a storage operation A storage capacitor element that stores the photocharge transferred by the overflow gate, and a potential region that lowers a potential barrier between the photodiode and the storage capacitor element between the photodiode and the overflow gate. A solid-state imaging device is obtained in which a plurality of pixels are integrated in a one-dimensional or two-dimensional array.
The overflow gate has a gate region formed by a reverse conductivity type semiconductor region formed on a surface of a one conductivity type semiconductor region, and the potential region is formed by the one conductivity type semiconductor region. Yes.
In this case, the photodiode is formed by a junction transistor, and includes a first region of the one conductivity type and a gate region of a reverse conductivity type provided on the first region, and the overflow gate is the gate The potential region is formed below the overflow semiconductor region, and is formed of a one conductivity type semiconductor region.
The potential region may be formed to partially overlap the first region and the gate region in the depth direction.
Further, the potential region may include a portion connected to the first region at a predetermined depth, and the potential region extends beyond the gate region at a predetermined depth position. May be .

  According to the solid-state imaging device of the present invention, high sensitivity and high S / N ratio are maintained in low-illuminance imaging by a photodiode that receives light and generates and accumulates photocharges, and further, the photodiode is connected to the storage capacitor through an overflow gate. By accumulating the photoelectric charge overflowing from the image, it is possible to perform imaging at high illuminance and widen the dynamic range.

  Hereinafter, embodiments of a solid-state imaging device of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 shows an equivalent circuit diagram of one pixel of a solid-state imaging device according to this example, and FIG. 2 shows a schematic plan view thereof.

  Each pixel receives light and generates and accumulates photocharges, a transfer transistor T2 for transferring photocharges provided adjacent to the photodiode PD1, and a photodiode PD1 via the transfer transistor T2. A floating region (floating diffusion) FD3 provided in connection with, and an overflow gate LO4 for transferring photocharge provided adjacent to the photodiode PD1 for transferring photocharge overflowing from the photodiode PD1 during the accumulation operation, The storage capacitor CS5 for storing the photoelectric charge overflowing from the photodiode PD1 during the storage operation through the overflow gate LO4 and the floating diffusion FD3 are connected to the storage capacitor CS5 and the floating diffusion FD3. The reset transistor R6 for discharging the signal charge in the FD3, the storage transistor S7 provided between the floating diffusion FD3 and the storage capacitor CS5, the signal charge of the floating diffusion FD3 or the signal charge of the floating diffusion FD3 and the storage capacitor CS5 Is composed of an amplifying transistor SF8 for reading as a voltage, and a selection transistor X9 provided in connection with the amplifying transistor for selecting the pixel or pixel block.

In the solid-state imaging device according to this embodiment, a plurality of pixels having the above-described configuration are integrated in a two-dimensional or one-dimensional array, and in each pixel, an overflow gate LO4, a transfer transistor T2, a storage transistor S7, and a reset transistor. The driving lines of φ _LO 10, φ _T 11, φ _S 12, and φ _R 13 are connected to the gate electrode of R6, and the pixel selection line φ driven from the row shift register is connected to the gate electrode of the selection transistor X9. _X 14 is connected, and further, an output line OUT 15 is connected to the output side source of the selection transistor _X 9, which is controlled by the column shift register and output.

Selection transistors X9, the driveline phi _X 14 is selected pixels, as can non-selecting operation, because it is sufficient fixing the voltage of the floating diffusion FD3 to appropriate values, it is also possible to omit them.

  FIG. 3A is a schematic cross-sectional view corresponding to the photodiode PD1, overflow gate LO4, and storage capacitor CS5 of the pixel of the solid-state imaging device according to the present embodiment, and FIG. 3-2 illustrates the pixel photodiode. FIG. 4 is a schematic cross-sectional view corresponding to PD1, a transfer transistor T2, a floating diffusion FD3, a storage transistor S7, and a storage capacitor CS5.

  For example, a p-type well (p-well) 21 is formed in an n-type silicon semiconductor substrate (n-sub) 20, and an element isolation insulating film (22, 22) by a LOCOS method or the like that separates each pixel and the storage capacitor CS region. 23, 24, 25) are formed, and p + type isolation regions (26, 27, 28, 29) are formed in the p type well 21 corresponding to the lower part of the element isolation insulating film for isolating the pixels. . An n-type semiconductor region 30 is formed in the p-type well 21, and a p + -type semiconductor region 31 is formed on the surface layer thereof. A charge transfer embedded photodiode PD is constituted by this pn junction. When light LT is incident on a depletion layer generated by applying an appropriate bias to the pn junction, a photoelectric charge is generated by the photoelectric effect.

  There is a region formed so as to protrude from the p + type semiconductor region 31 at the end of the n type semiconductor region 30, and an n + type semiconductor region 32 is formed on the surface layer of the p type well 21 at a predetermined distance from this region. Yes.

  There is another region formed at the end of the n-type semiconductor region 30 so as to protrude from the p + -type semiconductor region 31. The floating diffusion FD and the surface layer of the p-type well 21 are separated from this region by a predetermined distance. The n + type semiconductor region 33 is formed, and the n + type semiconductor region 34 is formed at a predetermined distance from this region.

  Here, in a region related to the n-type semiconductor region 30 and the n + -type semiconductor region 32, a gate electrode 36 made of polysilicon or the like is formed on the upper surface of the p-type well 21 via a gate insulating film 35 made of silicon oxide or the like. An overflow gate LO having a channel formation region on the surface layer of the p-type well 21 is formed using the type semiconductor region 30 and the n + type semiconductor region 32 as the source / drain.

  Further, in a region related to the n-type semiconductor region 30 and the n + -type semiconductor region 33, a gate electrode 38 made of polysilicon or the like is formed on the upper surface of the p-type well 21 via a gate insulating film 37 made of silicon oxide or the like. A transfer transistor T having the semiconductor region 30 and the n + -type semiconductor region 33 as a source / drain and having a channel formation region in the surface layer of the p-type well 21 is configured.

  Further, in a region related to the n + -type semiconductor region 33 and the n + -type semiconductor region 34, a gate electrode 40 made of polysilicon or the like is formed on the upper surface of the p-type well 21 via a gate insulating film 39 made of silicon oxide or the like. A storage transistor S having a semiconductor region 33 and an n + -type semiconductor region 34 as a source / drain and having a channel formation region in the surface layer of the p-type well 21 is formed.

  Further, in a region divided by the element isolation insulating films (23, 24), a p + type semiconductor region 41 serving as a lower electrode is formed on the surface layer of the p type well 21, and a capacitive insulation made of silicon oxide or the like is formed on the upper layer. An upper electrode 43 made of polysilicon or the like is formed through the film 42, and a storage capacitor CS is formed from these.

  An insulating film 44 made of silicon oxide or the like is formed so as to cover the overflow gate LO, the transfer transistor T, the storage transistor S, and the storage capacitor CS. The n + type semiconductor region 32, the n + type semiconductor region 33, and the n + type semiconductor region. 34 and an opening reaching the upper electrode 43 are formed, and a wiring 45 connecting the n + type semiconductor region 32 and the upper electrode 43 and a wiring 46 connecting to the n + type semiconductor region 33 are formed.

A drive line φ _T is connected to the gate electrode 38 of the transfer transistor T, and a drive line φ _S is connected to the gate electrode 40 of the storage transistor S.

A drive line φ _LO is connected to the gate electrode 36 of the overflow gate LO. A drive pulse signal may be applied to the drive line _φLO , but it may be connected to the same zero potential as the p-type well 21. The threshold voltage of the overflow gate LO is set to a value lower than the threshold voltage of the transfer transistor T so that excess charge exceeding the saturation of the photodiode PD can efficiently flow to the storage capacitor CS through the overflow gate LO. Further, when the threshold voltage of the overflow gate LO and the transfer transistor T is made the same, if the potential of the overflow gate LO is set higher than zero potential, excess charge exceeding the saturation of the photodiode PD is stored through the overflow gate LO. It is possible to efficiently flow to CS.

For the reset transistor R, the amplification transistor SF, the selection transistor X, the drive lines (φ _R , φ _X ), and the output line OUT, which are the other elements, for example, the wiring 46 is connected to the amplification transistor SF (not shown). 1 is configured in a region (not shown) on the semiconductor substrate 20 shown in FIGS. 3A and 3B so as to have the configuration shown in the equivalent circuit diagram of FIG.

The photodiode PD constitutes a relatively shallow potential capacitor _CPD , and the floating diffusion FD and the storage capacitor CS constitute relatively deep potential capacitors (C _FD , C _CS ).

  An operation method of the solid-state imaging device according to this embodiment described with reference to FIGS. 1, 2, 3-1, and 3-2 will be described. FIG. 4 is a drive timing chart of the solid-state imaging device of the present embodiment.

First, before exposure accumulation, the accumulation transistor S is turned on, and the transfer transistor T and the reset transistor R are turned off. At this time, the photodiode PD is completely depleted. Next, the reset switch R is turned on to reset the floating diffusion FD and the storage capacitor CS (time t ₁ ), and then the FD + CS reset noise taken immediately after the reset transistor R is turned off is read as the noise signal N2 ( Time t ₂ ). At this time, the threshold voltage variation of the amplification transistor SF is included in the noise signal N2 as a fixed pattern noise component. During the accumulation period (time t ₃ ), with the accumulation transistor S, the transfer transistor T, the reset transistor R, and the selection transistor X turned off, photocharge before saturation is accumulated in the photodiode PD and exceeds saturation. The excess photocharge at that time is stored in the storage capacitor CS via the overflow gate LO. By this operation, the charge overflowing from the photodiode PD in the oversaturated state is effectively utilized without being discarded. In this manner, the accumulation operation is performed by receiving light within the same period with the same photodiode PD for each pixel before and after saturation.

After the accumulation is completed (time t ₄ ), the selection transistor X is turned on, and then the reset transistor is turned on to reset the floating diffusion FD unit (time t ₅ ). The FD reset noise captured immediately after the reset is a noise signal. Read as N1 (time t ₆ ). At this time, the noise signal N1 includes a variation in threshold voltage of the amplification transistor SF as a fixed pattern noise component.

Next, the transfer transistor T is turned on to completely transfer the optical signal accumulated in the photodiode PD to the FD (time t ₇ ), and the signal is read as S1 + N1. Next, the storage transistor S is also turned on, and the signal charge stored in the photodiode PD is completely transferred to the floating diffusion FD and the storage capacitor CS (time t ₈ ), and stored in the photodiode PD, the floating diffusion FD, and the storage capacitor CS. The mixed charges are mixed and a signal is read as S1 + S2 + N2.

  FIG. 5 shows a block diagram of the solid-state imaging device of the present embodiment. A row shift register 104, a column shift register 105, a signal and noise hold unit 106, and an output circuit 107 are provided in the periphery of the pixel array (100, 101, 102, 103) arranged two-dimensionally. Here, a pixel array of 2 pixels × 2 pixels is shown for simplicity, but the number of pixels is not limited to this.

  Signals read out in a dot-sequential manner from each pixel are the noise signal N1 and the pre-saturation optical signal that has undergone charge-voltage conversion with the FD + noise signal S1 + N1, and the pre-saturation and post-saturation signals that have undergone charge-voltage conversion with the noise signals N2 and FD + CS The added optical signal + noise signal S1 + S2 + N2. The subtraction circuit performs the operation of noise removal before saturation (S1 + N1) −N1 to remove both the random noise component and the fixed pattern noise component. On the other hand, since the noise N2 on the oversaturation side is read out immediately after the start of accumulation, when removing both the random noise component and the fixed pattern noise component, the noise N2 is temporarily stored in the frame memory and then removed by the subtraction circuit (S1 + S2 + N2) − The operation of N2 is performed. In this way, the pre-saturation signal S1 and the supersaturation signal S1 + S2 from which noise has been removed are obtained. The subtraction circuit and the frame memory may be formed on the image sensor chip or may be formed as separate chips.

The expansion rate of the dynamic range can be expressed simply as (C _FD + C _CS ) / C _FD when the capacity of the floating diffusion FD is C _FD and the capacity of the storage capacitor CS is C _CS . In practice, the reset transistor R is less susceptible to the clock feedthrough when the FD + CS is reset than when the FD is reset, and the saturation voltage of the oversaturation side signal S2 is less than the saturation voltage of the presaturation side signal S1. The higher the dynamic range, the larger the dynamic range. In order to effectively expand the dynamic range without increasing the pixel size while maintaining a high photodiode aperture ratio, it is required to form a large storage capacitor with high area efficiency.

The synthesis of the wide dynamic range signal is realized by selecting one of the pre-saturation signal S1 and the supersaturation signal S1 + S2 from which noise has been removed. The selection of S1 and S1 + S2 is realized by comparing a preset S1 / (S1 + S2) switching reference voltage with the signal output voltage of S1 and selecting either S1 or S1 + S2. The switching reference voltage is set to a voltage that is lower than the S1 saturation voltage so as not to be affected by variations in the saturation voltage of the pre-saturation signal S1, and that maintains the S / N ratio of the oversaturated signal S1 + S2 at the switching point. do it. Here, it is possible to match the gain of the pre-saturation side signal S1 by multiplying the gain of the supersaturation side signal S1 + S2 by the ratio (C _FD + C _CS ) / C _FD ratio. In this way, it is possible to obtain a video signal with a wide dynamic range that is selectively synthesized with linear signals from low illuminance to high illuminance.

  As is apparent from the above-described operation, in this solid-state imaging device, the signal charges on the saturation side and the saturation side are mixed to form the signal S1 + S2 on the saturation side, so that at least S1 + S2 is the PD saturation of the light signal S1 on the saturation front side. The signal charge close to is present, and the tolerance for noise components such as reset noise and dark current on the oversaturation side is increased. Utilizing the fact that the noise tolerance for the supersaturated S1 + S2 signal becomes high, the potential of the next field floating diffusion FD and the storage capacitor CS immediately after resetting is N2 ′, and the difference between S1 + S2 + N2 in the field before reading is taken and fixed pattern noise component Even if the signal is removed ((S1 + S2 + N2) −N2 ′), a sufficient S / N ratio can be secured even in the vicinity of the selection switching point between the pre-saturation side signal and the supersaturation side signal. Therefore, a frame memory is not always necessary.

The read operation of the signal S1 + N1 and the noise signal N1 on the saturation side performs a floating diffusion FD reset noise and a source follower amplifier threshold value voltage variation correction operation. Therefore, high sensitivity and high S / N (low noise) characteristics are obtained in a low illuminance region. And there is no afterimage. In the operation on the oversaturation side, after the charge overflowing from the photodiode PD during the same accumulation period is accumulated in the storage capacitor CS via the overflow gate LO, the signal reading on the low illuminance side is completed, and then the time t ₈ In addition, the pre-saturation signal charge remaining in the FD is mixed with the supersaturated signal charge and read out. The potential of the FD when the storage transistor S is turned ON at time t ₈ is connected to a large capacitance CS FD + CS is directed to the positive direction. Therefore, even if the PD is in a saturated state, the photocharge of the PD is efficiently transferred to the FD + CS efficiently, so that no afterimage occurs even near the PD saturation.

  Further, even when the CS capacitance is saturated, it is possible to efficiently discharge surplus charges to VDD by adjusting the threshold voltages of the reset transistor R and the storage transistor S. Therefore, blooming even when a p-type silicon semiconductor substrate is used. Can be suppressed. Further, the low-side potential of the reset transistor R and the storage transistor S may be set higher than the zero potential.

  As described above, in low-illuminance imaging in which the photodiode PD is not saturated, high sensitivity and a high S / N ratio can be maintained by the pre-saturation charge signal (S1) obtained by canceling noise. In high-illuminance imaging with PD saturation, a signal obtained by accumulating photocharges overflowing from a photodiode through a storage capacitor and taking it in, and canceling noise in the same manner as described above (sum of pre-saturation charge signal and supersaturation charge signal ( By S1 + S2)), a wide dynamic range can be realized on the high illuminance side while maintaining a high S / N ratio.

  As described above, the solid-state imaging device of the present embodiment increases the sensitivity on the high illuminance side without lowering the sensitivity on the low illuminance side, and widens the dynamic range, and does not increase the power supply voltage from the range in which it is normally used. Therefore, it can cope with future miniaturization of image sensors. The addition of elements is kept to a minimum, and the pixel size is not increased.

  Furthermore, unlike conventional image sensors that achieve a wide dynamic range, the accumulation time is not divided between the high illuminance side and the low illuminance side, i.e., it is accumulated in the same accumulation time without straddling frames. The image quality is not deteriorated even in the case of imaging.

  As for the leakage current of the floating diffusion FD, in the image sensor of the present embodiment, the minimum signal of S1 + S2 becomes the saturation charge from the photodiode PD, and the charge amount larger than the charge of the FD leak is handled. There is an advantage that it is hardly affected by the FD leak.

Second Embodiment The present embodiment is a modification of the circuit configuration of the pixels of the solid-state imaging device according to the present embodiment according to the first embodiment. FIG. 6 is an equivalent circuit diagram of one pixel of this embodiment, and FIG. 7 is a schematic plan view thereof.

  Each pixel receives light and generates and accumulates photocharges, a transfer transistor T2 for transferring photocharges provided adjacent to the photodiode PD1, and a photodiode PD1 via the transfer transistor T2. Connected to the floating diffusion FD3, an overflow gate LO4 for transferring photocharge provided adjacent to the photodiode PD1 for transferring the photocharge overflowing from the photodiode PD1 during the accumulation operation, and during the accumulation operation A storage capacitor CS5 that accumulates photoelectric charges overflowing from the photodiode PD1 through the overflow gate LO4, and a reset transistor for discharging the signal charges in the storage capacitor CS5 and the floating diffusion FD3 are connected to the storage capacitor CS5. A register R6, a storage transistor S7 provided between the floating diffusion FD3 and the storage capacitor CS5, an amplification transistor SF8 for reading out the signal charge of the floating diffusion FD3 or the signal charge of the floating diffusion FD3 and the storage capacitor CS5 as a voltage, A selection transistor X9 is provided that is connected to the amplification transistor and selects a pixel or a pixel block.

As in the first embodiment, the solid-state imaging device according to the present embodiment has a plurality of pixels having the above-described configuration integrated in a two-dimensional or one-dimensional array, and each pixel has an overflow gate LO4 and a transfer. The driving lines φ _LO 10, φ _T 11, φ _S 12, and φ _R 13 are connected to the gate electrodes of the transistor T2, the storage transistor S7, and the reset transistor R6, and the row electrode is shifted to the gate electrode of the selection transistor X9. The pixel selection line φ _X 14 driven from the register is connected, and the output line OUT15 is connected to the output side source of the selection transistor X9, which is controlled and output by the column shift register.

Selection transistors X9, the driveline phi _X 14 is the similar to the first embodiment, selection of the pixel, so that it is non-selective operation, since it is sufficient fixing the voltage of the floating diffusion FD3 to appropriate values, they It can be omitted.

  Schematic cross-sectional view corresponding to the photodiode PD1, overflow gate LO4, and storage capacitor CS5 of the pixel of the solid-state imaging device according to the present embodiment, and the pixel photodiode PD1, transfer transistor T2, floating diffusion FD3, storage transistor S7, A schematic cross-sectional view corresponding to the storage capacitor CS5 is the same as FIGS. 3-1 and 3-2.

  An operation method of the solid-state imaging device according to this embodiment described with reference to FIGS. 6 and 7 will be described. FIG. 8 is a drive timing chart of the solid-state imaging device of the present embodiment.

  First, before accumulation, the accumulation transistor S is turned on, and the transfer transistor T and the reset transistor R are set off. At this time, the photodiode PD is completely depleted.

Next, the reset transistor R is turned on to reset the floating diffusion FD and the storage capacitor CS (time t ₁ ′), and the reset noise of FD + CS captured immediately after the reset transistor R is turned off is read as the noise signal N2. (Time t ₂ '). At this time, the threshold voltage variation of the amplification transistor SF is included in the noise signal N2 as a fixed pattern noise component. During the accumulation period (time t ₃ ′), with the accumulation transistor S, the transfer transistor T, the reset transistor R, and the selection transistor X turned off, photocharge before saturation is accumulated in the photodiode PD, and saturation is performed. Excess charge when exceeding is stored in the storage capacitor CS via the overflow gate LO. By this operation, the charge overflowing from the photodiode PD in the oversaturated state is effectively utilized without being discarded. In this manner, the accumulation operation is performed by receiving light within the same period with the same photodiode PD for each pixel before and after saturation.

After the accumulation is completed (time t ₄ ′), the selection transistor X is turned on, and then the noise signal N1 accumulated in the FD is read. At this time, the noise signal N1 includes the SF threshold voltage variation of the amplification transistor as a fixed pattern noise component. Next, the transfer transistor T is turned on to completely transfer the optical signal accumulated in the photodiode PD to the FD (time t ₅ ′), and the signal is read as S1 + N1. Next, the storage transistor S is also turned on (time t ₆ ′), and the signal charge stored in the photodiode PD is completely transferred to the floating diffusion FD and the storage capacitor CS, and is transferred to the photodiode PD, the floating diffusion FD, and the storage capacitor CS. The accumulated charges are mixed and a signal is read as S1 + S2 + N2.

In the first embodiment, a portion of the noise signal N2 accumulated in the floating diffusion FD and the storage capacitor CS were discarded during the reset operation of the time t ₅ Oite floating diffusion FD. The amount of the noise signal discarded at this time is C _FD / (C _FD + C _CS ) times the noise signal N 2 stored in the floating diffusion FD and the storage capacitor CS. In the solid-state imaging device of the present embodiment, part of the noise signal is not discarded.

  The block diagram of the solid-state imaging device of this embodiment is the same as that of FIG. 5 shown in the first embodiment. Signals read out in dot order from each pixel, dynamic range expansion ratio, and synthesis of wide dynamic range signals are the same as those described in the first embodiment.

  As in the first embodiment, the solid-state imaging device of the present embodiment increases the sensitivity on the high illuminance side without increasing the sensitivity on the low illuminance side as described above, and widens the dynamic range. Since it is not raised from the range in which it is used, it can cope with future miniaturization of image sensors. Further, the addition of elements is suppressed to a minimum, and the pixel size is not increased.

  Furthermore, unlike conventional image sensors that achieve a wide dynamic range, the accumulation time is not divided between the high illuminance side and the low illuminance side, i.e., it is accumulated in the same accumulation time without straddling frames. The image quality is not deteriorated even in the case of imaging.

As for the leakage current of the floating diffusion FD, the minimum signal read by the floating diffusion FD and the capacitance C _FD + C _CS of the storage capacitor CS in the image sensor of the present embodiment is the oversaturated charge + the saturated charge from the photodiode PD. Therefore, since an amount of charge larger than that of the FD leak is handled, there is an advantage that it is hardly affected by the FD leak.

Third Embodiment This embodiment is a modification of the overflow gate of the pixel of the solid-state imaging device according to this example according to the first and second embodiments. 9 and 10 are an equivalent circuit diagram and a schematic plan view of one pixel corresponding to the first embodiment of the present embodiment. 11 and 12 are an equivalent circuit diagram and a schematic plan view of one pixel corresponding to the second embodiment of the present embodiment.

  Each pixel receives light and generates and accumulates photocharges, a transfer transistor T2 for transferring photocharges provided adjacent to the photodiode PD1, and a photodiode PD1 via the transfer transistor T2. A floating diffusion FD3 provided in connection with the photodiode, an overflow gate LO4 ′ for transferring photocharge provided adjacent to the photodiode PD1 for transferring photocharge overflowing from the photodiode PD1 during the accumulation operation, and an accumulation operation A storage capacitor CS5 that sometimes accumulates the photoelectric charge overflowing from the photodiode PD1 through the overflow gate LO4 ′ and a signal charge in the floating diffusion FD3 (FIG. 9) or the storage capacitor CS5 (FIG. 11) are formed connected to the storage capacitor CS5. Discharge Reset transistor R6, a storage transistor S7 provided between the floating diffusion FD3 and the storage capacitor CS5, and an amplification for reading the signal charge of the floating diffusion FD3 or the signal charge of the floating diffusion FD3 and the storage capacitor CS5 as a voltage. The transistor SF8 is connected to the amplifying transistor and includes a selection transistor X9 for selecting a pixel or a pixel block.

As in the first and second embodiments, the solid-state imaging device according to this embodiment includes a plurality of pixels having the above-described configuration integrated in a two-dimensional or one-dimensional array, and each pixel has a transfer transistor. The drive lines φ _T 11, φ _S 12, and φ _R 13 are connected to the gate electrodes of T2, the storage transistor S7, and the reset transistor R6, and the gate electrode of the selection transistor X9 is driven from the row shift register. The pixel selection line φ _X 14 is connected, and the output line OUT15 is connected to the output side source of the selection transistor X9, which is controlled and output by the column shift register.

Selection transistors X9, the driveline phi _X 14 is the similar to the first embodiment, selection of the pixel, so that it is non-selective operation, since it is sufficient fixing the voltage of the floating diffusion FD3 to appropriate values, they It can be omitted. Further, as shown in FIGS. 9 and 11, the gate of the overflow gate LO4 ′ is grounded.

  FIG. 13 shows a schematic cross-sectional view corresponding to the photodiode PD1, overflow gate LO4 ', and storage capacitor CS5 of the pixel of the solid-state imaging device according to the present embodiment. Here, in a region related to the n-type semiconductor region 30 and the n + -type semiconductor region 32, a p + semiconductor region 50 is formed on the upper surface of the p-type well 21, and the n-type semiconductor region 30 and the n + -type semiconductor region 32 are used as a source / drain. A junction transistor type overflow gate LO having the p + type semiconductor region 50 as a gate is formed. Other structures are the same as those in the first embodiment. The p + semiconductor region 50 is electrically connected to the p + type semiconductor region 31 and the p type well region 21.

  The operation method of the solid-state imaging device of this embodiment is the same as that of the first and second embodiments. The block diagram of the solid-state imaging device of this embodiment is the same as that of FIG. 5 shown in the first embodiment. Signals read out in dot order from each pixel, dynamic range expansion ratio, and synthesis of wide dynamic range signals are the same as those described in the first embodiment.

  In the solid-state imaging device according to the present embodiment, the p + semiconductor region 50 is electrically connected to the p + type semiconductor region 31 and the p type well region 21 in addition to exhibiting the same effect as the first embodiment and the second embodiment. Since they are connected, the number of drive signal wirings can be reduced as compared with the first embodiment and the second embodiment, and higher density pixels can be realized.

Fourth Embodiment A solid-state imaging device according to the present embodiment has a structure in which the charge overflowing from the photodiode during charge accumulation can be moved more smoothly to the floating diffusion in the solid-state imaging device of the third embodiment. The solid-state imaging device.

  In the solid-state imaging device shown in FIG. 14, the overflow gate LO has a buried channel type having a semiconductor layer of the same conductivity type as the channel of the junction transistor formed from the surface of the substrate constituting the junction transistor or near the surface to a predetermined depth. It is sectional drawing of an example, and is equivalent to the part of photodiode PD, overflow gate LO, and storage capacity CS.

Here, the n-type semiconductor region 51 is partially overlapped with the n-type semiconductor region 30 and the n ⁺ -type semiconductor region 32 from the surface of the substrate below the gate p + -type semiconductor region 50 of the overflow gate LO to a predetermined depth. Is formed. The n-type semiconductor region 51 is an n-type region having an effective impurity concentration lower than that of the n-type semiconductor region 30 and the n ⁺ -type semiconductor region 32.

  The above structure corresponds to lowering the potential barrier between the photodiode PD and the storage capacitor CS. Therefore, the charge overflowing from the photodiode PD during charge accumulation can be smoothly moved to the storage capacitor CS.

  In the solid-state imaging device shown in FIGS. 15 and 16, the overflow gate LO is formed at a predetermined depth of the substrate in parallel with the lower portion of the overflow gate LO, and punch-through between the photodiode PD and the storage capacitor CS is performed. The semiconductor device has a semiconductor layer that reduces a barrier.

  FIG. 15 is a cross-sectional view of an example of the solid-state imaging device according to the present embodiment, and corresponds to a photodiode PD, an overflow gate LO, and a storage capacitor CS. Here, an n-type semiconductor region 52 is formed so as to be connected to the n-type semiconductor region 30 in a region having a predetermined depth below the gate electrode 50 of the overflow gate LO.

  The above structure corresponds to lowering the punch-through barrier of the overflow gate LO. This oblique punch-through route from the n-type semiconductor region 52 to the n + -type semiconductor region 32 becomes an overflow path from the photodiode PD to the storage capacitor CS, and the charge overflowing from the photodiode PD during charge accumulation is punch-through. Thus, the storage capacitor CS can be moved smoothly.

  FIG. 16 is a cross-sectional view of an example of the solid-state imaging device according to the present embodiment. Like the solid-state imaging device of FIG. 15, an n-type is formed in a region having a predetermined depth below the gate electrode 50 of the overflow gate LO. An n-type semiconductor region 53 is formed in connection with the semiconductor region 30. In the present embodiment, the n-type semiconductor region 53 is formed so as to extend further below the n + -type semiconductor region 32.

  The above structure corresponds to lowering the punch-through barrier of the overflow gate LO. The substantially vertical punch-through route from the n-type semiconductor region 53 to the n + -type semiconductor region 32 becomes an overflow path from the photodiode PD to the storage capacitor CS, and punches the charge overflowing from the photodiode PD during charge accumulation. It can be smoothly moved to the storage capacitor CS.

Fifth Embodiment The present embodiment is a modified form of the pixel circuit configuration of the solid-state imaging device according to the present embodiment according to the first embodiment. FIG. 17 is an equivalent circuit diagram of two pixels of the present embodiment, and FIG. 18 is a schematic plan view thereof.

  The present embodiment is a solid-state imaging device having a pixel block composed of two photodiodes and pixels a and b having storage capacitors as a basic unit. Each pixel block receives photodiodes PDa1 and PDb1 ′ that generate and accumulate photocharges, and transfer transistors Ta2 and Tb2 ′ that transfer photocharges provided adjacent to the photodiodes PDa1 and PDb1 ′. And one floating diffusion FD3 provided to be connected to each of the photodiodes PDa1 and PDb1 ′ via the transfer transistors Ta2 and Tb2 ′, respectively, and a photocharge overflowing from each of the photodiodes PDa1 and PDb1 ′ during the accumulation operation. Overflow gates LOa4 and LOb4 ′ for transferring photocharges provided adjacent to the photodiodes PDa1 and PDb1 ′, and the photocharges overflowing from the photodiodes PDa1 and PDb1 ′ during the accumulation operation, respectively. The storage capacitors CSa5 and CSb5 ′ that are stored through the flow gates LOa4 and LOb4 ′ are connected to the storage capacitors CSa5 and CSb5 ′, respectively, for discharging signal charges in the storage capacitors CSa5 and CSb5 ′ and the floating diffusion FD3. The reset transistor R6, the storage transistors Sa7 and Sb7 provided between the floating diffusion FD3 and the storage capacitors CSa5 and CSb5 ′, and the signal charges of the floating diffusion FD3 or the respective signal charges of the floating diffusion FD3 and the storage capacitors CSa5 and CSb5 ′ An amplification transistor SF8 for reading out as a voltage, and a selection transistor X9 provided in connection with the amplification transistor for selecting a pixel or a pixel block. It is configured. In this manner, a basic unit pixel block having the floating diffusion FD, the amplification transistor SF, the reset transistor R, and the selection transistor X in the two photodiodes and the storage capacitor is formed.

In the solid-state imaging device according to the present embodiment, a plurality of pixels having the above-described configuration are integrated in a two-dimensional or one-dimensional array, and in each pixel block, overflow gates LOa4 and LOb4 ′, transfer transistors Ta2 and Tb2 ′. , The drive lines φ _LOa , φ _LOb , φ _Ta , φ _Tb , φ _Sa , φ _Sb , φ _R are connected to the gate electrodes of the storage transistors _{Sa 7} , _Sb 7 ′ and the reset transistor R 6. A pixel selection line φ _X driven from the row shift register is connected to the gate electrode, and an output line OUT15 is connected to the output side source of the selection transistor X9, which is controlled and output by the column shift register.

  As with the first embodiment, the selection transistor X9 and the drive line φX are omitted as long as the voltage of the floating diffusion FD3 can be fixed to an appropriate value so that the pixel can be selected and deselected. It is also possible.

  Schematic sectional view and pixels corresponding to the photodiodes PDa1, PDb1 ′, overflow gates LOa4, LOb4 ′, storage capacitors CSa5, CSb5 ′ of the pixels a and b in the pixel block of the solid-state imaging device according to the present embodiment. Schematic cross-sectional views corresponding to the photodiodes PDa1, PDb1 ′, transfer transistors Ta2, Tb2 ′, floating diffusion FD3, storage transistors Sa7, Sb7 ′, and storage capacitors CSa5, CSb5 are shown in FIGS. 3-1 and 3-2. It is the same.

  An operation method of the solid-state imaging device according to this embodiment described with reference to FIGS. 17 and 18 will be described. FIG. 19 is a drive timing chart of the solid-state imaging device of the present embodiment. In each pixel block, when reading out the pixel a and the pixel b, they are read out using the same floating diffusion FD, amplification transistor SF, reset transistor R, and selection transistor X.

First, before exposure accumulation, the accumulation transistor Sa of the pixel a is set to on, the transfer transistor Ta, and the reset transistor R are set to off. At this time, the photodiode PDa of the pixel a is completely depleted. Next, the reset transistor R is turned on to reset the floating diffusion FD and the storage capacitor CSa of the pixel a (time t ₁ ), and the reset noise of FD + CSa taken immediately after the reset transistor R is turned off is read as the noise signal N2. (Time t ₂ ). At this time, the threshold voltage variation of the amplification transistor SF is included in the noise signal N2 as a fixed pattern noise component. During the accumulation period (time t ₃ ), the photocharge before saturation is accumulated in the photodiode PDa, and excess photocharge when the saturation is exceeded is accumulated in the storage capacitor CSa via the overflow gate LOa. By this operation, the charge overflowing from the photodiode PD in the oversaturated state is effectively utilized without being discarded. In this manner, the accumulation operation is performed by receiving light within the same period with the same photodiode PD for each pixel before and after saturation.

After the accumulation is completed (time t ₄ ), the selection transistor X is turned on, and then the reset transistor is turned on to reset the floating diffusion FD unit (time t ₅ ). The FD reset noise captured immediately after the reset is a noise signal. Read as N1 (time t ₆ ). At this time, the noise signal N1 includes a variation in threshold voltage of the amplification transistor SF as a fixed pattern noise component. Next, the transfer transistor Ta is turned on to completely transfer the optical signal accumulated in the photodiode PDa to the FD (time t ₇ ), and the signal is read as S1 + N1. Next, the storage transistor Sa is also turned on (time t ₈ ), and the signal charge stored in the photodiode PDa is completely transferred to the floating diffusion FD and the storage capacitor CSa, and stored in the photodiode PDa, the floating diffusion FD, and the storage capacitor CSa. The mixed charges are mixed and a signal is read as S1 + S2 + N2. Also in the pixel b, before the exposure accumulation, the accumulation transistor Sb is turned on, the transfer transistor Tb and the reset transistor R are set off, the reset transistor R is turned on to reset the floating diffusion FD and the accumulation capacitor CSb, and the reset transistor The reset noise of FD + CSb captured immediately after R is turned off is read as a noise signal N2. At this time, the threshold voltage variation of the amplification transistor SF is included in the noise signal N2 as a fixed pattern noise component.

During the accumulation period (time t ₉ ), the photocharge before saturation is accumulated in the photodiode PDb, and excess photocharge when the saturation is exceeded is accumulated in the storage capacitor CSb via the overflow gate LOb.

After the accumulation is completed (time t ₁₀ ), the selection transistor X is turned on, and then the reset transistor is turned on to reset the floating diffusion FD section (time t ₁₁ ), and the FD reset noise captured immediately after the reset is a noise signal. Read as N1 (time t ₁₂ ).

Next, the transfer transistor Tb is turned on to completely transfer the optical signal accumulated in the photodiode PDb to the FD (time t ₁₃ ), and the signal is read as S1 + N1. Next, the storage transistor Sb is also turned on (time t ₁₄ ), and the signal charge stored in the photodiode PDb is completely transferred to the floating diffusion FD and storage capacitor CSb, and stored in the photodiode PDb, floating diffusion FD, and storage capacitor CSb. The mixed charges are mixed and a signal is read as S1 + S2 + N2.

  In the solid-state imaging device according to the present embodiment, the floating diffusion FD, the amplification transistor SF, the reset transistor R, and the selection transistor X are provided in a ratio of one set per two pixels, so that the pixel area per pixel can be reduced. it can.

  The block diagram of the solid-state imaging device of this embodiment is the same as that of FIG. 5 shown in the first embodiment, but one output line is provided for every two pixels. Signals read out sequentially from each pixel, dynamic range expansion ratio, and synthesis of wide dynamic range signals are the same as those described in the first embodiment.

  In the above operation, the case where the pixels provided in each pixel block are sequentially driven and signals obtained from all the pixels are used is shown. A signal obtained from a pixel may be used, or pixel signals may be mixed and added in each pixel block as an averaging operation, and the signal may be used.

  As in the first embodiment, the solid-state imaging device according to the present embodiment normally uses a power supply voltage in addition to increasing the sensitivity on the high illuminance side without increasing the sensitivity on the low illuminance side and widening the dynamic range. Since it is not raised from the range, it can cope with future miniaturization of image sensors. Further, the addition of elements is suppressed to a minimum, and the pixel size is not increased.

  Furthermore, unlike conventional image sensors that achieve a wide dynamic range, the accumulation time is not divided between the high illuminance side and the low illuminance side, i.e., it is accumulated in the same accumulation time without straddling frames. The image quality is not deteriorated even in the case of imaging.

  As for the leakage current of the floating diffusion FD, in the image sensor of the present embodiment, the minimum signal of S1 + S2 becomes the saturation charge from the photodiode PD, and the charge amount larger than the charge of the FD leak is handled. There is an advantage that it is hardly affected by the FD leak.

Sixth Embodiment The present embodiment is an embodiment obtained by modifying the circuit configuration of a pixel of the solid-state imaging device according to the present embodiment according to the first embodiment. FIG. 20 is an equivalent circuit diagram of the pixel of this embodiment, and FIG. 21 is a schematic plan view thereof.

  The present embodiment is a solid-state imaging device having a pixel block composed of four photodiodes and pixels a, b, c, and d having storage capacitors as a basic unit. Each pixel block receives photodiodes PDa1, PDb1 ′, PDc1 ″, PDd1 ′ ″ that generate and store photoelectric charges, and photodiodes PDa1, PDb1 ′, PDc1 ″, PDd1 ′ ″, respectively. And transfer transistors Ta2, Tb2 ′, Tc2 ″, Td2 ′ ″, which are provided adjacent to each other, and photodiodes via the transfer transistors Ta2, Tb2 ′, Tc2 ″, Td2 ′ ″, respectively. One floating diffusion FD3 connected to each of PDa1, PDb1 ′, PDc1 ″, PDd1 ′ ″ and photocharges overflowing from each of the photodiodes PDa1, PDb1 ′, PDc1 ′, PDd1 ′ ″ during the accumulation operation Adjacent to the photodiodes PDa1, PDb1 ′, PDc1 ″, PDd1 ′ ″ for transferring The overflow gates LOa4, LOb4 ′, LOc4 ″, LOd4 ′ ″ for transferring the photocharges provided and the photocharges overflowing from the photodiodes PDa1, PDb1 ′, PDc1 ″, PDd1 ′ ″ during the accumulation operation, respectively. Storage capacitors CSa5, CSb5 ′, CSc5 ″, CSd5 ′ ″ and storage capacitors CSa5, CSb5 ′, CSc5 ″, CSd5 ′ ″ stored through the overflow gates LOa4, LOb4 ′, LOc4 ″, LOd4 ′ ″ The storage capacitors CSa5, CSb5 ′, CSc5 ″, CSd5 ′ ″ and the reset transistor R6 for discharging signal charges in the floating diffusion FD3, the floating diffusion FD3, the storage capacitors CSa5, CSb5 ', CSc5' ', CSd5' '' The product transistors Sa7, Sb7 ′, Sc7 ″, Sd7 ′ ″ and the signal charges of the floating diffusion FD3 or the signal charges of the floating diffusion FD3 and the storage capacitors CSa5, CSb5 ′, CSc5 ″, CSd5 ′ ″ are used as voltages. It comprises an amplification transistor SF8 for reading and a selection transistor X9 provided in connection with the amplification transistor for selecting a pixel or a pixel block. In this way, a basic unit pixel block having the floating diffusion FD, the amplification transistor SF, the reset transistor R, and the selection transistor X is configured in the four photodiodes and the storage capacitor.

In the solid-state imaging device according to this embodiment, a plurality of pixels having the above-described configuration are integrated in a two-dimensional or one-dimensional array, and in each pixel block, overflow gates LOa4, LOb4 ′, LOc4 ″, LOd4 ′. '', Transfer transistors Ta2, Tb2 ′, Tc2 ″, Td2 ′ ″, storage transistors Sa7, Sb7 ′, Sc7 ″, Sd7 ′ ″, and the gate electrodes of the reset transistor R6 are φ _LOa , φ _LOb , φ _{LOc, φ LOd, φ Ta,} φ Tb, φ Tc, φ Td, φ Sa, φ Sb, φ Sc, φ Sd, φ the drive line of _R are connected, the line to a gate electrode of the selection transistor X9 A pixel selection line φ _X driven from the shift register is connected, and an output line OUT15 is further connected to the output side source of the selection transistor X9, which is controlled and output by the column shift register.

Selection transistors X9, for driveline phi _X, wherein similarly to the first embodiment, selection of the pixel, so that it is non-selective operation, since it is sufficient fixing the voltage of the floating diffusion FD3 to an appropriate value, omit them It is also possible to do.

  Photodiodes PDa1, PDb1 ′, PDc1 ″, PDd1 ′ ″, overflow gates LOa4, LOb4 ′, LOc4 ′ of the pixels a, b, c, and d in the pixel block of the solid-state imaging device according to the present embodiment. ', LOd4' '', schematic sectional views corresponding to the storage capacitors CSa5, CSb5 ', CSc5' ', CSd5' '' and pixel photodiodes PDa1, PDb1 ', PDc1' ', PDd1' '', Transfer transistors Ta2, Tb2 ′, Tc2 ″, Td2 ′ ″, floating diffusion FD3, storage transistors Sa7, Sb7 ′, Sc7 ″, Sd7 ′ ″, storage capacitors CSa5, CSb5 ′, CSc6 ″, CSd7 ″ A schematic cross-sectional view corresponding to the portion 'is the same as FIGS. 3-1 and 3-2.

  An operation method of the solid-state imaging device according to this embodiment described with reference to FIGS. 20 and 21 will be described. FIG. 22 is a drive timing chart of the solid-state imaging device of the present embodiment. In each pixel block, when the pixel a, the pixel b, the pixel c, and the pixel d are read out, they are read out using the same floating diffusion FD, amplification transistor SF, reset transistor R, and selection transistor X.

  First, before exposure accumulation, the accumulation transistor Sa of the pixel a is set to on, the transfer transistor Ta, and the reset transistor R are set to off. At this time, the photodiode PDa of the pixel a is completely depleted.

Next, the reset transistor R is turned on to reset the floating diffusion FD and the storage capacitor CSa of the pixel a (time t ₁ ), and the reset noise of FD + CSa taken immediately after the reset transistor R is turned off is read as the noise signal N2. (Time t ₂ ). At this time, the threshold voltage variation of the amplification transistor SF is included in the noise signal N2 as a fixed pattern noise component.

During the accumulation period (time t ₃ ), the photocharge before saturation is accumulated in the photodiode PDa, and excess photocharge when the saturation is exceeded is accumulated in the storage capacitor CSa via the overflow gate LOa. By this operation, the charge overflowing from the photodiode PD in the oversaturated state is effectively utilized without being discarded. In this manner, the accumulation operation is performed by receiving light within the same period with the same photodiode PD for each pixel before and after saturation.

After the accumulation is completed (time t ₄ ), the selection transistor X is turned on, and then the reset transistor is turned on to reset the floating diffusion FD unit (time t ₅ ). The FD reset noise captured immediately after the reset is a noise signal. Read as N1 (time t ₆ ). At this time, the noise signal N1 includes a variation in threshold voltage of the amplification transistor SF as a fixed pattern noise component.

Next, the transfer transistor Ta is turned on to completely transfer the optical signal accumulated in the photodiode PDa to the FD (time t ₇ ), and the signal is read as S1 + N1. Next, the storage transistor Sa is also turned on (time t ₈ ), and the signal charge stored in the photodiode PDa is completely transferred to the floating diffusion FD and the storage capacitor CSa, and stored in the photodiode PDa, the floating diffusion FD, and the storage capacitor CSa. The mixed charges are mixed and a signal is read as S1 + S2 + N2. Also in the pixel b, before the exposure accumulation, the accumulation transistor Sb is turned on, the transfer transistor Tb and the reset transistor R are set off, the reset transistor R is turned on to reset the floating diffusion FD and the accumulation capacitor CSb, and the reset transistor The reset noise of FD + CSb captured immediately after R is turned off is read as a noise signal N2. At this time, the threshold voltage variation of the amplification transistor SF is included in the noise signal N2 as a fixed pattern noise component.

During the accumulation period (time t ₉ ), the photocharge before saturation is accumulated in the photodiode PDb, and excess photocharge when the saturation is exceeded is accumulated in the storage capacitor CSb via the overflow gate LOb. After the accumulation is completed (time t ₁₀ ), the selection transistor X is turned on, and then the reset transistor is turned on to reset the floating diffusion FD section (time t ₁₁ ), and the FD reset noise captured immediately after the reset is a noise signal. Read as N1 (time t ₁₂ ). Next, the transfer transistor Tb is turned on to completely transfer the optical signal accumulated in the photodiode PDb to the FD (time t ₁₃ ), and the signal is read as S1 + N1. Next, the storage transistor Sb is also turned on (time t ₁₄ ), and the signal charge stored in the photodiode PDb is completely transferred to the floating diffusion FD and storage capacitor CSb, and stored in the photodiode PDb, floating diffusion FD, and storage capacitor CSb. The mixed charges are mixed and a signal is read as S1 + S2 + N2. Thereafter, the same operation as described above is repeated for the pixels c and d.

  In the solid-state imaging device of the present embodiment, the floating diffusion FD, the amplification transistor SF, the reset transistor R, and the selection transistor X are provided in a ratio of one set per four pixels, so that the pixel area per pixel can be reduced. it can.

  In the above operation, the case where the pixels provided in each pixel block are sequentially driven and signals obtained from all the pixels are used is shown. A signal obtained from a pixel may be used, or pixel signals may be mixed and added in each pixel block as an averaging operation, and the signal may be used.

  The block diagram of the solid-state imaging device of this embodiment is the same as that of FIG. 5 shown in the first embodiment, but one output line is provided for every four pixels. Signals read out sequentially from each pixel, dynamic range expansion ratio, and synthesis of wide dynamic range signals are the same as those described in the first embodiment.

  As in the first embodiment, the solid-state imaging device according to the present embodiment normally uses a power supply voltage in addition to increasing the sensitivity on the high illuminance side without increasing the sensitivity on the low illuminance side and widening the dynamic range. Since it is not raised from the range, it can cope with future miniaturization of image sensors. Further, the addition of elements is suppressed to a minimum, and the pixel size is not increased.

  Furthermore, unlike conventional image sensors that achieve a wide dynamic range, the accumulation time is not divided between the high illuminance side and the low illuminance side, i.e., it is accumulated in the same accumulation time without straddling frames. The image quality is not deteriorated even in the case of imaging.

In addition, regarding the leakage current of the floating diffusion FD, in the image sensor of this embodiment, the minimum signal of C _FD + C _CS becomes the saturation charge from the oversaturation charge + the photodiode PD, and the charge amount is larger than the charge of the FD leakage. Since it comes to handle, there exists an advantage that it is hard to receive the influence of FD leak.

Seventh Embodiment The present embodiment shows a modification of the form of the storage capacitor for storing photocharges overflowing from the photodiode in the first to sixth embodiments.

As the storage capacity, when considering junction type storage capacitor, the capacitance per 1 [mu] m ² even considering the condition is 0.3~3 fF / μm ² or so, the area efficiency is not very good, the dynamic range It is difficult to make it wide.

On the other hand, in the planar type storage capacitor, the insulating film electric field is 3 to 4 MV / cm or less, the maximum applied voltage is 2.5 to 3 V, and the capacitor insulating film thickness is about 7 nm in order to suppress the insulating film leakage current of the capacitor insulating film. When set, the relative dielectric constant of the material of the capacitive insulating film is 3.9 and 4.8 fF / μm ² , the relative dielectric constant is 7.9 and 9.9 fF / μm ² , and the relative dielectric constant is 20 and 25 fF / μm ^2. When the relative dielectric constant is 50, the dielectric constant is 63 fF / μm ² .

In addition to silicon oxide (relative dielectric constant 3.9), silicon nitride (7.9), Ta ₂ O ₅ (about 20-30), HfO ₂ (about 30), ZrO ₂ (about 30), By using a so-called High-k material of La ₂ O ₃ (about 40 to 50), a larger electrostatic capacity can be realized, and even a planar type image sensor having a relatively simple structure has a wide dynamic range of 100 to 120 dB. Can be realized.

  Furthermore, it is possible to achieve a wide dynamic range of 120 dB by applying a stack type or trench type structure capable of expanding the area contributed by the capacitance by suppressing the occupied area, and further combining the above High-k materials. Thus, it is possible to achieve 140 dB in the stack type and 160 dB in the trench type.

  The following are examples of storage capacities that can be applied in this embodiment. FIG. 23 is a cross-sectional view of a planar type MOS storage capacitor similar to that of the first embodiment. That is, the storage capacitor CS includes, for example, an n + type semiconductor region 60 that is a lower electrode formed in the surface layer portion of the p type well 21 on the p type semiconductor substrate 20 and a silicon oxide formed on the n + type semiconductor region 60. In this configuration, the capacitor insulating film 42 and an upper electrode 43 such as polysilicon formed on the capacitor insulating film 42 are provided.

  FIG. 24 is a cross-sectional view of a planar type MOS and junction type storage capacitor. For example, an n + type semiconductor region 61 serving as a lower electrode is integrally formed with an n + type semiconductor region 32 serving as a source / drain of a storage transistor in a surface layer portion of a p type well 21 formed in the p type semiconductor substrate 20. An upper electrode 43 is formed through a capacitive insulating film 42 of silicon oxide thereon, thereby forming a storage capacitor CS. In this case, the power supply voltage VDD or the ground GND is applied to the upper electrode 43.

The storage capacitor shown in the sectional view of FIG. 25 is a planar type MOS storage capacitor similar to FIG. However, the capacitor insulating film 42a is made of a high-k material such as silicon nitride or Ta ₂ O ₅ and has a larger capacity than the storage capacitor of FIG.

The storage capacitor shown in the cross-sectional view of FIG. 26 is a planar type MOS and junction type storage capacitor similar to FIG. However, the capacitor insulating film 42a is made of a high-k material such as silicon nitride or Ta ₂ O ₅ and has a larger capacity than the storage capacitor of FIG.

  FIG. 27 is a cross-sectional view of a stack type storage capacitor. For example, a lower electrode 63 formed on the element isolation insulating film 62 formed on the p-type semiconductor substrate 20, a capacitive insulating film 64 formed on the lower electrode 63, and an upper portion formed on the capacitive insulating film 64. This is a configuration having an electrode 65. Here, the n + -type semiconductor region 32 serving as the source / drain of the storage transistor and the lower electrode 63 are connected by the wiring 45. In this case, the power supply voltage VDD or the ground GND is applied to the upper electrode 65.

  FIG. 28 is a cross-sectional view of a stack type storage capacitor. For example, the lower electrode 67 formed so as to be connected to the n + type semiconductor region 32 serving as the source / drain of the storage transistor, the capacitive insulating film 68 formed on the inner wall surface of the lower electrode 67, and the inner side of the lower electrode 67 And an upper electrode 69 formed through a capacitive insulating film 68 so as to embed this portion. Here, the power supply voltage VDD or the ground GND is applied to the upper electrode 69. The structure of the upper electrode 69 formed so as to bury the lower electrode 67 and the portion inside the lower electrode 67 can have a larger opposing area that contributes to the capacitance than a normal stack type.

  FIG. 29 is a cross-sectional view of a composite storage capacitor combining a planar MOS type and a stack type. According to this example, a large capacity with high area efficiency can be formed.

  FIG. 30 is a cross-sectional view of a trench type storage capacitor. A trench TC is formed so as to penetrate the p-type well 21 of the n-type semiconductor substrate 20 and reach the n-type substrate, and an n + -type semiconductor region 70 serving as a lower electrode formed on the inner wall of the trench TC, and the trench TC The capacitor insulating film 71 is formed so as to cover the inner wall, and the upper electrode 72 is formed by filling the trench TC with the capacitor insulating film 71 interposed therebetween. Here, the n + -type semiconductor region 32 serving as the source / drain of the storage transistor and the upper electrode 72 are connected by the wiring 45.

  FIG. 31 is a cross-sectional view of a trench type storage capacitor having a junction. A trench TC is formed in the p-type well 21 of the n-type semiconductor substrate 20, and an n + -type semiconductor region 73 serving as a lower electrode is integrated with an n + -type semiconductor region 32 serving as a source / drain of the storage transistor on the inner wall of the trench TC. The capacitor insulating film 74 is formed so as to cover the inner wall of the trench TC, and the upper electrode 75 is formed by filling the trench TC via the capacitor insulating film 74.

  FIG. 32 is a cross-sectional view of a trench type storage capacitor. A trench TC is formed so as to penetrate the p-type well 21 of the n-type semiconductor substrate 20 and reach the n-type substrate, and in a region deeper than a certain depth of the trench TC, it becomes a lower electrode formed on the inner wall thereof. The n + type semiconductor region 76, a capacitive insulating film 77 formed so as to cover the inner wall of the trench TC, and an upper electrode 78 formed by filling the trench TC with the capacitive insulating film 77 interposed therebetween. Here, the n + -type semiconductor region 32 serving as the source / drain of the storage transistor and the upper electrode 78 are connected by the wiring 45.

  FIG. 33 is a cross-sectional view of a trench type storage capacitor. A trench TC is formed so as to penetrate the p-type well 21 of the n-type semiconductor substrate 20 and reach the n-type substrate, and a p + -type semiconductor region 79 serving as a lower electrode formed on the inner wall of the trench TC, and the trench TC. In this configuration, the capacitor insulating film 80 is formed so as to cover the inner wall, and the upper electrode 81 is formed by filling the trench TC with the capacitor insulating film 80 interposed therebetween. Here, the n + -type semiconductor region 32 serving as the source / drain of the storage transistor and the upper electrode 81 are connected by the wiring 45.

  FIG. 34 is a sectional view of a CMOS sensor having a buried storage capacitor using a junction capacitor. For example, a p-type epitaxial layer 91 is formed on a p-type silicon semiconductor substrate (p-sub) 90, and an n + -type semiconductor region 92 is formed across the p-type silicon semiconductor substrate 90 and the p-type epitaxial layer 91. That is, an n-type (first conductivity type) semiconductor region and a p-type (second conductivity type) semiconductor region bonded to the n-type (first conductivity type) semiconductor region are embedded in the semiconductor substrate constituting the solid-state imaging device, thereby increasing the junction capacitance. The embedded storage capacitor used is formed. A p + type isolation region 93 is further formed in the p type silicon semiconductor substrate 90 and the p type epitaxial layer 91 region. A p-type semiconductor layer 94 is formed on the p-type epitaxial layer 91. The photodiode PD, the overflow gate LO, the transfer transistor T, the floating diffusion are compared with the p-type semiconductor layer 94 as in the above embodiments. An FD and a storage transistor S are formed. For example, the n + -type semiconductor region 92 serving as a storage capacitor is widely formed over the formation regions of the photodiode PD, the overflow gate LO, the transfer transistor T, the floating diffusion FD, and the storage transistor T. Further, the n + type semiconductor region 32 serving as the source / drain of the storage transistor T is connected to the n + type semiconductor region 92 constituting the storage capacitor by the n + type semiconductor region 95 extending vertically in the p type semiconductor layer 94. .

  FIG. 35 is a cross-sectional view of a CMOS sensor having a buried storage capacitor using an insulating film capacitor and a junction capacitor. Although the structure is the same as that of FIG. 34, a first p-type epitaxial layer 91a and a second p-type epitaxial layer 91b are formed on a p-type silicon semiconductor substrate (p-sub) 90 via an insulating film 90a. This is an SOI (Semiconductor on Insulator) substrate in which a semiconductor layer is formed on a semiconductor substrate via an insulating film. Here, an n + -type semiconductor region 92 is formed over the first p-type epitaxial layer 91a and the second p-type epitaxial layer 91b up to a region in contact with the insulating film 90a, and the semiconductor substrate and the semiconductor layer facing each other through the insulating film are formed. A storage capacitor is configured by using the insulating film capacitance therebetween. Further, similarly to the storage capacitor in FIG. 34, a junction capacitor is formed between the n + type semiconductor region 92 and the first p-type epitaxial layer 91a and the second p-type epitaxial layer 91b. The other structure is the same as that of the CMOS sensor of FIG.

  FIG. 36 is a sectional view of a CMOS sensor having a buried storage capacitor using an insulating film capacitor and a junction capacitor. Although the structure is similar to that of FIG. 35, a low-concentration semiconductor layer (i layer) 96 is further formed between the n-type semiconductor region 30 constituting the photodiode PD and the n + -type semiconductor region 92 constituting the storage capacitor. ing. The above structure corresponds to lowering the potential barrier between the n-type semiconductor region 30 and the n + -type semiconductor region 92, and serves as an overflow path from the photodiode PD to the storage capacitor CS. Thereby, the charge overflowing from the photodiode during charge accumulation can be punched through and moved to the storage capacitor.

  The various storage capacitors described above can be applied to any of the first to sixth embodiments described above. As described above, by storing the photoelectric charges overflowing from the photodiode with the storage capacitors having these shapes, Wide dynamic range can be realized on the illuminance side.

Example 1
In the solid-state imaging device of the present invention, solid-state imaging having pixels arranged in a two-dimensional array and having a horizontal pixel number of 640 × vertical 480, a pixel size of 7.5 μm square, a floating diffusion capacitance C _FD = 4 fF, and a storage capacitance C _CS = 60 fF The element was produced by a semiconductor manufacturing method having a two-layer polysilicon three-layer metal wiring. Each storage capacitor is constituted by a parallel capacitor of polysilicon-silicon oxide film-silicon capacitor and polysilicon-silicon nitride film-polysilicon capacitor. The saturation signal voltages of the signals S1 and S1 + S2 were 500 mV and 1000 mV, respectively, and the residual noise voltages remaining in S1 and S1 + S2 after noise removal were equally 0.09 mV. The switching voltage from S1 to S1 + S2 was set lower than the saturation voltage of S1 and set to 400 mV.

  Since the S / N ratio between the S1 + S2 signal and the residual noise at each switching point is 40 dB or more, a solid-state imaging device having high image quality performance can be realized. The dynamic range performance was 100 dB. In addition, the overflow gate LO efficiently transports excess photocharges overflowing from the photodiode PD when irradiated with high-intensity light to the storage capacitor, thereby suppressing leakage of excess photocharges to adjacent pixels, and excellent blooming Resistance and smear resistance were obtained.

  In the present embodiment, a sufficiently wide dynamic range can be realized on the high illuminance side while maintaining a high S / N ratio.

(Example 2)
In the solid-state imaging device according to the present invention, a pixel block in which two photodiodes and two storage capacitors are provided in a basic pixel block having a horizontal size of 3.5 μm and a vertical size of 7 μm is formed into a two-dimensional array of 640 × vertical 240 pixels. A solid-state solid-state imaging device was prepared. The effective number of pixels is 640 × 480. The floating diffusion capacitance of each pixel block was C _FD = 3.4 fF, and the storage capacitance was C _CS = 100 fF by applying a trench type storage capacitance structure. The saturation signal voltages of the signals S1 and S1 + S2 were 500 mV and 1000 mV, respectively, and the residual noise voltages remaining in S1 and S1 + S2 after noise removal were equally 0.09 mV. The switching voltage from S1 to S1 + S2 was set lower than the saturation voltage of S1 and set to 400 mV.

  Since the S / N ratio between the S1 + S2 signal and the residual noise at each switching point is 40 dB or more, a solid-state imaging device having high image quality performance can be realized. The dynamic range performance was 110 dB. In addition, the overflow gate LO efficiently transports excess photocharges overflowing from the photodiode PD when irradiated with high-intensity light to the storage capacitor, thereby suppressing leakage of excess photocharges to adjacent pixels, and excellent blooming Resistance and smear resistance were obtained.

  In the present embodiment, a sufficiently wide dynamic range can be realized on the high illuminance side while maintaining a high S / N ratio.

  The present invention is not limited to the above description. For example, in the embodiment, the solid-state imaging device is described. However, the present invention is not limited to this, and a line sensor in which the pixels of each solid-state imaging device are arranged in a straight line or the pixels of each solid-state imaging device are configured as they are. As for the optical sensor obtained in this way, it is possible to achieve a wide dynamic range, high sensitivity, and high S / N ratio that have not been obtained in the past.

  Further, the shape of the storage capacitor is not particularly limited, and various methods developed so far to increase the capacity using the memory storage capacitor of the DRAM can be employed. The solid-state imaging device may have a configuration in which a photodiode and a storage capacitor that accumulates photoelectric charges overflowing from the photodiode are connected via an overflow gate, and can be applied to a CCD in addition to a CMOS image sensor. it can. In addition, various modifications can be made without departing from the scope of the present invention.

  The solid-state imaging device of the present invention can be applied to an image sensor that requires a wide dynamic range, such as a digital camera, a mobile phone with a camera, a surveillance camera, an in-vehicle camera, and a scanner.

  The operation method of the solid-state imaging device of the present invention can be applied to the operation method of an image sensor for which a wide dynamic range is desired.

2 is an equivalent circuit diagram of one pixel of the solid-state imaging device according to the first embodiment of the present invention. FIG. 1 is a schematic plan view of one pixel of a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view corresponding to a portion of a photodiode PD1, an overflow gate LO4, and a storage capacitor CS5 of a pixel of the solid-state imaging device according to the first embodiment of the present invention. 3 is a schematic cross-sectional view corresponding to a portion of a photodiode PD1, a transfer transistor T2, a floating diffusion FD3, a storage transistor S7, and a storage capacitor CS5 of a pixel of the solid-state imaging device according to the first embodiment of the present invention. FIG. It is a drive timing diagram of the solid-state imaging device concerning a 1st embodiment of the present invention. 1 is a block diagram of a solid-state imaging device according to a first embodiment of the present invention. It is an equivalent circuit diagram of one pixel of the solid-state imaging device concerning a 2nd embodiment of the present invention. It is a schematic plan view of one pixel of the solid-state imaging device concerning a 2nd embodiment of the present invention. It is a drive timing diagram of the solid-state imaging device concerning a 2nd embodiment of the present invention. It is an equivalent circuit diagram of one pixel corresponding to the first embodiment of the solid-state imaging device according to the third embodiment of the present invention. It is a schematic plan view of one pixel corresponding to 1st Embodiment of the solid-state imaging device which concerns on 3rd Embodiment of this invention. It is the equivalent circuit schematic of one pixel corresponding to 2nd Embodiment of the solid-state imaging device which concerns on 3rd Embodiment of this invention. It is a schematic plan view of one pixel corresponding to 2nd Embodiment of the solid-state imaging device which concerns on 3rd Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 3rd Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device which concerns on 4th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device which concerns on 4th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device which concerns on 4th Embodiment of this invention. It is an equivalent circuit diagram of two pixels of the solid-state imaging device according to the fifth embodiment of the present invention. It is a schematic plan view of 2 pixels of the solid-state imaging device concerning a 5th embodiment of the present invention. It is a drive timing diagram of the solid-state imaging device concerning a 5th embodiment of the present invention. It is an equivalent circuit schematic of four pixels of the solid-state imaging device concerning a 6th embodiment of the present invention. It is a schematic plan view of four pixels of the solid-state imaging device concerning a 6th embodiment of the present invention. It is a drive timing diagram of the solid-state imaging device concerning a 6th embodiment of the present invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is pixel sectional drawing of the solid-state imaging device concerning 7th Embodiment of this invention. It is an equivalent circuit diagram corresponding to Patent Document 1 of a conventional example. It is an equivalent circuit diagram corresponding to patent document 2 of a prior art example. It is an equivalent circuit diagram corresponding to patent document 3 of a prior art example. It is an equivalent circuit diagram corresponding to patent document 4 of a prior art example. It is an equivalent circuit diagram corresponding to Non-Patent Document 3 of a conventional example.

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Transfer transistor 3 Floating diffusion 4, LO Overflow gate 5 Storage capacity 6 Reset transistor 7 Storage transistor 8 Amplification transistor 9 Selection transistor 10 Overflow gate drive line 11 Transfer transistor drive line 12 Storage transistor drive line 13 Reset transistor Drive line 14 selection transistor drive line 15 pixel output line 20 n-type semiconductor substrate 21 p-type well 22, 23, 24, 25 element isolation insulating film 26, 27, 28, 29, 79, 93 p + type isolation region 30 n Type semiconductor region 31, 41, 50 p + type semiconductor region 32, 33, 34, 61, 61a, 70, 73, 76, 92, 95 n + type semiconductor region 35, 37, 39 Gate insulation 36, 38, 40 Gate electrode 42, 42a, 64, 68, 71, 74, 77, 80 Storage capacitor insulating film 43, 65, 69, 72, 75, 78, 81 Storage capacitor upper electrode 44 Interlayer insulating film 45, 46 , 66 wiring 51, 52, 53 n-type semiconductor region 60, 60a p + type semiconductor region or n + type semiconductor region 62 element isolation insulating film 63, 67 storage capacitor lower electrode 90 p-type semiconductor substrate 91 p-type epitaxial layer 91a first p-type Epitaxial layer 91b Second p-type epitaxial layer 94 P-type semiconductor layer 96 Low-concentration semiconductor layer 100, 101, 102, 103 Pixel array 104 Row shift register 105, HSR column shift register 106 Signal and noise hold unit 107 Output circuit

Claims (24)

A photodiode that receives light and generates a photoelectric charge;
An overflow gate that is connected to the photodiode and transfers photoelectric charges overflowing from the photodiode during a storage operation;
A storage capacitor element for storing photocharges transferred by the overflow gate during storage operation;
With optical sensor. A photodiode that receives light and generates a photoelectric charge;
An overflow gate that is connected to the photodiode and transfers photoelectric charges overflowing from the photodiode during a storage operation;
A storage capacitor element for storing photocharges transferred by the overflow gate during storage operation;
A solid-state imaging device in which a plurality of pixels having a pixel are integrated in a one-dimensional or two-dimensional array. The pixel is
A transfer transistor connected to the photodiode and transferring the photocharge;
The solid-state imaging device according to claim 2, further comprising: a floating region to which the photocharge is transferred via the transfer transistor. Photodiode that receives light to generate photocharge, transfer transistor that is connected to the photodiode and transfers the photocharge, and overflow that is connected to the photodiode and transfers the photocharge overflowing from the photodiode during storage operation A gate, and a storage capacitor element for storing the photocharge transferred by the overflow gate during the storage operation;
A plurality of pixels each having
One floating region connected to each photodiode via each transfer transistor of each pixel;
A solid-state imaging device in which a plurality of pixel blocks having a plurality of pixels are integrated in a one-dimensional or two-dimensional array. A reset transistor connected to the floating region and for discharging signal charge in the floating region and the floating region;
A transistor provided between the floating region and the storage capacitor element;
An amplification transistor for reading out the signal charge of the floating region or the signal charge of both the floating region and the storage capacitor as a voltage;
A selection transistor connected to the amplification transistor for selecting the pixel;
The solid-state imaging device according to claim 3, further comprising: A reset transistor formed to be connected to the storage capacitor element, and for discharging signal charges in the storage capacitor element and the floating region;
A transistor provided between the floating region and the storage capacitor element;
An amplification transistor for reading out the signal charge of the floating region or the signal charge of both the floating region and the storage capacitor as a voltage;
A selection transistor connected to the amplification transistor for selecting the pixel;
The solid-state imaging device according to claim 3, further comprising:   The solid-state imaging device according to claim 2, wherein the overflow gate includes a MOS transistor or a junction transistor.   The overflow gate is formed of a junction transistor, and a semiconductor region that forms a gate of the junction transistor includes a semiconductor region that forms a surface region of the photodiode, a well region in which the photodiode and the overflow gate are formed The solid-state imaging device according to any one of claims 2 to 6, wherein the solid-state imaging device is connected to.   The transfer transistor is a buried channel type having a semiconductor layer having the same conductivity type as the channel of the transfer transistor formed from the surface of the substrate constituting the transfer transistor or near the surface to a predetermined depth. The solid-state imaging device according to any one of the above.   The overflow gate has a semiconductor layer formed at a predetermined depth of a substrate constituting the overflow gate, having the same conductivity type as a channel of the overflow gate, and reducing a punch-through barrier of the overflow gate. Item 9. The solid-state imaging device according to any one of Items 2 to 8.   The storage capacitor element is formed on a semiconductor region serving as a lower electrode formed on a surface layer portion of a semiconductor substrate constituting the solid-state imaging device, a capacitor insulating film formed on the semiconductor region, and the capacitor insulating film. The solid-state imaging device according to any one of claims 2 to 10, further comprising an upper electrode formed.   The storage capacitor element includes a lower electrode formed on a substrate constituting the solid-state imaging device, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. The solid-state imaging device according to any one of claims 2 to 10.   The storage capacitor element includes a semiconductor region to be a lower electrode formed on an inner wall of a trench formed in a semiconductor substrate constituting the solid-state imaging device, a capacitor insulating film formed to cover the inner wall of the trench, The solid-state imaging device according to claim 2, further comprising an upper electrode formed by filling the trench with the capacitive insulating film interposed therebetween. A voltage signal obtained from photocharge transferred to the floating region or both the floating region and the storage capacitor;
Noise canceling means for taking a difference between the floating region or a voltage signal at a reset level of both the floating region and the storage capacitor element;
The solid-state imaging device according to claim 5 or 6, further comprising:   The solid-state imaging device according to claim 14, further comprising storage means for storing a voltage signal at a reset level of the floating region and the storage capacitor element. A photodiode that receives light and generates a photoelectric charge;
An overflow gate that is connected to the photodiode and transfers photoelectric charges overflowing from the photodiode during a storage operation;
A storage capacitor element that stores the photocharge transferred by the overflow gate during the storage operation,
The overflow sensor includes a region that lowers a potential barrier between the photodiode and the storage capacitor element. A photodiode that receives light and generates a photoelectric charge;
An overflow gate that is connected to the photodiode and transfers photoelectric charges overflowing from the photodiode during a storage operation;
A storage capacitor element that stores the photocharge transferred by the overflow gate during the storage operation,
The solid-state imaging device, wherein the overflow gate includes a plurality of pixels each having a potential region that lowers a potential barrier between the photodiode and the storage capacitor element in a one-dimensional or two-dimensional array. A photodiode that receives light and generates a photoelectric charge;
An overflow gate that is connected to the photodiode and transfers photoelectric charges overflowing from the photodiode during a storage operation;
A storage capacitor element that stores the photocharge transferred by the overflow gate during the storage operation,
The overflow gate includes a junction transistor having a gate region, and a plurality of pixels having a configuration in which the gate region of the junction transistor is grounded are integrated in a one-dimensional or two-dimensional array. Solid-state imaging device.   19. The gate region of the overflow gate according to claim 18, wherein the gate region of the overflow gate is electrically connected to a grounded region of the photodiode, whereby the gate region of the overflow gate passes through the grounded region of the photodiode. A solid-state imaging device characterized by being grounded.   20. The solid-state imaging device according to claim 18, wherein the overflow gate includes a junction transistor and a potential region that lowers a potential barrier between the photodiode and the storage capacitor element.   21. The junction transistor according to claim 17, wherein the photodiode includes a region of one conductivity type forming a pn junction and a region of reverse conductivity type, and the potential region of the overflow gate configures the overflow gate. A solid-state imaging device including a semiconductor region provided in a lower portion of the semiconductor device.   23. The solid-state imaging device according to claim 21, wherein the potential region is formed so as to partially overlap the photodiode region in the depth direction.   23. The solid-state imaging device according to claim 22, wherein the potential region includes a portion connected to the first region at a predetermined depth.   23. The solid-state imaging device according to claim 22, wherein the potential region extends beyond the gate region at a predetermined depth position.